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Chapter 5 The LC-3

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Control Instructions Used to alter the sequence of instructions (by changing the Program Counter) Conditional Branch branch is taken if a specified condition is true signed offset is added to PC to yield new PC else, the branch is not taken PC is not changed, points to the next sequential instruction Unconditional Branch (or Jump) always changes the PC TRAP changes PC to the address of an OS “service routine” routine will return control to the next instruction (after TRAP)

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Condition Codes LC-3 has three condition code registers: N -- negative Z -- zero P -- positive (greater than zero) Set by any instruction that writes a value to a register (ADD, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times Based on the last instruction that altered a register

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**Branch Instruction Branch specifies one or more condition codes.**

If the set bit is specified, the branch is taken. PC-relative addressing: target address is made by adding signed offset (IR[8:0]) to current PC. Note: PC has already been incremented by FETCH stage. Note: Target must be within 256 words of BR instruction. If the branch is not taken, the next sequential instruction is executed.

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**BR (PC-Relative) What happens if bits [11:9] are all zero? All one?**

If all zero, no CC is tested, so branch is never taken. (See Appendix B.) If all one, then all are tested. Since at least one of the CC bits is set to one after each operate/load instruction, then branch is always taken. (Assumes some instruction has set CC before branch instruction, otherwise undefined.) What happens if bits [11:9] are all zero? All one?

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**Example from last class: Multiply value stored in R2 by 15**

; initialize ; R0 <- R0 AND ; R1 <- R1 AND 0 ; code to repeat ; R1 <- R1 + R ; R0 <- R0 + 1 ; set condition codes ; R3 <- R0 – 15 ; branch if R3 < 0 because count < ; PC<- PC- 4 if n==1 R0 <- R0 AND 0 R1 <- R1 AND 0 R1 <- R1 + R2 R0 <- R0 + 1 R3 <- R0 -15 true R3 < 0? n==1 false

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**Refined Example: a better way to count**

; initialize ; R0 <- R0 AND ; R1 <- R1 AND ; R0 <- R ; code to repeat ; R1 <- R1 + R ; R0 <- R0 - 1 ; set condition codes ; R3 <- R0 – 15 ; branch if R0 >0 because count < ; PC<- PC- 3 if p==1 R0 <- R0 AND 0 R1 <- R1 AND 0 R0 <- R0 + 15 R1 <- R1 + R2 R0 <- R0 -1 true R0 > 0? p==1 false

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Iterative Do-While Loop While Loop true false

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**Multiply Using the While Loop Structure**

R0 <- R0 AND 0 ; initialize ; R0 <- R0 AND ; R1 <- R1 AND ; R0 <- R ; branch if R0== 0 because count == ; PC<- PC+3 if z==1 ; code to repeat ; R1 <- R1 + R ; R0 <- R0 - 1 ; branch unconditionally ; PC<- PC-4 R1 <- R1 AND 0 R0 <- R0 + 15 true R0 == 0? z==1 false R1 <- R1 + R2 R0 <- R0 -1 always true true false

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**Unconditional branch to retest condition**

Code for Iteration PC offset to address C Exact bits depend on condition being tested true false Unconditional branch to retest condition PC offset to address A Assumes all addresses are close enough that PC-relative branch can be used.

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Conditional If If-Else "hammock" "diamond"

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**WRONG??? If conditional Problem statement: Increment R0 if R0 < R1**

R0 <- NOT R0 ; form 2s complement of R ; R0 <- NOT R ; R0 <- R0 + 1 ; R3 <- R1 + complement of R ; R3 <- R0 + R1 ; branch if R3 is neg or ; PC<- PC+1 if z==1 or n==1 ; increment R ; halt R0 <- R0 + 1 R3 <- R0 + R1 true z==1 R3 <= 0? n==1 false R0 <- R0 +1 false

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Analyze the Situation Goal: Increment R0 if R0 < R1 R0 and R1 can each be positive or negative So increment R0 if (R1-R0) is positive and branch to skip that step if (R1-R0) is zero or negative when we don’t want to increment -> we do want to branch Assume R0 >= R1 result of (R1-R0) R0 is pos & R1 is pos zero or neg R0 is pos & R1 is neg neg R0 is neg & R1 is pos NA pos R0 is neg & R1 is neg zero, neg

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**If conditional (CORRECTED)**

Problem statement: Increment R0 if R0 < R1 ; form 2s complement of R0 & store in R ; R4 <- NOT R ; R4 <- R4 + 1 ; R3 <- R1 + complement of R0 (stored in R4) ; R3 <- R4 + R1 ; branch if R3 is neg or ; PC<- PC+1 if z==1 or n==1 ; increment R ; R0 <- R ; halt R0 <- NOT R0 R0 <- R0 + 1 R3 <- R0 + R1 true R3 <= 0? z==1 n==1 false R0 <- R0 +1 false

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**Unconditional branch to Next Subtask**

Code for Conditional PC offset to address C Exact bits depend on condition being tested Unconditional branch to Next Subtask PC offset to address D Assumes all addresses are close enough that PC-relative branch can be used.

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**JMP (Register) Jump is an unconditional branch -- always taken.**

Target address is the contents of a register. Allows any target address.

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**TRAP Calls a service routine, identified by 8-bit “trap vector.”**

When routine is done, PC is set to the instruction following TRAP. (We’ll talk about how this works later.) vector routine x23 input a character from the keyboard (IN) x21 output a character to the monitor (OUT) x25 halt the program (HALT) Warning: TRAP changes R7.

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The LC-3. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 5-2 Instruction Set Architecture ISA = All of the.

The LC-3. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 5-2 Instruction Set Architecture ISA = All of the.

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