# 1 Introduction Linus Svensson D4, Åke Östmark D4,

## Presentation on theme: "1 Introduction Linus Svensson D4, Åke Östmark D4,"— Presentation transcript:

1 Introduction Linus Svensson D4, linsve-7@student.luth.se Åke Östmark D4, akeost-6@student.luth.se

2 Why we are here Project called Design and Implementation of a 32-bit FPU in VHDL Complete project presentation fpu.varulv.net

3 Today's topics Floating-Point Unit (FPU) Design of our FPU Multiplication, an example of an algorithm Normalisation and rounding Implementation in an HDL Testing of the implementation Final result Life after SMD082 Questions

4 Floating-Point Unit (FPU) A unit providing floating-point processing capabilities Konrad Zuse had a proposal for building a computer in Germany in 1939 First commercial machine with floating-point hardware was the IBM 704 in 1955 Professor W. Kahan - Twenty years ago anarchy threatened floating-point arithmetic. Forming of the IEEE floating-point committee in 1977 The first chip manufactured in complains with the IEEE standard 754 were the Intel 8087 Math Coprocessor The Intel486 DX processor for the first time integrated the CPU and the FPU architectures on one chip

5 A possible place for the FPU FPU

6 Why an FPU LAB3 SMD082 Multiplication …... bgezal \$r0 posbrk#run posbrk on "a" nop beq \$v1 \$r0 fmulzero#if a==0 or \$s0 \$r0 \$v0#s0:=a's sign bit or \$a0 \$r0 \$v1#a0:=a's fraction or \$a1 \$r0 \$a3#a1:=a's exponent bgezal \$r0 prenrm#run prenrm on "a" nop or \$s1 \$r0 \$v0#s1:=a's fraction or \$s2 \$r0 \$v1#s2:=a's exponent lw \$a0 -8(\$fp)#fetch "b" bgezal \$r0 posbrk#run posbrk on "b" nop …... LAB3 SMD082 with an FPU Multiplication fmul \$v0 \$a1 \$a2#Done...

7 Design of our FPU We started on a high level of abstraction Defined I/O

8 Design of our FPU We divided the design into smaller blocks …

9 Design of our FPU …until we had a low level of abstraction

10 Design of our FPU Picked an existing algorithm, or modified an existing algorithm, or designed a new algorithm

11 Multiplication A = 1.112 0 = 1.75 B = 1.102 -1 = 0.75 Iter 1 – B(0) == 0 – RES := RES>>1 – RES = 0000000 Start B(i)=1 RES:=RES>>1 i:=i+1 RES:=RES+A Done i<3 0 1 0 1

12 Multiplication A = 1.112 0 = 1.75 B = 1.102 -1 = 0.75 Iter 2 – B(1) == 1 – RES := RES + A – RES = 1110000 – RES := RES>>1 – RES = 0111000 Start B(i)=1 RES:=RES>>1 i:=i+1 RES:=RES+A Done i<3 0 1 0 1

13 Multiplication A = 1.112 0 = 1.75 B = 1.102 -1 = 0.75 Iter 3 – B(2) == 1 – RES := RES + A – RES = 1010100 – RES := RES>>1 – RES = 0101010 Start B(i)=1 RES:=RES>>1 i:=i+1 RES:=RES+A Done i<3 0 1 0 1

14 Multiplication signA xor signB = 0 expA + expB = -1 man = 10.1010

15 Normalisation Express the result in normalised form Binary formDecimal form 10.10102 -1 (2.6252 -1 = 1.3125) 1.010102 0 (1.31252 0 = 1.3125)

16 Rounding The result has to many digits and must be rounded BinaryDecimal 1.010102 0 (1.3125) Identify the nearest numbers that can be represented BinaryDecimal 1.012 0 (1.25) 1.102 0 (1.50)

17 Rounding Four different round modes BinaryDecimal - Round to nearest1.012 0 1.25 - Round toward +  1.102 0 1.50 - Round toward -  1.012 0 1.25 - Round toward zero1.102 0 1.25 - Exact1.010102 0 1.3125

18 Implementation in an HDL A software programming language used to model the intended operation of a piece of hardware Two languages - Verilog - VHDL

19 What is VHDL VHSIC (Very High Speed Integrated Circuits) Hardware Description Language Created by US Department of Defence. Adopted as an IEEE standard in 1987. Latest standard is IEEE 1076 ‘93 Intended for documenting and modeling digital systems at different abstraction levels ranging from system level down to gate level

20 Main language concepts Concurrency – VHDL can describe activities that are happening in parallel Structure, hierarchy – VHDL allows to structure a design in a hierarchical manner Sequential statements – VHDL also allows sequential execution of statements. Just like any other programming language

21 VHDL example if selectX = '1’ then X <= A; else X <= B; end if;

22 VHDL example 2 if selectX = '1’ then X <= A; else X <= B; end if; if selectY = '1’ then Y <= A; else Y <= B; end if;

23 Speedup Sign, exponent and mantissa in parallel

24 Testing - Verification Verification – Are we building the product right? Bottom-up integration Testing every module on its own before integrating it into higher level modules

25 Testing - Tools used ModelSim

26 Testing - Tools used Synplify

27 Testing - Example Avoid introducing new errors in verified code A := operand_A B := operand_B C := expected_result if result is equal to C test is ok else raise flag to indicate fault in test

28 Testing - Validation Validation – Are we building the right product? What if we have misinterpreted the IEEE standard 754?

29 Testing - Validation Simulate with a test bench using Modelsim Compare the simulated result with the computed result from an UltraSparc IIi running Solaris

30 Final result Operations - addition - subtraction - division - multiplication - square root - ceiling - floor - fraction - float2integer - integer2float

31 Final result Round modes - to nearest - towards +  - towards -  - towards zero Exceptions - overflow - underflow - divide by zero - inexact operation - invalid operation

32 Final result

33 Life after SMD082 Computer Architecture / Datorarkitektur SMD077, 4p, LP2 Computation Structures / Beräkningsstrukturer SMD098, 4p, LP2 Project in Digital Synthesis / Projekt i digital syntes SMD106, 8p, LP3-4 Computer Science, Advanced course / Datateknik, fördjupningskurs SMD061-3, 2-4p, LP1-4

34 Questions