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CMPUT Compiler Design and Optimization1 CMPUT680 - Winter 2006 Topic 6: Optimal Code Generation José Nelson Amaral

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CMPUT Compiler Design and Optimization2 Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a

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CMPUT Compiler Design and Optimization3 Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a bcde

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CMPUT Compiler Design and Optimization4 Data Dependency Graph B3 a bcde f (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8);

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CMPUT Compiler Design and Optimization5 Data Dependency Graph B3 a bcdefg (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8);

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CMPUT Compiler Design and Optimization6 Data Dependency Graph B3 a bcdefg h (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8);

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CMPUT Compiler Design and Optimization7 Data Dependency Graph B3 a bcdefg h i (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8);

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CMPUT Compiler Design and Optimization8 Code Generation Problem: How to generate optimal code for a basic block specified by its DAG representation? If the DAG is a tree, we can use Sethi-Ullman algorithm to generate code that is optimal in terms of program length or number of registers used. (Aho-Sethi-Ullman,pp. 557)

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CMPUT Compiler Design and Optimization9 Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 Generate code for a machine with two registers. (Aho-Sethi-Ullman,pp. 558) Assume that only t4 is alive at the exit of the basic block.

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CMPUT Compiler Design and Optimization10 Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD a, R0 ADD b, R0 (Aho-Sethi-Ullman,pp. 558)

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CMPUT Compiler Design and Optimization11 Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 (Aho-Sethi-Ullman,pp. 558) Assume that SUB only works with registers. Can’t evaluate t3 because there are no available registers!

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CMPUT Compiler Design and Optimization12 Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 (Aho-Sethi-Ullman,pp. 558)

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CMPUT Compiler Design and Optimization13 Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 LOAD t1, R1 SUB R0, R1 STORE R1, t4 (Aho-Sethi-Ullman,pp. 558)

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CMPUT Compiler Design and Optimization14 Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 LOAD t1, R1 SUB R0, R1 STORE R1, t4 10 instructions 1 spill (Aho-Sethi-Ullman,pp. 558) Evaluation Order: t1, t2, t3, t4

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CMPUT Compiler Design and Optimization15 Example (can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD c, R0 ADD d, R0 (Aho-Sethi-Ullman,pp. 559)

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CMPUT Compiler Design and Optimization16 Example (can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0,R1 (Aho-Sethi-Ullman,pp. 559)

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CMPUT Compiler Design and Optimization17 Example (can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 (Aho-Sethi-Ullman,pp. 559)

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CMPUT Compiler Design and Optimization18 Example (can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 SUB R1, R0 STORE R0, t4 (Aho-Sethi-Ullman,pp. 559)

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CMPUT Compiler Design and Optimization19 Example (can we do better? Yes!!!) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 8 instructions no spills!!! (Aho-Sethi-Ullman,pp. 559) LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 SUB R1, R0 STORE R0, t4 Evaluation Order: t2, t3, t1, t4

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CMPUT Compiler Design and Optimization20 Example: Why the improvement? t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 t ab e cd t3 t2 t1 We evaluated t4 immediately after t1 (its leftmost argument). (Aho-Sethi-Ullman,pp. 559)

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CMPUT Compiler Design and Optimization21 Heuristic Node Listing Algorithm for a DAG (1) while unlisted interior nodes remain (2)select an unlisted node n, all of whose parents have been listed; (3)list n; (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; endwhile (Aho-Sethi-Ullman,pp. 560)

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CMPUT Compiler Design and Optimization22 Node Listing Example +-ab+c -+ed (1) while unlisted interior nodes remain (2)select an unlisted node n, all of whose parents have been listed; (3)list n;

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CMPUT Compiler Design and Optimization23 Node Listing Example +-ab+c -+ed List: 1 (1) while unlisted interior nodes remain (2)select an unlisted node n, all of whose parents have been listed; (3)list n; 8 n

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CMPUT Compiler Design and Optimization24 Node Listing Example +- ab+c -+ed (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 m n List: 1

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CMPUT Compiler Design and Optimization25 Node Listing Example +- ab+c -+ed (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; List: m n

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CMPUT Compiler Design and Optimization26 Node Listing Example +- ab +c -+ed (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; List: m n

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CMPUT Compiler Design and Optimization27 Node Listing Example +- ab+c -+ed List: (1) while unlisted interior nodes remain (2)select an unlisted node n, all of whose parents have been listed; (3)list n; 8 n

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CMPUT Compiler Design and Optimization28 Node Listing Example +- ab+c -+ed (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m List: 1 2 3

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CMPUT Compiler Design and Optimization29 Node Listing Example +- ab+c -+ed List: (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m

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CMPUT Compiler Design and Optimization30 Node Listing Example +- ab+c -+ ed (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m List:

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CMPUT Compiler Design and Optimization31 Node Listing Example +- ab+c -+ ed List: (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m

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CMPUT Compiler Design and Optimization32 Node Listing Example +- ab +c -+ ed (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m List:

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CMPUT Compiler Design and Optimization33 Node Listing Example +- ab +c -+ ed List: (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m

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CMPUT Compiler Design and Optimization34 Node Listing Example +- ab +c -+ ed List: (4)while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5)list m; (6)n := m; 8 n m

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CMPUT Compiler Design and Optimization35 Node Listing Example +- ab +c -+ ed List: (1) while unlisted interior nodes remain (2)select an unlisted node n, all of whose parents have been listed; (3)list n; n

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CMPUT Compiler Design and Optimization36 Node Listing Example +- ab +c -+ ed List: Therefore the optimal evaluation order (regardless of the number of registers available) for the internal nodes is

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CMPUT Compiler Design and Optimization37 Optimal Code Generation for Trees The order is optimal in the sense that it yields the shortest instruction sequence over all instruction sequences that evaluate the tree. If the DAG representing the data flow in a basic block is a tree, then for some machine models, there is a simple algorithm (the SethiUllman algorithm) that gives the optimal order.

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CMPUT Compiler Design and Optimization38 Sethi-Ullman Algorithm Intuition: 1. Label each node according to the number of registers that are required to generate code for the node. 2. Generate code from top down always generating code first for the child that requires the most registers.

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CMPUT Compiler Design and Optimization39 Sethi-Ullman Algorithm (Intuition) Left leaf Right leaves Bottom-Up Labeling: visit a node after all its children are labeled.

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CMPUT Compiler Design and Optimization40 Labeling Algorithm

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CMPUT Compiler Design and Optimization41 Labeling Algorithm

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CMPUT Compiler Design and Optimization42 Example ab t2 cd t1t3 e t4

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CMPUT Compiler Design and Optimization43 Example ab t2 cd t1t3 e t4 Labeling leaves: leftmost is 1, others are

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CMPUT Compiler Design and Optimization44 Example abt2 cd t1t3 e t4 Labeling t2: Thus

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CMPUT Compiler Design and Optimization45 Example abt2 cd t1t3 e t

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CMPUT Compiler Design and Optimization46 Example abt2 cd t1t3 e t Likewise labeling t1

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CMPUT Compiler Design and Optimization47 Example abt2 cd t1t3 e t

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CMPUT Compiler Design and Optimization48 Example abt2 cd t1t3 e t See Aho, Sethi, Ullman (pp. 564) for code generating algorithm.

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