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**CMPUT 680 - Compiler Design and Optimization**

CMPUT680 - Winter 2006 Topic 6: Optimal Code Generation José Nelson Amaral CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Data Dependency Graph B3 (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); a CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Data Dependency Graph B3 (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); a b c d e CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Data Dependency Graph B3 (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); a b c d e f CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Data Dependency Graph B3 (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); a b c d e f g CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Data Dependency Graph B3 (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); a b c d e f g h CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Data Dependency Graph B3 (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); a b c d e f g h i CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Code Generation Problem: How to generate optimal code for a basic block specified by its DAG representation? If the DAG is a tree, we can use Sethi-Ullman algorithm to generate code that is optimal in terms of program length or number of registers used. CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 557)

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**CMPUT 680 - Compiler Design and Optimization**

Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 Generate code for a machine with two registers. - t4 Assume that only t4 is alive at the exit of the basic block. + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

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**CMPUT 680 - Compiler Design and Optimization**

Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

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**CMPUT 680 - Compiler Design and Optimization**

Example Assume that SUB only works with registers. Can’t evaluate t3 because there are no available registers! t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

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**CMPUT 680 - Compiler Design and Optimization**

Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

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**CMPUT 680 - Compiler Design and Optimization**

Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 LOAD t1, R1 SUB R0, R1 STORE R1, t4 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

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**CMPUT 680 - Compiler Design and Optimization**

Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 LOAD t1, R1 SUB R0, R1 STORE R1, t4 1 spill - t4 Evaluation Order: t1, t2, t3, t4 + - t1 t3 e + a b t2 c d 10 instructions CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

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**Example (can we do better?)**

t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

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**Example (can we do better?)**

t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0,R1 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

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**Example (can we do better?)**

t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

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**Example (can we do better?)**

t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 SUB R1, R0 STORE R0, t4 - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

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**Example (can we do better? Yes!!!)**

t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 SUB R1, R0 STORE R0, t4 no spills!!! - t4 Evaluation Order: t2, t3, t1, t4 + - t1 t3 e + a b t2 8 instructions c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

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**Example: Why the improvement?**

t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 We evaluated t4 immediately after t1 (its leftmost argument). - t4 + - t1 t3 e + a b t2 c d CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

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**Heuristic Node Listing Algorithm for a DAG**

(1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; endwhile CMPUT Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 560)

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 + - 2 3 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example n 1 List: 1 + - 2 3 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example n 1 List: 1 m + 2 - 3 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example n 1 List: 1 2 m + 2 - 3 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 n + 2 - 3 4 - + 5 8 m + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 n + 2 - 3 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 n + 2 - 3 m 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 n + 2 - 3 m 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 + 2 - 3 n 4 m - + 5 8 + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 5 + 2 - 3 n 4 m - + 5 8 + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 5 + 2 - 3 4 n - + 5 8 m + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 5 6 + 2 - 3 4 n - + 5 8 m + c 7 6 e d 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 5 6 + 2 - 3 4 - + 5 8 n + c 7 6 e d m 11 12 a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 5 6 8 + 2 - 3 4 n - + 5 8 + c 7 6 e d 11 12 a b 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Node Listing Example 1 List: 1 2 3 4 5 6 8 + 2 - 3 4 - + 5 8 + c 7 6 e d 11 12 a b 9 10 Therefore the optimal evaluation order (regardless of the number of registers available) for the internal nodes is CMPUT Compiler Design and Optimization

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**Optimal Code Generation for Trees**

If the DAG representing the data flow in a basic block is a tree, then for some machine models, there is a simple algorithm (the SethiUllman algorithm) that gives the optimal order. The order is optimal in the sense that it yields the shortest instruction sequence over all instruction sequences that evaluate the tree. CMPUT Compiler Design and Optimization

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**Sethi-Ullman Algorithm**

Intuition: 1. Label each node according to the number of registers that are required to generate code for the node. 2. Generate code from top down always generating code first for the child that requires the most registers. CMPUT Compiler Design and Optimization

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**Sethi-Ullman Algorithm (Intuition)**

Left leaf Right leaves Bottom-Up Labeling: visit a node after all its children are labeled. CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Labeling Algorithm CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Labeling Algorithm CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example t4 t1 t3 a b e t2 c d CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example Labeling leaves: leftmost is 1, others are 0 t4 t1 t3 a b e t2 1 1 c d 1 CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example Labeling t2: Thus t4 t1 t3 a b e t2 1 1 c d 1 CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example t4 t1 t3 a b e t2 1 1 1 c d 1 CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example Likewise labeling t1 t4 t1 t3 2 a b e t2 1 1 1 c d 1 CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example t4 t1 t3 1 2 a b e t2 1 1 1 c d 1 CMPUT Compiler Design and Optimization

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**CMPUT 680 - Compiler Design and Optimization**

Example a b t2 c d t1 t3 e t4 1 2 See Aho, Sethi, Ullman (pp. 564) for code generating algorithm. CMPUT Compiler Design and Optimization

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