Index addressing (1) opcode Reg index instruction operand memory or registers operand + registers
Index addressing (2) Advantages: -Allows specification of fixed offset to operand address Disadvantages: -Extra addition to operand address Notation: ADD X(R1),R3 (X=number) Meaning: [ R3 ] [ R3 ] + M( [ R1 ] + X )
Example index addressing NENE Program with index addressing program loop sex age salary n Empoyee ID sex age salary Empoyee ID L Move #E,R0 Move N,R1 Clear R2 Add 8(R0),R2 Add #16,R0 Decrement R1 Branch>0 L Div R1,R2 Move R2,Sum Move N,R1 0(R0) 4(R0) 8(R0) 12(R0) 16(R0) 20(R0) Q1: What does this program do?
8 Arithmetic shifts C before: after: 0 1 110001... 01 11001011 R0... 0 11100.. 101. virtual: AShiftR #2,R0 AShiftR #1,R0 Arithmetic shift right (signed shift) AShiftR #2,R0 Q1: AShiftR by n bits is equivalent to division by 2 n for numbers in 2C or 1C? Q2: Rounding negative number shifts towards 0 or -infinity? Tough questions
Done so far… Circuit Design Digital logic Memory elements Other building blocks (Multiplexer,Decoder) Finite State Machines Lecture 1 Programmable Devices Memory organization Program sequencing von Neumann archi. Instruction levels Lecture 2 History of Computing (1642-2011) Why Computer Organization Matters? Lecture 0 Computers Lectures 3,4 Data representation, conversion, and op. Instruction representation and use
Problem: How to Program Computers? Circuit Design Digital logic Memory elements Other building blocks (Multiplexer,Decoder) Finite State Machines Lecture 1 Programmable Devices Memory organization Program sequencing von Neumann archi. Instruction levels Lecture 2 Why Computer Organization Matters? Lecture 0 Computers Lectures 3,4 Data representation, conversion, and op. Instruction representation and use
TU-Delft TI1400/11-PDS 13 Program Creation and Execution Flow editor type source program Source in ASCII linker/loader link/load memory image runinput/ output machine 2 assemblerlisting translate Source and Object code +error messages object code machine 1
Three levels of instructions fetch/execute implementation program execution in hardware high level programming language program expressed in a high-level language translation instruction set program expressed as a series of instructions direct implementation Assembler C/C++, Java, …
15 Instructions and Addressing 1.Introduction 2.Assembler: What and Why? 3.Assembler Statements and Structure 4.The Stack 5.Subroutines 6.Architectures: CISC and RISC
TU-Delft TI1400/11-PDS 16 Why assembler? [1/2] Assembler is a symbolic notation for machine language It improves readability (vs machine code): -Assembler: Move R0,SUM -Machine code: 0010 1101 1001 0001 (16 bits)
TU-Delft TI1400/11-PDS 17 Why assembler ? [2/2] Speed of programs in critical applications Access to all hardware resources of the machine Target for compilers Source: http://www.cs.berkeley.edu/~volkov/cs267.sp09/hw1/results/ Lecture 0
Q: Where to get ISA references? Manufacturer’s documentation Third-party manuals (ATTN: may be incorrect)
Q: Does each processor have its own machine language (instruction set)? Shared across generations and even competitors www.eng.ucy.ac.cy/theocharides/Courses/ECE656/ia-32.pdf developer.download.nvidia.com/compute/cuda/3_1/toolkit/docs/ptx_isa_2.1.pdf 1982 1985 1989 1993 1995 Intel AMD Cyrix … NVIDIA
Q: Are similar instructions identical on different platforms? Often, they are not NVIDIA Intel AMD Cyrix
TU-Delft TI1400/11-PDS 21 Machine Language [1/4] Is Machine language difficult to learn? -That holds for every unknown language. Machine language is more difficult because you have to work with the specifically defined micro instruction set. Is Machine language difficult to read and to understand? -Of course, if you do not know the language; however, assembler is more difficult to read and understand than a High Level Language (HLL).
TU-Delft TI1400/11-PDS 22 Machine Language [2/4] Is Machine language difficult to write? -Often HLL languages use libraries to make programming simpler. Machine language programmers often start from scratch. However, full performance may require machine language implementation (or a smart/expensive compiler) Machine language programming is time consuming -One estimates that the time for coding a program is only 30% of the total development time.
TU-Delft TI1400/11-PDS 23 Machine Language [3/4] Compilers make machine language superfluous -A good machine language program often looks very different from a compiler generated program. Generally, a C program will win over a hand-made assembly program (unless you’re Michael Abrash … or a student at TU Delft) -Assembler still heavily used for hot/optimized functions (esp. scientific codes), real-time platforms, embedded systems, …
TU-Delft TI1400/11-PDS 24 Machine Language [4/4] Is Machine language difficult to maintain? -Maintainable programs are not specifically dependent on the language they are written in, but more on the way they are contructed Is Machine language difficult to debug? -Often debuggers output both the HLL and the machine language, and the error can only be found in the generated machine language
TU-Delft TI1400/11-PDS 26 Case U niversele B rander A utomaat Klant:Nefit Fasto B.V. Markt :HVAC (AirCo) Ontwikkelen (1990) en produceren (100k/jaar) van de UBA universele brander- automaat voor Nefit Fasto voorzien van een bipolaire Application-Specific Integrated Circuit (ASIC). Eerste product met een universeel karakter, die een fail-safe approval heeft.
TU-Delft TI1400/11-PDS 27 Case 6 schakel ingangen 8 analoge ingangen 3 schakeluitgangen 3 modulerende uitgangen 2 draads communicatie bus Externe KIM module aansluiting met 178 bytes config settings 230V, Pump and Fan ASIC and micro-Computer Ignition U niversele B rander A utomaat
TU-Delft TI1400/11-PDS 30 UBA PuR After Power up Reset special routine [ see also The Zen of Diagnostics, http://www.ganssle.com/articles/adiags1.htm ] - all instruction set in test routine - 16-bit CRC (99,98% data integrity) - Walking A0 and 05 RAM test (pattern sensitivity) - Check on A/D (converter linearity) - Main loop partitioned in modules - Module check in each phase - Acknowledge module check by pulse to ASIC (350ms) - Interrupt program termination check by pulse to ASIC (20ms)
TU-Delft TI1400/11-PDS 31 UBA Assembly Check instruction set -Test of each opcode over and over again -Emergency stop at fault detection -Not possible in “C” Check memory -As part of the program -Emergency stop at fault detection -Difficult in “C” Better control on application -Compiler generated code must be checked for correctness.
TU-Delft TI1400/11-PDS 32 Instructions and Addressing 1.Introduction 2.Assembler: What and Why? 3.Assembler Statements and Structure 4.The Stack 5.Subroutines 6.Architectures: CISC and RISC
TU-Delft TI1400/11-PDS 33 Assembler Statements Declarations -no code generation -memory reservation -symbolic data declarations -where to start the code execution Executable statements -are translated to real machine instructions (often, one-to-one)
TU-Delft TI1400/11-PDS 36 Memory lay-out Move N,R1 100..... 102 103 104 105 106 107 101..... Branch >0 200 300 202 203 501 201..... Nn S N N1
TU-Delft TI1400/11-PDS 37 Structure assembler [1/3] Assembler is hardly more than substitution -substitute 0001 for Move -substitute 0000 0000 0000 0101 for #5 Assembler is level above machine language Assembler languages for different architectures are alike, but not identical
TU-Delft TI1400/11-PDS 38 Structure assembler [2/3] Assembler programs contain three kind of quantities: Absolute: -opcodes, contants: can be directly translated Relative: -addresses of instructions which are dependent of final memory location Extern: -call to subroutines
TU-Delft TI1400/11-PDS 39 Structure assembler [3/3] Literals: constants in programs Some assemblers act as if literals are immediate operands Example: Load #1 is equivalent to: Load One... One: 1
TU-Delft TI1400/11-PDS 40 Number notation Numbers can be represented using various formats: ADD #93,R1 or ADD #%01011101,R1 or ADD #$5D,R1
TU-Delft TI1400/11-PDS 41 Instructions and Addressing 1.Introduction 2.Assembler: What and Why? 3.Assembler Statements and Structure 4.The Stack 5.Subroutines 6.Architectures: CISC and RISC
TU-Delft TI1400/11-PDS The Stack Main idea -(Large?) Memory space used to store program data -Items are added to the stack through a PUSH operation -Items are removed from the stack through a POP operation Details -Often, a stack is a contiguous array of memory locations -Often, any number of stacks can be set up by a program -Often, only one stack can be used at a time (changing the active stack possible at any time) Q1: Why use stacks?Q2: Implications?
TU-Delft TI1400/11-PDS 43 Stack registers SP PC CPU Main Memory Stack Pointer
TU-Delft TI1400/11-PDS 53 Parameter passing (1) Through registers -fast -limited number of parameters -caller and callee must know where parameters are placed Example: Move A,R0Sub:Move R0,C Call Sub...... RTS
TU-Delft TI1400/11-PDS 54 Parameter passing (2) Through memory -very flexible -slower than through registers Often implemented through Stack Pointer Parameters are pushed on stack before calling subroutine Results are popped from stack after return Subroutine needs registers
TU-Delft TI1400/11-PDS 66 Frame Pointer SP (stack pointer) FP (frame pointer) saved [R1] saved [R0] Stack frame for called subroutine Return address localvar3 localvar2 localvar1 saved [FP] Old ToS param2 param1 param3 param4 (top-of-stack) Access of local variables of Subroutine through Index Addressing on FP
TU-Delft TI1400/11-PDS 67 Re-entrancy Subroutines can be called more than once -Recursion: subroutine calls itself -Sub A calls Sub B, which in turn calls Sub A -Multiple callers “at the same time” Special measures for re-entrancy -No change of instructions -Each caller must have its own copy of data -Use stack(s)
TU-Delft TI1400/11-PDS 68 Instructions and Addressing 1.Introduction 2.Assembler: What and Why? 3.Assembler Statements and Structure 4.The Stack 5.Subroutines 6.Architectures: CISC and RISC
TU-Delft TI1400/11-PDS 69 CISC characteristics Complex Instruction Set Traditional architectures Powerful instructions -Complex operations -Many instructions Memory to memory operations Programs often use stacks Examples 68xxx and 80xxx architectures The Pentium architecture Memory CPU
TU-Delft TI1400/11-PDS 70 RISC characteristics Reduced Instruction Set Small number of instructions Load/Store from memory Operations between registers Large register sets Example PowerPC architecture Memory CPU
TU-Delft TI1400/11-PDS Pro CISC Easier to program Reduced code size Complexity in hardware not in software -HLL support in hardware (Politics) Legacy -CISCs are in all our PCs and servers See also: http://arstechnica.com/cpu/4q99/risc-cisc/rvc-5.html
TU-Delft TI1400/11-PDS Con CISC Instruction encoding complex Variable number of cycles to load instruction -IA-32 instructions can be 1—17 bytes long Many instructions too specific, thus not used May be slow -Stacks are in main memory, registers are near processor May consume more energy -Not in embedded systems, portable devices, …
TU-Delft TI1400/11-PDS Frequency of Instruction Use Frequency of Use (logscale) Instruction Rank Source: http://www.eng.ucy.ac.cy/theocharides/Courses/ECE656/ia-32.pdf 50% code just 3 instructions (mov, call, jmp) 99% code under 50 instructions