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April 12, 2015 The NS7520. 2 NET+ARM ARM7TDMI Programmer’s Model.

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Presentation on theme: "April 12, 2015 The NS7520. 2 NET+ARM ARM7TDMI Programmer’s Model."— Presentation transcript:

1 April 12, 2015 The NS7520

2 2 NET+ARM ARM7TDMI Programmer’s Model

3 3 Processor Operating States The ARM7TDMI can be in one of two Processor Operating States: - ARM state which executes 32-bit, word-aligned ARM instructions - Thumb state which operates with 16-bit, halfword-aligned Thumb instructions. Note: Transition between these two states does not affect the operating mode (user, supervisor, …) or the contents of the registers

4 4 Switching between OP States Entering Thumb state: - Execute a BX instruction with the state bit (bit 0) set in the operand register - Transition also occurs automatically when returning from an exception if this was entered with the processor in Thumb state Entering ARM state - Execute a BX instruction with the state bit clear in the operand register - Also occurs on the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI, etc.) BX = Branch and Exchange (Operating State)

5 5 Memory Formats ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first word, bytes 4 to 7 the second and so on. The ARM7TDMI can treat words in memory as being stored either in - Big Endian format (also known as Motorola format) - Little Endian format (also known as Intel format)

6 6 Big Endian Format Word Address Lower Address Higher Address Most Significant Byte is at lowest address Word is addressed by byte address of most significant byte

7 7 Little Endian Format Word Address Lower Address Higher Address Least Significant Byte is at lowest address Word is addressed by byte address of least significant byte

8 8 Instruction Length and Data Types ARM7TDMI Instruction Length is - 32 bits in ARM state - 16 bit in Thumb state ARM7TDMI supported datatypes are: - byte (8-bit) - halfword (16-bit) - word (32-bit) Words must be aligned to four-byte boundaries and halfwords at two-byte boundaries

9 9 ARM7TDMI Registers ARM7TDMI has a total of 37 registers - 31 general purpose 32-bit registers - 6 status registers Not all registers can be seen at once! The processor state and operating mode dictate which registers are available to the programmer

10 10 ARM State Register Set 16 general registers and one or two status registers are visible at one time Mode-specific banked registers are switched in in privileged, non-User modes Dedicated registers are: - R14 receives a copy of R15 when a Branch with Link instruction ( BL ) is executed. - R15 holds the Program Counter - R16 is the CPSR (Current Program Status Register) This contains the condition code flags and the current mode bits.

11 11 ARM State Register Set R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP LR PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq SP_fiq LR_fiq PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_svc LR_svc PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_abt LR_abt PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_irq LR_irq PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_und LR_und PC CPSR SPSR_fiqSPSR_svcSPSR_abtSPSR_irqSPSR_und System & UserFIQSupervisorAbortIRQUndefined Banked Registers

12 12 Thumb State Register Set R0 R1 R2 R3 R4 R5 R6 R7 PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 CPSR R0 R1 R2 R3 R4 R5 R6 R7 CPSR R0 R1 R2 R3 R4 R5 R6 R7 CPSR R0 R1 R2 R3 R4 R5 R6 R7 CPSR SPSR_fiqSPSR_svcSPSR_abtSPSR_irqSPSR_und System & UserFIQSupervisorAbortIRQUndefined SP LR SP_fiq LR_fiq SP_svc LR_svc SP_abt LR_abt SP_irq LR_irq SP_und LR_und PC Banked Registers

13 13 State Switching R0 R1 R2 R3 R4 R5 R6 R7 Stack Pointer (SP) Link Register (LR) Program Counter (PC) CPSR SPSR Thumb State R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Stack Pointer (SP) Link Register (LR) Program Counter (PC) CPSR SPSR ARM State

14 14 Accessing R8..R12 in Thumb state R8..R12 are not part of the standard Thumb register set. There is limited access to R8..R12 in Thumb state, using special variants of the MOV instruction. R8..R12 can be compared against or added to R0..R7 using CMP and ADD instructions Conclusion: R8..R12 may have changed when switching back to ARM state.

15 15 The Program Status Registers The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSR). These - hold Information about the most recently performed ALU operation - control the enabling and disabling of Interrupts - set the Processor operating mode N 31 Z 30 C 29 V I 7 F 6 T 5 M4 4 M3 3 M2 2 M1 1 M0 0 Overflow Carry/Boorow Zero Negative Mode State FIQ disable IRQ disable Control BitsreservedCondition Code

16 16 Condition Codes N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed. In ARM state a l l instructions may be executed conditionally In Thumb state, only the Branch instruction is capable of conditional execution

17 17 Control Bits The T-bit Reflects the operating state and is set when in Thumb The Interrupt disable bits Are used to mask (disable) the IRQ and FIQ interrupts The mode bits M4..M0 determine the operating mode. Not all combinations define a valid operating mode – Illegal values programmed into the mode bits will cause the processor enter an unrecoverable state. If this happens, a reset should be applied. Reserved bits Should never be altered.

18 18 Operating Mode Summary M4:M0ModeVisible Thumb state registers Visisble ARM state registers 0b10000UserR7..R0 LR, SP PC, CPSR R14..R0 PC, CPSR 0b10001FIQR7..R0 LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0 R14_fiq..R8_fiq PC, CPSR, SPSR_fiq 0b10010IRQR7..R0 LR_irq, SP_irq PC, CPSR, SPSR_irq R12..R0 R14_irq..R13_irq PC, CPSR, SPSR_irq 0b10011SupervisorR7..R0 LR_svc, SP_svc PC, CPSR, SPSR_svc R12..R0 R14_svc..R13_svc PC, CPSR, SPSR_svc 0b10111AbortR7..R0 LR_abt, SP_abt PC, CPSR, SPSR_abt R12..R0 R14_abt..R13_abt PC, CPSR, SPSR_abt 0b11011UndefinedR7..R0 LR_und, SP_und PC, CPSR, SPSR_und R12..R0 R14_und..R13_und PC, CPSR, SPSR_und 0b11111SystemR7..R0 LR, SP PC, CPSR R14..R0 PC, CPSR

19 19 Exceptions (1) Actions on entering an exception - Save return address in the appropriate LR Return address is either current PC + 4 or current PC +8 (depending on the exception) - Copy the CPSR into the appropriate SPSR - Force the CPSR mode bits to a value which depends on the exception - Load PC to fetch next instruction from the relevant exception vector Note: If the processor is in Thumb state when an exception occurs, it will automatically switch into ARM state when the PC is loaded with the exception vector address.

20 20 ARM State Register Set R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP LR PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq SP_fiq LR_fiq PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_svc LR_svc PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_abt LR_abt PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_irq LR_irq PC CPSR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP_und LR_und PC CPSR SPSR_fiqSPSR_svcSPSR_abtSPSR_irqSPSR_und System & UserFIQSupervisorAbortIRQUndefined Banked Registers Saved CPSR CPSR PC Saved PC CPSR PC

21 21 Exceptions (2) Actions when leaving an exception - Load PC, minus an offset where appropriate, from LR (offset will vary depending on the exception) - Copy the SPSR back into the CPSR Note: An explicit switch back to Thumb state is not required, since restoring the CPSR from the SPSR automatically sets the T-bit to the value it held immediately prior to the exception.

22 22 Exception entry/exit Summary Return InstructionPrevious State ARM R14_xThumb R14_x BLMOV PC,R14PC+4PC+2 SWIMOVS PC, R14_svcPC+4PC+2 UNDEFMOVS PC, R14_undPC+4PC+2 FIQSUBS PC, R14_fiq, #4PC+4 IRQSUBS PC, R14_irq, #4PC+4 PABTSUBS PC, R14_abt, #4PC+4 DABTSUBS PC, R14_abt, #8PC+8 RESETNA--

23 23 Exception Vectors and Priority AddressExceptionMode on entryPriority 0x0ResetPC+41 0x4Undefined InstructionPC+46* 0x8Software InterruptPC+46* 0xcPrefetch AbortPC+45 0x10Data AbortPC+42 0x14reservedPC+4NA 0x18IRQPC+84 0x1cFIQ-3 Note: Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decodings of the current instruction.

24 24 Interrupt Latencies T D = T syncmax + T ldm + T fiq T syncmax is 5 clock cycles T ldm is the time for the longest instruction to complete (which is the LDM instruction) and is 23 cycles T fiq is the time for the FIQ entry and is 2 clock MHz this will give a total of 30 clocks (less than 1us) for the processor to execute the FIQ Instruction at address 0x1c.

25 25 Q & A


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