3 Sections 5.1 Immediate and register addressing modes 5.2 Accessing memory using various address modes 5.3 Bit addresses for I/O and RAM 5.4 Extra-128-byte on-chip RAM in 8052
4 Section 5.1 Immediate and Register Addressing Modes
5 What is Addressing Mode The CPU can access data in various ways. The data could be in a register, or in memory （ RAM or ROM ）, or be provided as an immediate value. These various ways of accessing data are called addressing mode.
6 Addressing Mode in the 8051 Five addressing mode in the 8051 ： 1. immediate 2. register 3. direct 4. register indirect 5. indexed –We use MOV as an example. One can use any instruction as long as that instruction supports the addressing mode.
7 Addressing Mode 1 1. immediate － the operand is a constant MOV A,#01FH 2. register － the operand is in a register MOV A,R0 3. direct － access the data in the RAM with address MOV A,01FH 4. register indirect － the register holds the RAM address of the data MOV A,@R0 5. indexed － for on-chip ROM access MOVC A,@A+DPTR
8 Immediate Addressing Mode The source operand is a constant. The immediate value can be loaded into any of the registers. –The immediate data must be preceded by the pound sign, ‘ ＃ ’. –The immediate value is bounded by the size of register. –Please use the simulation tools to find the the machine code and the content of registers after execution. –See Tables 10 ＆ 11 (page 614). When the instruction is assembled, the operand comes immediately after the opcode.
9 Example of Immediate Mode （ 1/2 ） Immediate Mode ： 1 0000 74 25 MOV A,#25H ;A=25H 2 0002 7C 3E MOV R4,#62 ;R4=62=3EH Instruction Opcodes in Table 11 Hex code Mnemonic Operands Byte 74 MOV A, #data 2 7C MOV R4, #data 2 Instruction Opcodes in Table 10 Mnemonic Oscillator Period MOV A, #data 12 MOV Rn, #data 12
11 EQU (1/2) The EQU directive is used in the immediate addressing mode. 1 0000 ORG 0H 2 0000 COUNT EQU 30 3 0000 7C 1E MOV R4,#COUNT 4 0002 90 02 00 MOV DPTR,#MYDATA 5 0200 ORG 200H 6 0200 41 6D 65... MYDATA:DB "America" 7 0207 END
12 EQU (2/2) In Pass 1, assembler reads these directives and creates a table: COUNT 1EH MYDATA 200H In Pass 2, assembler transfers COUNT and MYDATA into numbers and creates machine codes: MOV R4,#COUNT → 7C 1E MOV DPTR,#MYDATA → 90 02 00
13 Addressing Mode 2 1. immediate － the operand is a constant MOV A,#01FH 2. register － the operand is in a register MOV A,R0 3. direct － access the data in the RAM with address MOV A,01FH 4. register indirect － the register holds the RAM address of the data MOV A,@R0 5. indexed － for on-chip ROM access MOVC A,@A+DPTR
14 Register Addressing Mode Register addressing mode involves the use of registers to hold the data. –Register means Rn, A & CY. –The source and destination registers must match in size. –The movement of data between Rn registers is not allowed. “MOV R4,R7” is illegal. You can find that the opcode in register addressing mode is short ！
15 Example of Register Mode （ 1/2 ） Register Mode ： 1 0000 E8 MOV A,R0 2 0001 FA MOV R2,A 3 0002 2D ADD A,R5 Instruction Opcodes in Table 11 Hex code Mnemonic Operands Byte E8 MOV A,R0 1 FA MOV R2,A 1 2D ADD A,R5 1
16 Example of Register Mode （ 2/2 ） Register Mode ： 1 0000 E8 MOV A,R0 2 0001 FA MOV R2,A 3 0002 2D ADD A,R5 Instruction Opcodes in Table 10 Mnemonic Oscillator Period MOV A, Rn 12 MOV Rn, A 12 ADD A, Rn 12
17 Section 5.2 Accessing Memory Using Various Address Modes
18 Addressing Mode 3 1. immediate － the operand is a constant MOV A,#01FH 2. register － the operand is in a register MOV A,R0 3. direct － access the data in the RAM with address MOV A,01FH 4. register indirect － the register holds the RAM address of the data MOV A,@R0 5. indexed － for on-chip ROM access MOVC A,@A+DPTR
19 Direct Addressing Mode (1/2) There are 128 bytes of RAM in the 8051. The RAM has been assigned address 00 - 7FH. –00-1FH ： the register banks and stack –20-2FH ： bit-addressable space to save single-bit data –30-7FH ： scratch pad RAM There is no name for some RAM locations -- so we need to use direct address mode to access them. If an number begins without a pound sign, ‘ ＃ ’, then Assembler think it as the RAM address.
20 Direct Addressing Mode (2/2) In direct addressing mode, the data is in a RAM memory location whose address is known, and this address is given as a part of the instruction. We can use the direct addressing mode to access –128-byte on chip RAM –Special Function Registers (they are RAM addresses too.)
21 Example of Direct Mode （ 1/2 ） Direct Mode ： 1 0000 A8 40 MOV R0,40H 2 0002 F5 56 MOV 56H,A 3 0004 90 45 21 MOV DPTR,#4521H 4 0007 75 83 45 MOV DPH,#45H 5 000A 75 82 21 MOV DPL,#21H Instruction Opcodes Table 11 Hex code Mnemonic Operands Bytes A8 MOV R0, data addr. 2 F5 MOV data addr., A 2 75 MOV data addr., #data 3
22 Example of Direct Mode （ 2/2 ） Direct Mode ： 1 0000 A8 40 MOV R0,40H 2 0002 F5 56 MOV 56H,A 3 0004 90 45 21 MOV DPTR,#4521H 4 0007 75 83 45 MOV DPH,#45H 5 000A 75 82 21 MOV DPL,#21H Instruction Opcodes Table 10 Mnemonic Oscillator Period MOV Rn, direct 24 MOV direct, A 12 MOV direct, #data 24
23 Register Bank （ 1/2 ） If we use register bank 0, then the following instructions 2 ＆ 3 do the same works ： 1 0000 7C 64 MOV R4,#100 2 0002 E5 04 MOV A,4 ;direct mode 3 0004 EC MOV A,R4 ;register mode –Initially, the 8051 uses the register bank 0. –R4 has RAM address 04H.
24 Register Bank （ 2/2 ） If we use register bank 1, then the following instructions 3 ＆ 4 do the different works ： 1 0000 D2 D3 SETB RS0 ;RS0=1 2 0002 7C 64 MOV R4,#100 3 0004 E5 04 MOV A,4 ;A=0 4 0006 EC MOV A,R4 ;A=100=64H –RS1=PSW.4=0 ＆ RS0=PSW.3=1 register bank 0 –The bit address of RS0 is D3. –Initially, the content of RAM is 00H. –R4 has RAM address 0CH. –RAM 0CH has the value 100.
25 SFR （ Special Function Register ） There are many special functions registers in the 8051. We call them SFR. –Example ： A, B, PSW, and DPTR The 8051 Assembler provides that the SFR can be accessed by their name or by their addresses. –See Table 5-1 for SFR addresses –The SFR have addresses between 80H and FFH. –Not all the address space of 80H to FFH is used by the SFR.
27 Table 5-1: Special Function Register (SFR) Addresses （ 2/2 ） SymbolNameAddress TCON*Timer/counter control88H T2CON*Timer/counter 2 control0C8H T2MODTimer/counter mode control0C9H TH0Timer/counter 0 high byte8CH TL0Timer/counter 0 low byte8AH TH1Timer/counter 1 high byte8DH TL1Timer/counter 1 low byte8BH TH2Timer/counter 2 high byte0CDH TL2Timer/counter 2 low byte0CCH RCAP2HT/C 2 capture register high byte0CBH RCAP2LT/C 2 capture register low byte0CAH SCON*Serial control98H SBUFSerial data buffer99H PCONPower control87H *bit addressable (discussed further in Chapter 8)
28 ACC and Its Address ACC has SFR address 0E0H. 1 0000 75 E0 55 MOV 0E0H,#55H 2 0003 74 55 MOV A,#55H 3 0005 D2 E1 SETB A.1 –Compare their code size and execution time. “ACC ＊ ”, ＊ means this register is bit addressable. You can access each bit of ACC independently. A.6A.5A.4A.3A.2A.1 A.7 A.0 ACC SFR addr. 0E7 0E6 0E5 0E4 0E3 0E2 0E1 0E0
29 Example 5-1 Write code to send 55H to ports P1 and P2, using (a) their names (b) their addresses. Solution: (a) MOV A,#55H ;A=55H MOV P1,A ;P1=55H MOV P2,A ;P2=55H (b) From Table 5-1, P1 address = 90H; P2 address = A0H MOV A,#55H ;A=55H MOV 90H,A ;P1=55H MOV 0A0H,A ;P2=55H
30 Stack Another major use of direct addressing mode is the stack. In the 8051 family, only direct addressing mode is allowed for pushing onto the stack or for popping from the stack.
31 Example 5-2 Show the code to push R5, R6, and A onto the stack and then pop them back them into R2, R3, and B. We want ： B = A, R2 = R6, and R3 = R5. Solution: ; Register bank 0 PUSH 05 ;push R5 onto stack C0 05 PUSH 06 ;push R6 onto stack C0 06 PUSH 0E0H ;push register A onto stack POP 0F0H ;pop top of stack into register B POP 02 ;pop top of stack into R2 POP 03 ;pop top of stack into R3
32 Addressing Mode 4 1. immediate － the operand is a constant MOV A,#01FH 2. register － the operand is in a register MOV A,R0 3. direct － access the data in the RAM with address MOV A,01FH 4. register indirect － the register holds the RAM address of the data MOV A,@R0 5. indexed － for on-chip ROM access MOVC A,@A+DPTR
33 Register Indirect Addressing Mode In the register indirect addressing mode, a register is used as a pointer to the data. –That is, this register holds the RAM address of the data. Only registers R0 and R1 can be used to hold the address of an operand located in RAM. –Usually, R0 and R1 are denoted by Ri. When R0 and R1 hold the addresses of RAM locations, they must be preceded by the “@” sign.
34 Example of Register Indirect Mode （ 1/2 ） Register Indirect Mode ： 1 0000 75 20 64 MOV 20H,#100 2 0003 78 20 MOV R0,#20H 3 0005 E6 MOV A,@R0 R0 20H A 64H RAM 1E 00 1F 00 20 64 21 00 22 00 23 : 1. put 64H to addr. 20H 2. let R0 be the data address 3. copy the content in addr. R0=20H to A
35 Example of Register Indirect Mode （ 2/2 ） Register Indirect Mode ： 1 0000 75 F0 80 MOV B,#080H 2 0003 79 31 MOV R1,#31H 3 0005 A7 F0 MOV @R1,B R1 31H B 80H RAM 2F 00 30 00 31 80 32 00 33 00 34 : 1. let B=80H 2. let R1 be the data address 3. copy B to the RAM location with addr. R1=31H
36 Example 5-3 (1/3) Write a program to copy the value 55H into RAM memory locations 40H to 44H using (a) direct addressing mode, (b) register indirect addressing mode without a loop, (c) with a loop. Solution of (a) : MOV A,#55H MOV 40H,A MOV 41H,A MOV 42H,A MOV 43H,A MOV 44H,A A 55H RAM 40 55 41 55 42 55 43 55 44 55 45 00 copy A to the RAM location of addr. 43H
37 Example 5-3 (2/3) Solution of (b) register indirect addressing mode without a loop MOV A,#55H ;load A with value 55H MOV R0,#40H ;load the pointer. R0=40H MOV @R0,A ;copy A to RAM location where R0 ; points to INC R0 ;increment pointer. Now R0=41H MOV @R0,A INC R0 ;R0=42H MOV @R0,A INC R0 ;R0=43H MOV @R0,A INC R0 MOV @R0,A R0 42H A 55H RAM 40 55 41 55 42 55 43 00 44 00 45 00
38 Example 5-3 (3/3) Solution of (c) with a loop: MOV A,#55H ;A=55H MOV R0,#40H ;load pointer. R0=40H, MOV R2,#05H ;load counter, R2=5 AGAIN: MOV @R0,A ;copy 55 to RAM location ; R0 points to INC R0 ;increment R0 pointer DJNZ R2,AGAIN ;loop until counter = 0
39 Advantage of Register Indirect Addressing Mode One of the advantages of register indirect addressing mode is that it makes accessing data dynamic rather than static. (Flexible!) Solution (c) in Example 5-3 is the most efficient and is possible only because of register indirect addressing mode. –Looping is not possible in direct addressing mode. –See Examples 5-4, 5-5, too. Their use is limited to accessing any information in the internal RAM.
40 Example 5-4 Write a program to clear 16 RAM locations starting at RAM address 60H. Solution: CLR A ;A=0 MOV R1,#60H ;load pointer. R1=60H MOV R7,#16 ;load counter, R7=10H AGAIN: MOV @R1,A ;clear RAM location R1 ; points to INC R1 ;increment R1 pointer DJNZ R7,AGAIN ;loop until counter = 0
41 Example 5-5 Write a program to copy a block of 10 bytes of data from RAM locations starting at 35H to RAM locations starting at 60H. Solution: MOV R0,#35H ;source pointer MOV R1,#60H ;destination pointer MOV R3,#10 ;counter BACK: MOV A,@R0 ;get a byte from source MOV @R1,A ;copy it to destination INC R0 ;increment source pointer INC R1 ;increment destination ; pointer DJNZ R3,BACK ;keep doing it 10 times
42 Addressing Mode 5 1. immediate － the operand is a constant MOV A,#01FH 2. register － the operand is in a register MOV A,R0 3. direct － access the data in the RAM with address MOV A,01FH 4. register indirect － the register holds the RAM address of the data MOV A,@R0 5. indexed － for on-chip ROM access MOVC A,@A+DPTR
43 Indexed Addressing Mode Indexed addressing mode is used to access 8051 on-chip ROM. It is widely used in accessing data elements of look-up table entries located in the program ROM space of the 8051. –A look-up table is a ROM block where the data is given previously (then you can access it frequently). –Ex: MOVC A,@A+DPTR
44 MOVC MOVC : to access internal ROM –Transfer data between internal ROM and A. –The “C” means code 16-bit memory address is held by DPTR or PC MOV DPTR,#0008 ;ROM address MOVC A,@A+DPTR ;access the ROM data with address A+DPTR MOVC A,@A+PC ;access the ROM data with address A+PC
45 Example of MOVC Register Indexed addressing Mode ： 1 0000 90 00 08 MOV DPTR,#MYDATA 2 0003 E4 CLR A 3 0004 93 MOVC A,@A+DPTR 4 0005 F8 MOV R0,A 5 0006 80 FE HERE: SJMP HERE 6 0008 55 53 41 MYDATA: DB "USA" –DPTR=#MYDATA=0008H –A+DPTR=0008H ROM 0000 90 0001 00 0002 08 0003 E4 0008 55 0009 53 000A 41 A 55H
46 MOVX MOVX : to access external RAM/ROM connected to the 8051 –Transfer data between external memory and A. –See Chapter 14 in page 431. –The “X” means external (memory space must be implemented externally). –Note: RAM can be read and write. 16-bit external memory address is held by DPTR MOVX A,@DPTR or MOVX @DPTR,A 8-bit external memory address is held by R0/R1 MOVX A,@Ri or MOVX @Ri,A
47 Example 5-6 (1/2) In this program, assume that the word “USA” is burned into ROM locations starting at 200H, and that the program is burned into ROM locations starting at 0. Analyze how the program works and state where “USA” is stored after this program is run. Solution: ROM 0000 90 0001 02 0002 00 0003 E4 : 0200 55 0201 53 0202 41 A 55H Clear A=0 A+DPTR= 0200H DPTR 02H 00H R0 55H USAUSA R1 00H R2 00H
48 Example 5-6 (2/2) ORG 0000H ;burn into ROM from 0 MOV DPTR,#200H ;DPTR=0200H CLR A ;clear A(A=0) MOVC A,@A+DPTR ;get the char space MOV R0,A ;save it in R0 INC DPTR ;DPTR=201 CLR A ;clear A(A=0) MOVC A,@A+DPTR ;get the next char MOV R1,A ;save it in R1 INC DPTR ;DPTR=202 CLR A ;clear A(A=0) MOVC A,@A+DPTR ;get the next char MOV R2,A ;save it in R2 HERE:SJMP HERE ;stay here ORG 200H MYDATA: DB “USA” END ;end of program
49 Example 5-7 (1/2) Assuming that ROM space starting at 250H contains “America”, write a program to transfer the bytes into RAM locations starting at 40H. Solution of (a) This method uses a counter ： ORG 0000 MOV DPTR,#MYDATA ;Initialization MOV R0,#40H MOV R2,#7 BACK: CLR A MOVC A,@A+DPTR MOV @R0,A INC DPTR INC R0 DJNZ R2,BACK HERE: SJMP HERE ORG 250H MYDATA: DB “AMERICA” END ROM 0000 90 0001 02 0002 50 0003 78 : 0250 41 0251 4D 0252 45 0253 52 AMERICAAMERICA RAM 40 41 41 4D 42 45 43 52 44 49 45 43 46 41 47 00 A 41 R0 40 DPTR 02 50
50 Example 5-7 (2/2) Solution of (b) This method uses null char for end of string ： ORG 0000 MOV DPTR,#MYDATA MOV R0,#40H ;No “MOV R2,#7” BACK: CLR A MOVC A,@A+DPTR JZ HERE ;if A=0 MOV @R0,A ;leave the block INC DPTR INC R0 SJMP BACK HERE: SJMP HERE ORG 250H MYDATA: DB “AMERICA”,0 ;notice null char ;for end of string END
51 Example 5-8 Write a program to get the x value from P1 and send x 2 to P2, continuously. Solution: ORG 0 MOV DPTR,#XSQR_TABLE MOV A,#0FFH MOV P1,A ;P1 as INPUT PORT BACK: MOV A,P1 ;GET X MOVC A,@A+DPTR ;Count the addr. MOV P2,A ;Issue it to P2 SJMP BACK ORG 300H XSQR_TABLE: DB 0,1,4,9,16,25,36,49,64,81 END
52 Example 5-9 Answer the following questions for Example 5-8. (a) Indicate the content of ROM locations 300-309H. (b) At what ROM location is the square of 6, and what value should be there? (c) Assume that P1 has a value of 9: what value is at P2 (in binary)? Solution: (a) All values are in hex. 300 = (00) 301 = (01) 302 = (04) 303 = (09) 304 = (10) 4×4=16=10H 305 = (19) 5×5=25=19H 306 = (24) 6×6=36=24H 307 = (31) 308 = (40) 309 = (51) (b) ROM Addr.=306H; the value is 24H=36 (c) P2 = 01010001B=51H=81 in decimal.
53 Example 5-10 Write a program to toggle P1 at total of 200 times. Use RAM location 32H to hold your counter value instead of registers R0- R7. Solution: MOV P1,#55H MOV 32H,#200 LOP1: CPL P1 ACALL DELAY DJNZ 32H,LOP1
55 Bit-addressable RAM The bit-addressable RAM locations are (byte addresses) 20H to 2FH. Only 16 bytes of RAM are bit-addressable. –16 * 8 bits = 128 bits (in decimal) = 80H bits (in hex) –They are addressed as 00 to 7FH –The internal RAM locations 20 to 2FH are both byte- addressable and bit-addressable. We can use only the single-bit instructions in Table 5-2 to access these bits. –Only direct addressing mode is used here.
56 Figure 8-3. 128 Bytes of Internal RAM General purpose RAM 7F7E7D7C7B7A7978 7776757473727170 6F6E6D6C6B6A6968 6766656463626160 5F5E5D5C5B5A5958 5756555453525150 4F4E4D4C4B4A4948 4746454443424140 3F3E3D3C3B3A3938 3736353433323130 2F2E2D2C2B2A2928 2726252423222120 1F1E1D1C1B1A1918 1716151413121110 0F0E0D0C0B0A0908 0706050403020100 Bank 3 Bank 2 Bank 1 Default register bank for R0 - R7 2E 2F 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 0F 08 07 00 30 7F Bit-addressable locations Byte address
57 Table 5-2: Single-Bit Instructions InstructionFunction SETBbitSet the bit (bit = 1) CLRbitClear the bit (bit = 0) CPLbitComplement the bit (bit = NOT bit) JBbit,targetJump to target if bit = 1 (jump if bit) JNBbit,targetJump to target if bit = 0 (jump if no bit) JBCbit,targetJump to target if bit = 1, clear bit (jump if bit, then clear)
58 Example 5-11 Find out to which byte each of the following bits belongs. Give the address of the RAM byte in hex. (a)SETB 42H;set bit 42H to 1 (d)SETB 28H;set bit 28H to 1 (b)CLR 67H;clear bit 67H (e)CLR 12 ;clear bit 12 (decimal) (c)CLR 0FH;clear bit 0FH (f)SETB 05 Solution: (a) RAM bit address of 42H belongs to D2 of RAM location 28H (b) RAM bit address of 67H belongs to D7 of RAM location 2CH (c) RAM bit address of 0FH belongs to D7 of RAM location 21H (d) RAM bit address of 28H belongs to D0 of RAM location 25H (e) RAM bit address of 12 belongs to D4 of RAM location 21H (f) RAM bit address of 05 belongs to D5 of RAM location 20H
59 Bit-addressable of SFR Every SFR register is assigned a bye address and ports P0-P3 are parts of the SFR. 8051 I/O ports are all bit-addressable. Only registers B, A, PSW, IP, IE, SCON, TCON are bit-addressable.
60 Figure 5-2. SFR RAM Address (Byte and Bit) (1/2) Bit addressByte address F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 AF -- -- AC AB AA A9 A8 B7 B6 B5 B4 B3 B2 B1 B0 -- -- -- BC BB BA B9 B8 FF F0 E0 D0 B8 B0 A8 A0 B ACC PSW IP P3 IE P2 Special Function Registers
61 Figure 5-2. SFR RAM Address (Byte and Bit) (2/2) Special Function Registers 9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 91 90 8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80 not bit addressable 99 98 90 8D 8C 8B 8A 89 SBUF SCON TH1 TL0 P1 TMOD DPH not bit addressable 88 87 83 82 81 80 TH0 TL1 TCON PCON DPL SP P0
62 I/O Bit Addresses When “SETB P1.0” is assembled, it becomes “SETB 90H” since P1.0 has RAM address of 90H. SETB P1.0 SETB 90H The machine codes for SETB P1.0 and SETB 90H are both D2 90.
64 Example 5-12 For each of the following instructions, state to which port the bit belongs. Use Figure 5-3. (a) SETB 86H (b) CLR 87H (c) SETB 92H (d) SETB 0A7H Solution: (a) SETB 86H is for SETB P0.6 (D2 86) (b) CLR 87H is for CLR P0.7 (C2 87) (c) SETB 92H is for SETB P1.2 (D2 92) (d) SETB 0A7H is for SETB P2.7 (D2 A7)
66 Example 5-13 Write a program to save the accumulator in R7 of bank 2. Solution: CLR PSW.3 ;C2 D3 SETB PSW.4 ;D2 D3 MOV R7,A ;FF
67 Example 5-14 While there are instructions such as JNC and JC to check the carry flag bit (CY), there are no such instructions for the overflow flag bit (OV). How would you write code to check OV? Solution: The OV flag is PSW.2 of the PSW register. We can use the following instruction to check the OV flag. JB PSW.2,TARGET ;jump if OV=1 (machine code is 20 D2 rel-addr)
68 Example 5-15 Write a program to see if the RAM location 37H contains an even number. If so, send it to P2. If not, make it even and then send it to P2. Solution: MOV A,37H ;RAM location 37H→A JNB ACC.0,YES ;If A is even, jump to YES INC A ;it is odd, make it even YES:MOV P2,A ;send A to P2
69 Example 5-16 Assume that bit P2.3 is an input and represents the condition of a door. If it goes high, it means that the door is open. Monitor the bit continuously. Whenever it goes high, send a low-to-high pulse to port P1.5 to turn on a buzzer. Solution: HERE:JNB P2.3,HERE ;keep monitoring for high CLR P1.5 ;clear bit (P1.5=0) ACALL DELAY SETB P1.5 ACALL DELAY SJMP HERE low-to-high pulse
70 Example 5-17 The states of bits P1.2 and P1.3 of I/O port P1 must be saved before they are changed. Write a program to save the status of P1.2 in bit location 06 and the status of P1.3 in bit location 07. Solution: CLR 06 ;clear bit address 06 CLR 07 ;clear bit address 07 JNB P1.2,OVER ;If P1.2=0,jump SETB 06 ; OVER:JNB P1.3,NEXT ;If P1.3=0,jump SETB 07 ; NEXT:...
71 Example 5-18 Write a program to save the status of bits P1.7 on RAM address bit 05. Solution: CY is used as a bit buffer. MOV C,P1.7 ;save status of P1.2 on CY MOV 05,C ;save in RAM bit location 05 The machine code is A2 97 for MOV C,P1.7 92 05 for MOV 05,C
72 Example 5-19 Write a program to get the status of bits P1.7 and send it to pin P2.0. Solution: CY is used as a bit buffer. HERE: MOV C,P1.7 ;get bit and send to CY MOV P2.0,C ;send bit to port P2.0 SJMP HERE
73 Using BIT and EQU Directive Assign bit-addressable I/O and RAM locations name BIT bit-address bit-address name OVEN_HOT BIT P2.3 HERE:JNB OVEN_HOT,HERE –Examples 5-20 to 5-23 We can also use the EQU directive to assign addresses. OVEN_HOT EQU P2.3 –Examples 5-24 to 5-25
74 Example 5-20 Assume that bit P2.3 is an input and represents the condition of an oven. If it goes high, it means that the oven is hot. Monitor the bit continuously. Whenever it goes high, send a low-to-high pulse to port P1.5 to turn on a buzzer. Solution: OVEN_HOT BIT P2.3 BUZZER BIT P1.5 HERE:JNB OVEN_HOT,HERE CLR BUZZER ACALL DELAY CPL BUZZER ACALL DELAY SJMP HERE
75 Example 5-21 An LED is connected to pin P1.7. Write a program to toggle the LED forever. Solution: LED BIT P1.7 ;using BIT directive HERE: CPL LED ;toggle LED LCALL DELAY ;delay SJMP HERE ;repeat forever
76 Example 5-22 A switch is connected to pin P1.7 and an LED to pin P2.0. Write a program to get the status of SW and send it to the LED. Solution: SW BIT P1.7 LED BIT P2.0 HERE: SETB P1.7 ;make P1.0 an input MOV C,SW ;save P1.0 to carry MOV LED,C ;send to LED SJMP HERE ;keep repeating
77 Example 5-23 (1/2) Assume that RAM bit location 12H holds the status of whether there has been a phone call or not. If it is high, it means there has been a new call since it was checked the last time. Write a program to display “New Message” on an LCD if bit RAM 12H is high. If it is low, the LCD should say “No New Message”. Solution: Use CY to hold the status. Use JNC to check CY flag. We use “LCALL DISPLAY” to display message (see Chap. 12)
78 Example 5-23 (2/2) PHONBIT BIT 12H MOV C,PHONBIT ;copy bit location 12H to JNC NO ;check to see if is high MOV DPTR,#400H ;address of YES_MG LCALL DISPLAY ;display SJMP EXIT ;get out NO: MOV DPTR,#420H LCALL DISPLAY EXIT: ;data to be displayed on LCD ORG 400H YES_MG: DB “New Message” ORG 420H NO_MG: DB “No New Message” Display YES_MG Test Jump if CY ＝ 0 Not Jump if CY ≠0 EXIT MOV C, 12H Display NO_MG SJMP EXIT
79 Example 5-24 (1/2) A switch (SW) is connected to pin P1.7. Write a program to check the status of SW and perform the following: (a) If SW=0, send “No” to P2. (a) If SW=1, send “YES” to P2. Solution: This program is to show how to use EQU by port names. SW EQU P1.7 ;bit address MYDATA EQU P2 ;byte address
80 Example 5-24 (2/2) SW EQU P1.7 ;bit address MYDATA EQU P2 ;byte address HERE: SETB SW ;make P1.7 an input MOV C,SW ;save P1.7 to carry JC OVER MOV MYDATA,#’N’;SW=0 MOV MYDATA,#’O’ SJMP HERE OVER: MOV MYDATA,#’Y’;SW=1 MOV MYDATA,#’E’ MOV MYDATA,#’S’ SJMP HERE
81 Example 5-25 (1/2) A switch (SW) is connected to pin P1.7. Write a program to check the status of SW and perform the following: (a) If SW=0, send “0” to P2. (a) If SW=1, send “1” to P2. Solution: This program is to show how to use EQU by bit/byte addresses. SW EQU 97H ;bit address MYDATA EQU 0A0H ;byte address
82 Example 5-25 (2/2) SW EQU 97H ;P1.7 bit address MYDATA EQU 0A0H ;P2 byte address HERE: SETB SW ;make P1.7 an input MOV C,SW ;save P1.7 to carry JC OVER MOV MYDATA,#’0’;SW=0, P2=30H SJMP HERE OVER: MOV MYDATA,#’1’;SW=1, P2=31H SJMP HERE
83 Section 5.4 Extra 128-byte On-chip RAM in 8052
84 The Upper 128 Bytes of RAM in 8052 8052 has 256-bytes RAM. –Lower 128 bytes: addresses 00-7FH –Upper 128 bytes: addresses 80-FFH However, 80-FFH has been used by SFR. –To send 55H to P1: MOV 90H,#55H –SFRs are accessed by direct addressing model Where is the location of 90H? –P1? or the RAM location 90H at 8052?
85 Figure 5-4. 8052 On-chip RAM Address Space FF 80 2F 20 1F 18 17 10 0F 08 07 00 scratch pad bit- addressable Bank 0 Bank 3 Bank 2 Bank 1 7F 30 Upper 128-byte RAM Indirect Access of upper 128-byte RAM MOV R0,#90H MOV @R0,#55H Direct Access for SFR MOV 90H,#55H MOV P1,#55H Special Function Registers P1 90H 80 FF
86 How to Distinguish Them? We use different addressing modes to access them: 1. To access the SFRs, we use direct addressing mode. –Ex: MOV 90H,#55H 2. To access the upper 128 bytes, we use the indirect addressing mode, which uses R0 and R1 as pointers. –Ex: MOV R0,#90H MOV @R0,#55H –R0 and R1 have address values of 80H or higher.
87 Example 5-26 Write a program for 8052 to put 55H into the upper RAM locations of 90-99H. Solution: MOV A,#55H MOV R0,#90H MOV R2,#10 BACK: MOV @R0,A ;indirect addressing mode INC R0 ;increment R0 pointer DJNZ R2,BACK ;loop until counter = 0 SJMP $ END
88 Example 5-27 (1/2) Assume that the on-chip ROM has a message. Write a program to copy it from code space into the upper memory space starting at address 80H. Also, as you place a byte in upper RAM, give a copy to P0. Solution: This program is similar to Example 5-3. We use indirect addressing mode to access both the lower and upper 128-byte RAM. We also use the indexed addressing mode.
89 Example 5-27 (2/2) Solution : ORG 0000 MOV DPTR,#MYDATA MOV R1,#80H ;upper 128-byte RAM B1: CLR A MOVC A,@A+DPTR ;read from code JZ EXIT MOV @R1,A ;copy to upper RAM MOV P0,A ;give a copy to P0 INC DPTR INC R1 SJMP B1 EXIT: SJMP $ ORG 300H MYDATA: DB “The promise of World Peace”,0 END
90 You are able to (1/2) List the 5 addressing modes of the 8051 microcontroller Contrast and compare the addressing modes Code 8051 Assembly language instructions using each addressing mode List the SFR （ special function registers ） address Discuss how to access the SFR Manipulate the stack using direct addressing mode
91 You are able to (2/2) Code 8051 instructions to manipulate a look-up table Access RAM, I/O, and ports using bit addresses Discuss how to access the extra 128 bytes of RAM space in the 8052