Lecture 3 Arithmetic, Logic Instructions,

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Lecture 3 Arithmetic, Logic Instructions,
ICT 6641: Advanced Embedded System Lecture 3 Arithmetic, Logic Instructions, Prof. S. M. Lutful Kabir IICT, BUET Session: April, 2011

Review on Lecture-2 Branching and Looping Loop inside loop
Different types of JMP Instructions Different types of CALL Instructions Stack and Stack Pointer The PUSH and POP Instruction The Subroutine Call and Returning From it Pipelining Instruction Cycle Time for the AVR Calculation of Delay Time IICT, BUET

Review on Lecture-2 (continued)
AVR I/O Programming I/O ports and their functions The Role of DDRx Registers Outputting Data to a Port Reading Data from a Port Built-in pull-up resistors with the input pins Duel Role of Ports I/O Bit Manipulation Programming I/O Registers SBI, CBI, SBIC and SBIS instructions IICT, BUET

In AVR, the add operation uses two general purpose registers as its input and the result is stored in first (left) Register The format is ADD Rd, Rr ; Rd=Rd+Rr ADD could change any of the Z, C, N, V, H and S bits of the status register depending of the operands involved Notice that none of the AVR Addition instruction direct memory access; to add memory location we should first load it to any of the registers R0-R31 IICT, BUET

How the status bits are affected during addition
LDI R21, 0xF5 Solution : LDI R22, 0x0B F5H ADD R21, R22 0BH 100H After the addition, register R21 contains 00 and the flags are as follows, C = 1, because there is a carry out of D7 Z = 1, because the result in the destination register (R21) is zero H = 1, because there is a Carry from D3 to D4 IICT, BUET

Addition using Data from the Memory Location
Assume that the memory location 0x400 has the value of 33H. Write a program to add the content of memory location 0x400 and the data 55H Solution: LDS R2, 0x400 ; R2 = 33H (location of 0x400 of RAM) LDI R21, 0x55 ; R21 = 55H ADD R21, R2 ; R21 = R21 + R2 = 55H + 33H = 88H, C = 0, Z = 0, H = 0 IICT, BUET

When adding two 16 bit operands, we need to be concerned with the propagation of carry from the lower byte to the higher byte This is called multi-byte addition to distinguish it from addition of individual bytes The instruction ADC (ADD with Carry) is used on such occasions For example, let us see the addition of 3CE7H+3B8DH 1 3C E7 3B 8D 78 74 Assume that R1 = 8D, R2 = 3B, R3 = E7 and R4 = 3C, ADD R3, R1 ; R3 = R3 + R1 = E7 + 8D = 74 and C = 1 ADC R4, R2 ; R4 = R4 + R2 + Carry = 3C + 3B + 1 = 78 IICT, BUET

Subtraction of unsigned numbers
In many microprocessors, there are two different instructions: SUB and SUBB In AVR we have five instructions for subtraction: SUB, SBC, SUBI, SBCI and SBIW Their formats are: SUB Rd, Rr ; Rd = Rd - Rr SBC Rd, Rr ; Rd = Rd - Rr - C SUBI Rd, K ; Rd = Rd - K SBIC Rd, K ; Rd = Rd - K - C SBIW Rd:Rd+1, K ; Rd + 1 : Rd = Rd + 1 : Rd - K S In AVR, SBC and SBCI are subtraction with borrow. In AVR we use Carry flag for borrow and so SBC (SuB with Carry) IICT, BUET

SUB Rd, Rr [Rd = Rd – Rr] In subtraction, AVR microcontroller (in fact all modern CPUs) use the 2’s complement method One can summarize the steps of the hardware of the CPU in executing the SUB instruction for unsigned numbers as follows: 1. Take the 2’s complement of subtrahend (left side operand) 2. Add with the minuend (right side operator) 3. Invert the carry IICT, BUET

Example of SUB instruction
Show the steps involved in the following: LDI R20, 0x23 LDI R21, 0x3F SUB R21, R20 Solution R21 = 3F R20 = (2’s complement) 1C C = 0 and D7=N=0 The flags will be set as follows: C=0 and N=0 (Notice that there is a carry but C flag will be set to 0, [this will be discussed later] The programmer will look into N (or C) to determine +ve or -ve IICT, BUET

If the result is negative
It is already mentioned that if N=0 (or C = 0) the result is positive But if N = 1 (or C = 1), the result will be negative and the destination will contain the 2’s complement of the result. NEG (negate) command can be used to change it IICT, BUET

SUBI and SBIW The other subtraction instructions are SUBI and SBIW, which subtracts an immediate (constant) value from a register The SBIW subtracts an immediate value in the range of 0-63 from a register pair and stores the result in the register pair Notice that only last 8 registers can be used for SBIW IICT, BUET

Subtraction of 18H from 2917H LDI R25, 0x29 LDI R24, 0x17
SBIW R25:24, 0x18 Notice that you should use SBIW Rd+1:Rd, K format If you type SWIB Rd:Rd+1, K the assembler will assemble your code as if you typed SBIW Rd+1:Rd, K IICT, BUET

SBC (Rd  Rd – Rr – C) Subtract with borrow (denoted by C)
This instruction is used for multi-byte numbers and will take care of borrow of the lower byte If the borrow flag is set to one (C=1) prior to executing the SBC instruction, this operation also subtracts 1 from the result Example: LDI R26, 0x62 27 62H LDI R27, 0x96 12 96H LDI R28, 0x96 14 CCH LDI R29, 0x12 SUB R26, R28 --> C=1, N=1 SBC R27, R29 IICT, BUET

The C flag in subtraction of AVR
Notice that AVR is like other CPUs such as the x86 and the 8051 when it comes to the carry flag in subtract operations. In the AVR, after subtract operations In AVR after the subtract operations, the carry is inverted by the CPU itself and we examine the C flag to see if the result is positive or negative That means that if C=0, the result is positive and if C=1, the result is negative Notice that the CPU does not invert the carry flag after the ADD instruction IICT, BUET

Multiplication of unsigned numbers
The AVR has several instructions dedicated to multiplication First we shall discuss MUL instruction and other are similar to MUL but are used for signed numbers MUL is byte by byte multiply instruction In byte by byte multiply instruction, operands must be in registers. After multiplication the unsigned product is placed in R1 (high byte) and R0 (low byte) Notice that if any of the operands is selected from R0 or R1, the result will overwrite those registers after multiplication IICT, BUET

Multiplication Summary
Multiplication Application Byte1 Byte2 High byte Low byte of result of result MUL Rd, Rr Unsigned numbers Rd Rr R R0 MULS Rd, Rr Signed numbers Rd Rr R R0 MULSU Rd, Rr Unsigned number with Rd Rr R R0 signed number IICT, BUET

Division of unsigned numbers
AVR has no instruction for divide operation We can write a program by repeated subtraction In dividing a byte by a byte the numerator is placed in a register and the denominator is subtracted from it repeatedly. The quotient is the number of times and the remainder is the register upon completion IICT, BUET

An example of Division .DEF NUM=R20 .DEF DENOMINATOR = R21
.DEF QUOTIENT = R22 LDI NUM, 95 LDI DENOMINATOR, 10 CLR QUOTIENT L1: INC QUOTIENT SUB NUM, DENOMINATOR BRCC L1 DEC QUOTIENT ; extra increment is reduced ADD NUM, DENOMINATOR ; NUM is now the remainder HERE: JMP HERE IICT, BUET

Assignment Analyze the example 5-8 of page 168 IICT, BUET

Signed Number Concepts and Arithmetic Operations
All data items used so far have been unsigned numbers meaning that the entire 8-bit operand was used for the magnitude To represent a number as signed, the MSB is set aside for sign The sign is represented by 0 for positive (+ve) numbers and 1 for negative (-ve) numbers The steps in representing a negative number (in 2’s Complement) Represent the number in 8-bit binary Invert the digits Add 1 with the inverted number -127 is represented by 81H, -34H by CCH, -5 as FBH IICT, BUET

Overflow problem in signed number operations
When using signed numbers, a serious problem sometimes arises that must be dealt with This is the Overflow problem, the AVR indicates the existence of an error by raising the V (overflow) flag, but it is upto the programmer to care of the erroneous result If the result of an operation on signed numbers is too large for the register, an overflow occurs, V flag is set Let us see the following operation The limit is (-90) INVALID RESULT N=1, V=1 IICT, BUET

When is the V flag set? In 8-bit signed operations, V is set to 1 if either of the following conditions occurs: There is a carry from D6 to D7 but no carry out of D7 (C=0) There is a carry from D7 out (C=1) but no carry from D6 to D7 In other words, the overflow flag is set the overflow flag is set to 1 if there is a carry from D6 to D7 or from D7 out but not the both It means that if there are carry both from D6 to D7 and from D7 out, V=0 IICT, BUET

Some example of Overflow
Carry from D6 to D7 only, no carry from D7 out (N=0,C=0,V=1) result is -90 WRONG Carry from D7 out only, no carry from D6 to D7 ( N=0,C=1,V=1) result is +126 WRONG Carry both from D6 to D7 and D7 out ( N=1, C=1, V=0) IICT, BUET

Further Consideration on V flag
In the ADD instruction there are two different conditions, either the operands have the same sign or the signs of the operands are different When we ADD operands of different signs, the absolute values of the operands are less than absolute values of one of the operands, so overflow can not happen Overflow can only happen when operands of same sign, it is possible that the result overflows the limit of the register In AVR, the equation of V flag is as follows: V = Rd7.Rr7.R7+ Rd7.Rr7.R7 Where Rd7 and Rr7 are 7th bit of the operands and R7 is the 7th bit of the result IICT, BUET

Further Consideration on V flag (continued)
We conclude that in any signed number addition, V flag indicates that whether the result is valid or not If V=1, the result is erroneous, if V=0, the result is valid We can state emphatically that in unsigned number addition, the V (overflow) flag must be monitored In AVR, there are BRVC and BRVS instructions for the V flag that allow us to correct the signed number error We also have BRCC and BRCS instructions to check for C flag and BRPL and BRMI for checking N flag IICT, BUET

Difference between N and S flag
As we mentioned before that the N flag represents D7 bit of the result If the result is positive, the N flag is zero and if the result is negative N flag is 1 In operations of signed numbers, overflow is possible. Overflow corrupts the result and negates (make opposite) the D7 bit So if we ADD two positive numbers, in case of overflow, the N flag would be 1 showing that the result is negative! (whether actual or not) The S flag helps you to know the real sign of the actual result IICT, BUET

Logic and Compare Instruction
Apart from I/O and arithmetic instructions, logic instructions are some of the most widely used instructions AND AND Rd, Rr ; Rd = Rd AND Rr ANDI Rd, K ; Rd = Rd AND K The AND instructions can affect Z, S and N flags The AND instructions are often used to mask certain bits of an operand LDI R20, 0x H = ANDI R20, 0x0F FH = [masking upper nibble] IICT, BUET

Logical OR instruction
OR Rd, Rr ; Rd = Rd OR Rr This instruction will perform a logical OR operation on two operands and keep the result is left hand operator There are also ORI instruction to perform OR operation between the content of a register and an immediate value, the format is ORI Rd, K ; Rd = Rd OR K OR instructions affects the Z, S and N flags The OR instructions can be used to set certain bits of an operand to 1, for example LDI R20, 0x04 ORI R20, 0x30 ; now R20 will be 34H IICT, BUET

An example of ORI and ANDI
Assume that PB2 is used to control an outdoor light and PB5 to control a light inside a building. Write a program to turn “on” the outdoor light and turn “off” the inside one. SBI DDRB, 2 ORI R20, 0b SBI DDRB, 5 AND R20, 0b IN R20, PORTB OUT PORTB, R20 Notice that we read PORTB instead of PINB because we want to know the last value of PORTB, not the value of chip’s pin ORI makes bit2 to 1 and keeps other bits as it is ANDI makes bit5 to 0 and keeps other bits as it is IICT, BUET

EX-OR instruction EOR Rd, Rs ; Rd = Rd XOR Rs
This instruction performs EX-OR between two operands and keeps the result is the left operand The EX-OR will affect the Z, S and N flags EX-OR can be used to check whether the values in two registers are equal or not OVER : IN R20, PORTB LDI R21, 0x45 EOR R20, R21 BRNE OVER Another widely used application of EX-OR is to toggle the bits of an operand; EOR R0, R20, and R20 is initialized with 0xFF IICT, BUET

Few Other Logical Instructions
COM (Complement) – COM R20 ; 1’s complement NEG (Negative) – NEG R20 ; 2’s complement CP (Compare) – CP Rd, Rr ; Compare is same as subtraction except that compare does not change the register There is also compare with constant value – CP Rd, K IICT, BUET

Branch Instruction Instruction Meaning Condition BREQ Branch if equal
Z=1 BRNE Branch if not equal Z=0 BRSH Branch if same or higher C=0 BRLO Branch if lower C=1 BRLT Branch if less than (signed) S=1 BRGE Branch if greater than or equal (signed) S=0 BRVS Branch if overflow flag set V=1 BRVC Branch if overflow flag clear V=0 IICT, BUET

Rotate and Shift Instructions
ROR Rd ; Rotate Rd right through carry MSB LSB C ROL Rd ; Rotate Rd left through carry C MSB LSB IICT, BUET

Serializing Data Serializing data is a way of sending a byte of data one bit at a time through a single pin of microcontroller There are two ways to transfer a byte of data serially Using one serial port. In using the serial port, programmers have very limited control over the sequence of data transfer The second method of data transfer is to transfer one bit at a time and control the sequence of data and space between them in many new generation of devices such as LCD, ADC, ROM and the serial versions are becoming popular because they take less space on a printed circuit board IICT, BUET

Sending data serially under program control
Write a program to transfer the value 41H serially one bit at a time via pin PB1. Put one high at the start and end of the data send LSB first SBI DDRB, 1 JMP NEXT LDI R20, 0x41 ONE: SBI PORTB, 1 CLC NEXT: LDI R16, 8 DEC R16 SBI PORTB, 1 BRNE AGAIN AGAIN: SBI PORTB, 1 ROR R20 BRCS ONE HERE: JMP HERE CBI PORTB, 1 IICT, BUET

Bring Data Serially CBI DDRC, 1 LDI R16, 8 LDI R20, 0 AGAIN: SBIC PINC, 7 SEC SBIS PINC, 7 CLC ROR R20 DEC R16 BRNE AGAIN HERE: JMP HERE Write a program to bring a byte of data serially through pin PC7 and save it in R20 register. The byte comes in LSB first IICT, BUET

Shift and Swap Instructions
There are three shift instructions in AVR LSL Rd ; Logical shift left LSR Rd ; Logical shift right ASR Rd ; Arithmetic shift right keeping MSB constant Swap Instruction Nibble swapping – left nibble goes to right and right to left IICT, BUET

End of Lecture 3 IICT, BUET

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