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By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF ENGINEERING UKM Supervised by PROF DR MASURI OTHMAN (UKM) Co-supervisor.

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Presentation on theme: "By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF ENGINEERING UKM Supervised by PROF DR MASURI OTHMAN (UKM) Co-supervisor."— Presentation transcript:

1 By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF ENGINEERING UKM Supervised by PROF DR MASURI OTHMAN (UKM) Co-supervisor DR BAMBANG SUNARYO SUPARJO (MENTOR GRAPHIC USA) THE DESIGN OF THE MEMORY BUILT-IN SELF-TEST, DIAGNOSIS AND REPAIR (MBISTDR) FOR SRAMs

2 Outline Introduction Memory Architecture Memory Fault Models Test Algorithms Memory Testing, Diagnosis and Repair Conclusion

3 Introduction Why BIST, BISD and BISR The advances of semiconductor memory technologies have become more complex and also the numbers of memory cell per chip (transistors) rapidly increase. The ITRS 2003 has shown an ever Increasing percentage of chip area devoted to embedded memory, with today’s SoCs already consisting of over 50% memory.

4 Introduction

5 Memory Sizes Versus Yield

6 Introduction ITRS SOC Test Requirements

7 Introduction The Requirement of Future MBISTDR Fault Modeling – New Fault Models (defect in deep-submicron) Test algorithm design – Optimal test/diagnosis (high defect coverage) BIST – allow at speed testing BISR – low cost repair scheme ( improve the yield and reliability)

8 Memory architecture Functional RAM Model Source: Testing and semiconductor memories, A.J. van de Goor

9 Reduced Functional RAM Model Memory architecture Source: Testing and semiconductor memories, A.J. van de Goor

10 Memory Fault Models Source: Testing and semiconductor memories, A.J. van de Goor

11 Memory Fault Models Source: Testing and semiconductor memories, A.J. van de Goor

12 Memory Fault Models

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15 Coupling Fault(CF)

16 Memory Fault Models Two Cell Faults - cont

17 Memory Fault Models

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19 Coupling Fault State Coupling Fault Source: Testing and semiconductor memories, A.J. van de Goor

20 Memory Fault Models

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23 Test Algorithms Functional RAM Testing Traditional Test - Zero-One - SAF - Checkerboard - SAF - GALPAT and Walking 1/0 – AF, SAF, TF and CF - testing time unacceptable - Sliding Diagonal – SAF, TF - Butterfly – SAF, AF Source: Testing and semiconductor memories, A.J. van de Goor

24 Test Algorithms March Test Algorithms

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26 Test Algorithms March Test Notation Source: Testing and semiconductor memories, A.J. van de Goor

27 Test Algorithms March Test Notation Source: Testing and semiconductor memories, A.J. van de Goor

28 Test Algorithms Source: Testing and semiconductor memories, A.J. van de Goor

29 Test Algorithms Comparison of March Tests March Test AlgorithmNumber Operation Fault Coverage Test-US MATS4n or * 2 N SAF, some AF MATS+ 2 5n or 5 * 2 N SAF, AF Test-UTMATS++7 or 7 * 2 N SAF, TF, AF Test-UCMarch C11nSAF, TF, AF, CF Test-LCMarch A15nSAF, AF, CF Test-LCTMarch B17nSAF, AF, CF, TF Source: Testing and semiconductor memories, A.J. van de Goor

30 Test Algorithms Fault detection using March C- M0 M1 M2 M3 { ⇕ (w0);  (r0, w1);  (r1, w0);  (r0,w1); M4 M5  (r1, w0); ⇕ (r0} - 10N Test algorithm Disable RAM (wait) {  (r0, w1,); Disable RAM(wait)  (r1):} - Data retention fault(DRF)

31 Test Algorithms Fault detection using Extended March C- (covered SOF) M0 M1 M2 M3 { ⇕ (w0);  (r0, w1,r1);  (r1, w0);  (r0,w1); M4 M5  (r1, w0); ⇕ (r0)} - 11N Test algorithm Disable RAM (wait) {  (r0, w1,); Disable RAM(wait)  (r1):} - Data retention fault(DRF)

32 Test Algorithms Fault detection using extended March C- Fault March Elements M0 ⇕ (w0) M1  (r0, w1,r1) M2  (r1, w0) M3  (r0,w1) M4  (r1, w0) M5 ⇕ (r0) SAF INITIALZATIONINITIALZATION r0 – s-a-1r1 – s-a-0 TF M1(r0,w1) followed M2(r1,w0) followed by M2(r1) for by M3(r0) for CF M1(r0,w1) for Cfid *ji M2(r1,w0 ) for Cfid *ji M3(r0,w1) followed M4(r1,w0) followed by M4(r1,w0) by M5(r0) for Cfid for Cfid M1 & M3(r0,w1) M2 & M4(r1,w0) Followed by followed by M5(r0) M4(r1,w0) for for Cfin Cfin *all CFids is j i is similar) AF (M1(r0, w1,r1) M2(r1, w0)) – j>i, (M3(r0,w1) M4 (r1, w0)) – i>j (Satisfied with known technology) SOF r1 DRF Disable RAM (wait) {  (r0, w1,); Disable RAM(wait)  (r1):}

33 Test Algorithms Functional Fault Models for Diagnosis ICCAD 2000 Chi-Feng Wu

34 Test Algorithms Fault detection and diagnosis using March CL {  (w0);  (r0, w1,);  (r1, w0,); ⇕ (r1); R0 R1 R2  (r0,w1); ⇕ (r1);  (r1, w0); ⇕ (r0)} R3 R4 R5 R6 -12N Test algorithm Disable RAM (wait){  (r0, w1,); Disable RAM(wait)  (r1):} - Data retention Fault(DRF).

35 Test Algorithms Fault detection and diagnosis by Extended March CL {  (w0);  (r0, w1, r1);  (r1, w0); ⇕ (r1);  R0 R1 R2 R3 (r0,w1); ⇕ (r1);  (r1, w0); ⇕ (r0)} R4 R5 R6 R7 -13N Test algorithm Disable RAM (wait){  (r0, w1,); Disable RAM(wait)  (r1):}- Data retention Fault(DRF).

36 Test Algorithms Fault syndrome for March CL

37 Test Algorithms Fault syndrome for Extended March CL

38 1. {  (w0);  (r0, w1,);  (r1, w0);  (r0,w1);  (r1, w0) }- Disable RAM (wait){  (r0,w1,); Disable RAM(wait)  (r1):} 9N test algorithm with data retention test – Rob Dekker 1988, has covered 100% coverage of the faults under the listed fault models. 2. {  (w0);  (r0, w1, r1, w0); delay  (r0, r0);  (w1);  (r1, w0, r0, w1); delay  (r1, r1)} 14N test algorithm - Said Hamdioui 2000, has covered 100% coverage of the faults under the listed fault models and spot defects. Test Algorithms Existing March Test Algorithms

39 3. {  (w0);  (r0); delay  (r0);  (w1);  (r1); delay  (r1)} or {  (w0);  (r0); delay  (r0);  (w1);  (r1); delay  (r1)} 6N test algorithm – Baosheng Wang 2003, has reduced less than half of the required time for the 9N test algorithm 4. { ⇕ (w0);  (r0, w1,); ⇕ (r1);  (r1, w0); ⇕ (r0);  (r0, w1); ⇕ (r1);  (r1, w0); ⇕ (r0); 13N test algorithm – V. N. Yarmolik 1996, has introduced diagnosis capability and achieved 63.6% diagnostic resolution (SAF & CF). Test Algorithms Existing March Test Algorithms

40 5. { ⇕ (w0);  (r0, w1,r1, w0);  (r0, w1);  (r1, w0,r0, w1); ⇕ (r1);  (r1, w0); ⇕ (r0);  (r0, w1); ⇕ (r1); 18N test algorithm – V. N. Yarmolik 1996, has been introduced for the diagnosis capability and achieved 90.9%diagnostic resolution (SAF & CF). 6. {  (w0);  (r0, w1, w0, w1);  (r1, w0, r0, w1);  (r1, w0, w1, w0);  (r0, w1, r1, w0); Hold  (r0, w1); Hold  (r1); 20N test algorithm – I. Kim 1998, has been diagnosis capability and achieved 59% diagnostic resolution (SAF & CF).

41 Test Algorithms Existing March Test Algorithms 7. {  (w0);  (r0, w1,r1, w0 ); ⇕ (r0); ⇕ (w1);  (r1, w0,r0, w1); ⇕ (r1); } 12N test algorithm – T. J. Bergfeld 2000, has proposed diagnosis capability but it could only achieve 22.7% diagnostic resolution (SAF & CF). 8. { ⇕ (w0);  (r0, w1, r1); ⇕ (r1);  (r1, w0,r0); ⇕ (r0);  (r0, w1, r1); ⇕ (r1);  (r1, w0, r0); ⇕ (r0); } 17N test algorithm – Jin-Fu Li 1996, has introduced diagnosis capability and achieved 100% diagnostic resolution(SAF & CF).

42 Test Algorithms Existing March Test Algorithms 9. {  (w0);  (r0, w1,); ⇕ (r1);  (r1, w0);  (r0, w1); ⇕ (r1);  (r1, w0); ⇕ (r0);} 12N test algorithm plus 3N or 4N ( for aggressor locating) – V. A. Vardanian 2002, has introduced diagnosis capability and achieved 100% diagnostic resolution.

43 STATE-OF-ART FOR TEST ALGORITHMS Optimality in term of time complexity Regularity and symmetry such that the self-test circuit can minimize the silicon areaRegularity and symmetry such that the self-test circuit can minimize the silicon area High defect coverage and diagnosis capability in order to increase the repair capabilities and the overall yieldHigh defect coverage and diagnosis capability in order to increase the repair capabilities and the overall yield Test Algorithms

44 Memory Testing, Diagnosis and Repair MBIST ARCHITECTURE SRAM MBIST SYSTEM FSM CONTROLLER COMPARATOR BIST

45 Memory Testing, Diagnosis and Repair MBISTD ARCHITECTURE SRAM MBISTD SYSTEM FSM CONTROLLER COMPARATOR BIST INDICATOR

46 STATE-OF-ART FOR BISTD Minimizing BIST overhead in both silicon area and routingMinimizing BIST overhead in both silicon area and routing Supporting diagnosis capabilitiesSupporting diagnosis capabilities Supporting different kinds of memories (single-port,multi-port)Supporting different kinds of memories (single-port,multi-port) Memory Testing, Diagnosis and Repair BISTD

47 Memory Testing, Diagnosis and Repair MBISTDR ARCHITECTURE SRAM MBISTDR SYSTEM FSM CONTROLLER COMPARATOR BIST INDICATOR EXTRA COLUMN /ROW/WORD

48 Conclusion MBISTDR is essential for memory reliability in the near future. The addition of BISD and BISR will enhance the yields of overall memory chips. New test algorithm and fault syndromes base on March CL has been proposed to detect and diagnose SOF and AF.

49 THANK YOU Q & A

50 THANK YOU Q & A

51 THANK YOU Q & A

52 Memory Testing, Diagnosis and Repair Example of MBISR Fuse Box Redundancy Logic RAM MBIST Mux Data Address Control The Memory BIST and Self-Repair (MBISR) Concept [Volker 2001]. Data

53 The Figure above shows the MBIST and Self-Repair using redundancy logic and Fuse Box concept. The MBISR concept contains an interface between MBIST logic, redundancy wrapper logic to replace defect address and Fuse boxes to store the failling addresses Memory Testing, Diagnosis and Repair

54 On Going Research The design and simulation of MBISTDR. New Test Algorithms with Diagnosis capability will be designed according to the required coverage and testing time.

55 Design of MBISTDR Controller for Stuck-at Faults MBISTDR CONTROLLER 32 X 12 SRAM MUX_1 MUX_2 d_in Wr_en Bistr_add r Bistr_error_addr bistr_data_read d_out Rd_en Sram_error bistr_data_write mode_sel addr bistr_en clk Mode_sel MBISTDR Methodology

56 The schematic of MBISTDR Controller for Stuck-at Faults MBISTDR Methodology

57 Figure above shows that MBISTDR contains MBISTDR controller and 32x12 SRAM Test Pattern In – Bistr_data_write (w0/w1) Mode_sel – test or normal mode Enable the Wr_en or Rd_en Test Pattern Out – Bistr_data_read(r0/r1) MBISTDR Methodology

58 Test and Repair Algorithm of MBISTDR controller for Stuck-at Faults MBISTDR Methodology

59 Figure above Shows that, how MBISTR controller implements the test and repair algorithm to the 32x12 SRAM memory. Procedure: address 1 – w0 then compare with r0 address 2 – w1 then compare with r1 Run until either marked addresses or memory addresses reach the maximum

60 MBISTDR Results And Discussion Fault Free Results for MBISTDR During Normal mode Operation

61 MBISTDR Result And Discussion Fault Detection Results for MBISTDR during Test mode Operation

62 Results for MBISTDR During Normal Mode and Test Mode Operation MBISTDR Result And Discussion

63 Final Target for MBISTDR Criteria: TA 1)High defect coverage and diagnosis capability in order to increase the repair capabilities and the overall yield – below 17N BISTDR 1)Supporting diagnosis capabilities – 100% diagnosis resolution (include SOF and AF) 2) Using Extra Memory for the BISR

64 MBISTDR Conclusion A new memory Built-in Self-test and Repair concept has been designed and this concept is proposed without using any extra rows and columns. These test and repair are only focused on the reconfiguration of the memory addresses, which means no extra spaces needed as the previous researches.


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