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11 Dynamic scheduling Kosarev Nikolay MIPT Apr, 2010.

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Presentation on theme: "11 Dynamic scheduling Kosarev Nikolay MIPT Apr, 2010."— Presentation transcript:

1 11 Dynamic scheduling Kosarev Nikolay MIPT Apr, 2010

2 22 Agenda In-order execution Out-of-order execution. Tomasulo’s algorithm Implementation in hardware Demo Hardware speculation Demo

3 33 In-order execution Data hazards - RAW, WAW. No WAR. Pipeline DIVR1 = R2, R3 ADDR9 = R1, R4 SUBR8 = R4, R5 DIVR1 = R2, R3 ADDR1 = R2, R4 SUBR6 = R1, R5 (but code has no sense)

4 44 Out-of-order execution Split ID into 2 stages: Issue - IS Decode, check for structural hazards Read operands - RO Wait until no data hazards, read operands Pipeline Out-of-order execution implies out-of-order completion (WB) Hazards – RAW, WAW, WAR DIVR0 = R2, R4 ADDR6 = R0, R8 SUBR8 = R10, R14 MULR6 = R10, R8

5 55 Tomasulo’s algorithm How are data hazards avoided? RAW – wait for availability of operands WAR, WAW – register renaming (переименование регистров) DIVR0 = R2, R4 ADDR6 = R0, R8 ADDR9 = R6, R1 SUBR8 = R10, R14 MULR6 = R10, R8 DIVR0 = R2, R4 ADDA = R0, R8 ADDR9 = A, R1 SUBB = R10, R14 MULR6 = R10, B

6 66 Implementation in HW

7 77 Demo Tomasulo's algorithm for dynamic scheduling LDF6 = R2, 2 LDF2 = R3, 4 MULF0 = F2, F4 SUBF8 = F2, F6 DIVF10 = F0, F6 ADDF6 = F8, F2

8 88 Hardware speculation Based on 3 key ideas: Dynamic branch prediction Speculative execution Dynamic scheduling Extra stage: instruction commit New buffer: ROB (reorder buffer) Pipeline

9 99 Hardware speculation

10 10 Demo Reorder buffer

11


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