Download presentation

Presentation is loading. Please wait.

Published byShawn Turkington Modified about 1 year ago

1
CSE260-1-1 Review for Exam 1 Chapters 1 through 3

2
CSE260-1-2 Chapter 1 Overview Information Representation Number Systems [binary, octal and hexadecimal] Base Conversion Decimal Codes [BCD (binary coded decimal)] Alphanumeric Codes Parity Bit Gray Codes

3
CSE260-1-3 1-2 Number Systems Positive radix, positional number systems Examples: Decimal (radix r =10) Binary (radix r =2) Octal (radix r = ) Hexadecimal (r = ) Ex: 1101.01 = (. ) 10 Ex: 24.3 = 2x10 1 + 4x10 0 +3x10 -1 Digits (0-9) Bits (0-1) Digits: 1,2,…9, A, B, C, D, E, F

4
CSE260-1-4 Range of numbers Binary number: ex. a 3-bit number: n=3 000, 001 …,111 or in decimal system: 0, 1 … 7 Total of 8 numbers (=2 3 ) Range: from 0 to 7 (0 to 2 3 -1) In general a n-bit number represents: 2 n different numbers Min: 0 Max number: 2 n -1 For fractions: m bits after the radix point: Min: 0 Max number: (2 m -1)/2 m

5
CSE260-1-5 Use of HEX system Short hand notation of large binary numbers: Each HEX digits can be represented by exactly 4 bits (16=2 4 ) Thus (10011110.0101) 2 Conversion from binary to HEX and HEX to binary is very easy: (10011101) 2 = ( ) 16 (1010110110.11) 2 = ( ) 16 B39.7 16 = ( ) 2 9 E. 5

6
CSE260-1-6 Octal system Radix r = 8 8 digits: 0, 1, 2,…7 Ex: 275 8 = 2x8 2 + 7x8 + 5x1 = 128 + 56 + 5 = 189 10 Each octal digit can be represented by 3 bits

7
CSE260-1-7 1-3 Conversion Between Bases To convert from one base to another: 1) Convert the Integer Part 2) Convert the Fraction Part 3) Join the two results with a radix point

8
CSE260-1-8 Example: convert (325.65) 10 to hex Integer part: 325 10 = (. ) 16 Fractional part:.65 325/16 = 20 and rem = 5 20/16 = 1 and rem = 4 1/16 = 0 and rem = 1 Most significant Least significant digit Thus 325 10 = 145 16 0.65x16 = 10.4 thus int = 10= A 0.4x16 = 6.4 thus int = 6 Etc. Most significant Least significant Thus.65 10 = A66 16 325.65 10 = 145.A66 16

9
CSE260-1-9 Conversion - Summary Binary Decimal Hexadecimal Octal Divisions (or x) by 16 A i.16 i A i.8 i Divisons by 8 Divisons by 2 A i.2 i Group in bits of 3 Group in bits of 4 Octal Hex: through the binary representation

10
CSE260-1-10 1-4 Binary Codes A n-bit binary code is a n-bit word which can represent up to 2 n different elements. Example: 3-bit code can represent up to 8 different elements”

11
CSE260-1-11 Binary Coded Decimal (BCD) The BCD code is the 8,4,2,1 code. This code only encodes the first ten values from 0 to 9. Each decimal digit is coded separately by 4 bits Example: (325) 10 = (0011 0010 0101) BCD Exercise: (856) 10 = ( ) BCD 5 23

12
12 Overview Chapter 2 Binary Logic and Gates Boolean Algebra Standard Forms Two-Level Optimization Map Manipulation Other Gate Types Exclusive-OR Operator and Gates High-Impedance Outputs

13
13 Operator Definitions and Truth Tables Truth table - a tabular listing of the values of a function for all possible combinations of values on its arguments Example: Truth tables for the basic logic operations: 111 001 010 000 Z = X·Y YX AND OR XYZ = X+Y 000 011 101 111 01 10 X NOT XZ =

14
14 3. 9. 4. 2. X. 1 X = X. 00 = 2-2 Boolean Algebra Boolean algebra deals with binary variables and a set of three basic logic operations: AND (.), OR (+) and NOT ( ) that satisfy basic identities 1. X + 0 X = + X 11 = 7. 8. 0 = X. X 1 = X + X X = X Existence 0 and 1 or operations with 0 and 1 Idempotence Involution 5. 6. X. XX = X + XX = Existence complements Basic identities Dual Replace “+” by “.”, “.” by +, “0” by “1” and “1’’ by”0”

15
15 Commutative Associative Distributive DeMorgan’s Boolean Algebra 10. X + YY + X = 12. (X + Y)Z + X + (YZ)Z) += 16. X + YX. Y = 11. XYYX = 13. (XY)ZX(YX(YZ ) = 15. X+ YZ(X + Y)(X + Z)= 17. X. YX + Y = Dual Boolean Theorems of multiple variables 14. X (Y+ Z)XYXZ +=

16
16 Other useful Theorems Minimization Absorption Simplification Consensus XY + XY = Y (X + Y)(X + Y) = Y X + XY = X X(X + Y) = X X + XY = X + Y X(X + Y) = XY XY + XZ + YZ = XY + XZ (X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z) Dual

17
17 2-3 Standard (Canonical) Forms It is useful to specify Boolean functions in a form that: Allows comparison for equality. Has a correspondence to the truth tables Canonical Forms in common usage: Sum of Products (SOP), also called Sum or Minterms (SOM) Product of Sum (POS), also called Product of Maxterms (POM)

18
18 Examples: Two variable minterms and maxterms. The index above is important for describing which variables in the terms are true and which are complemented. Maxterms and Minterms IndexMintermMaxterm 0 (00)x yx + y 1 (01)x yx + y 2 (10)x yx + y 3 (11)x yx + y

19
19 Index Examples – Four Variables Index Binary Minterm Maxterm i Pattern m i M i 0 0000 1 0001 3 0011 5 0101 7 0111 10 1010 13 1101 15 1111 ? ? dcba dcba dcba dcba dcba d cba dcba ? dba dcba ? c i mM = i i i Mm = Notice: the variables are in alphabetical order in a standard form dcba Relationship between min and MAX term?

20
20 Minterm Function Example F(A, B, C, D, E) = m 2 + m 9 + m 17 + m 23 F(A, B, C, D, E) write in standard form: Sum of Product (SOP) expression: F = Σm(2, 9, 17, 23) A’B’C’DE’ + A’BC’D’E + AB’C’D’E + AB’CDE m2m2 m9m9 m 17 m 23

21
21 Expressing a function with Maxterms Start with the SOP: F1(x,y,z) =m1 + m4 + m7 Thus its complement F1can be written as F1 = m0 +m2 +m3 + m5 + m6 (missing term of F1) Apply deMorgan’s theorem on F1: (F1 = (m0 +m2 +m3 + m5 + m6) = m0.m2.m3.m5.m6 = M0.M2.M3.M5.M6 = Π M (0,2,3,5,6) Thus the Product of Sum terms (POS): )z y z)·(x y ·(x z) y (x F 1 ++++++= z) y x)·(z y x·( ++++ also called, Big M notation

22
22 2-4 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization requires a cost criterion to measure the simplicity of a circuit Distinct cost criteria we will use: Literal cost (L) Gate input cost (G) Gate input cost with NOTs (GN)

23
23 Literal – a variable or its complement Literal cost – the number of literal appearances in a Boolean expression corresponding to the logic circuit diagram Examples (all the same function): F = BD + AB’C + AC’D’ L = 8 F = BD + AB’C + AB’D’ + ABC’ L = F = (A + B)(A + D)(B + C + D’)( B’ + C’ + D) L = Which solution is best? Literal Cost

24
24 Karnaugh Maps (K-map) A K-map is a collection of squares Each square represents a minterm The collection of squares is a graphical representation of a Boolean function Adjacent squares differ in the value of one variable Alternative algebraic expressions for the same function are derived by recognizing patterns of squares The K-map can be viewed as A reorganized version of the truth table A topologically-warped Venn diagram as used to visualize sets in algebra of sets

25
25 2-5 Map Manipulation: Systematic Simplification A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle with the number of squares a power of 2. A prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers (includes) one or more minterms. Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map.

26
26 Sometimes a function table or map contains entries for which it is known : the input values for the minterm will never occur, or The output value for the minterm is not used In these cases, the output value need not be defined Instead, the output value is defined as a “don't care” By placing “don't cares” ( an “x” entry) in the function table or map, the cost of the logic circuit may be lowered. Example 1: A logic function having the binary codes for the BCD digits as its inputs. Only the codes for 0 through 9 are used. The six codes, 1010 through 1111 never occur, so the output values for these codes are “x” to represent “don’t cares.” Don't Cares in K-Maps

27
27 Other Gate Types: overview A B BUF NAND NOR XOR XNOR 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 0 0 0 1 A ABAB ABAB ABAB ABAB

28
28 The Tri-State Buffer For the symbol and truth table, IN is the data input, and EN, the control input. For EN = 0, regardless of the value on IN (denoted by X), the output value is Hi-Z. For EN = 1, the output value follows the input value. Variations: Data input, IN, can be inverted Control input, EN, can be inverted by addition of “bubbles” to signals. IN EN OUT Symbol Truth Table OUT= IN.EN

29
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Logic and Computer Design Fundamentals

30
NAND Mapping Algorithm 1.Replace ANDs and ORs: 2.Repeat the following pair of actions until there is at most one inverter between : a.A circuit input or driving NAND gate output, and b.The attached NAND gate inputs.

31
NOR Mapping Algorithm 1.Replace ANDs and ORs: 2.Repeat the following pair of actions until there is at most one inverter between : a.A circuit input or driving NAND gate output, and b.The attached NAND gate inputs.

32
Enabling Function Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0, or 1 When disabled, 0 output When disabled, 1 output See Enabling App in text

33
3-7 Decoding A n-bit binary code can represent up to m=2 n elements: m elements n-bit binary code Decoding - the conversion of an n-bit input code to an m-bit output code with n ≤ m ≤ 2 n such that each valid code word produces a unique output code A 0 : A n-1 D 0 D 1 : D m-1 n-2 n decoder n bits m-elements ≤ 2 n encoding decoding (ex. 256 alpha-num. chars) (ex. 8-bit ASCII code)

34
2-to-4 Line Decoder circuit D 0 = A 1 A 0 D 1 = A 1 A 0 D 2 = A 1 A 0 D 3 = A 1 A 0 A 1 A 0 Notice that the outputs of the decoder correspond to the minterms: D i =m i

35
Decoder Expansion Larger decoders can be realized by implementing each minterm using a single AND gate: However for large decoders this requires multiple input AND gates which is not always feasible. Better to use a hierarchical approach: build larger ones from smaller decoders. Approach: Output AND gates have only 2 inputs and implement the minterms. The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.

36
Rule for building large decoders k-to-2 k decoder: One needs 2 k output AND gates If k can be divided by 2: use two k/2-to-2 k/2 decoders If k cannot divided by 2: use a (k+1)/2 and use a (k-1)/2 decoder. Previous example: 3-to-8 decoder (k=3): Use a 2-to-4 and a 1-to-2 decoder

37
Combinational Logic Implementation - Decoder and OR Gates Implement m functions of n variables with: Sum-of-minterms expressions One n-to-2 n -line decoder m OR gates, one for each output

38
Example Design and implement a majority function F(ABC) using a 3-to-8 decoder Truth table: Minterms: F= m(3,5,6,7) Implementation using decoder: A B C F 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 F 0123456701234567 ABCABC 210210 Indicate MSB, LSB

39
Encoding Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears: ex. D1=1 output 0001 Examples: Octal-to-Binary encoder Other examples? 0100001000 10001000 A 0 : A n-1 D 0 D 1 : D m-1 encoder 0 1 2 3 m-1 0 1 2 n-1

40
Priority Encoder If more than one input value is 1, then the encoder just designed does not work. An encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder. Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position. D0D1D2D3D0D1D2D3 A1A0A1A0 ? V 01230123 1010 To processor

41
3-9 Selecting (multiplexers) Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of n information inputs from which the selection is made A set of k control (select) lines for making the selection A single output 0 1 2 3 : n-1 I 0 I 1 I 2 I 3 I n-1 OUT S k-1..S 1 S 0 n ≤ 2 k inputs k select lines k-1.. 1 0

42
4:1 MUX realization Expression for OUT Circuit implementation: SOP 4 AND gates (4 product terms) 2-to-4 line decoder (to generate the minterms) S 1 S 0 OUT 0 0 I 0 0 1 I 1 1 0 I 2 1 1 I 3 OUT = S 1 S 0 I 0 + S 1 S 0 I 1 + S 1 S 0 I 2 + S 1 S 0 I 3 or OUT = Σ m i I i i=0 2 k -1 m3m3 m2m2 m1m1 m0m0

43
Exercise Build a 8:1 MUX using two 4:1 and one 2:1 muxes 4:1 01230123 1 0 I0I1I2I3I0I1I2I3 4:1 01230123 1 0 I4I5I6I7I4I5I6I7 S 1 S 0 0101 OUT S2S2 Ex: S2S1S0=110 : select I 6

44
Multiplexer-based combinational circuits realization- Approach 1 A mux can be easily used to implement a function defined by a truth table (lookup table) Indeed the output F of a mux is equal to: F = Σ m i I i i=0 2 k -1 Give the input I i the value of 0 or 1 as shown in the truth table 4:1 01230123 1 0 F 01100110 A B Example A B OUT =F 0 0 I 0 0 0 1 I 1 1 1 0 I 2 1 1 1 I 3 0 m0m0 m1m1 m2m2 m3m3 F= Σm(1,2)

45
Combinational Logic Implementation - Multiplexer Approach 2 Implement any m functions of n + 1 variables by using: An m-wide 2 n -to-1-line multiplexer Design: Find the truth table for the functions. Based on the values of the first n variables, separate the truth table rows into pairs For each pair and output, define a rudimentary function of the final variable (0, 1, X, ) X

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google