Presentation is loading. Please wait.

Presentation is loading. Please wait.

© 2000 M. CiesielskiDatapath Synthesis1 ANALYTICAL APPROACH TO CUSTOM DATAPATH SYNTHESIS Serkan Askar, Maciej Ciesielski Department of Electrical & Computer.

Similar presentations


Presentation on theme: "© 2000 M. CiesielskiDatapath Synthesis1 ANALYTICAL APPROACH TO CUSTOM DATAPATH SYNTHESIS Serkan Askar, Maciej Ciesielski Department of Electrical & Computer."— Presentation transcript:

1 © 2000 M. CiesielskiDatapath Synthesis1 ANALYTICAL APPROACH TO CUSTOM DATAPATH SYNTHESIS Serkan Askar, Maciej Ciesielski Department of Electrical & Computer Engineering University of Massachusetts, Amherst {saskar,

2 © 2000 M. CiesielskiDatapath Synthesis2 Outline Introduction Problem definition Approach, design phases Analytical formulation (MILP) Results Conclusions and future work

3 © 2000 M. CiesielskiDatapath Synthesis3 Motivation Datapath: highly regular structure – array of bit/row slices – rows: identical cells – hand-crafted layout Datapath cell power rails Limitations of custom design – ability of the designer – slow development time

4 © 2000 M. CiesielskiDatapath Synthesis4 Typical Datapath Cell - schematic General topoloy generated by floorplanning –power rails –bristles Fixed width (pitch)

5 © 2000 M. CiesielskiDatapath Synthesis5 Datapath Cell - layout

6 © 2000 M. CiesielskiDatapath Synthesis6 Problem Definition Automation of transistor level placement –diffusion-limited, routing ignored (to certain degree) Goal: – minimize layout area, size – improve manufacturability, routability Constraints – bit-slice constraints – component constraints – custom design issues fixed

7 © 2000 M. CiesielskiDatapath Synthesis7 Previous Work Very little work on custom quality datapath synthesis Stochastic methods – simulated annealing – genetic algorithms Deterministic methods – analytical (QP, ILP, etc) – constructive methods

8 © 2000 M. CiesielskiDatapath Synthesis8 Bit-slice Constraints Fixed width (pitch) – power rails Vertical bristles – data lines Horizontal bristles – control lines control lines pitch VDDGND data lines

9 © 2000 M. CiesielskiDatapath Synthesis9 Component Types Transistors, logic gates Transistor chains, folded transistors

10 © 2000 M. CiesielskiDatapath Synthesis10 Component Geometries RectangularL-shape

11 © 2000 M. CiesielskiDatapath Synthesis11 Custom Design Issues Multiple instances – chaining, folding Merging ( same diffusion type, sharing common net) –diffusion sharing (same cell)

12 © 2000 M. CiesielskiDatapath Synthesis12 Custom Design Issues (cont’d) Component sharing –combine components from adjacent cells with common independent net VDD GND cell icell i+1

13 © 2000 M. CiesielskiDatapath Synthesis13 Design Objective Secondary objectives: – performance – routability – well minimization Main objective: – minimize height of datapath cell fixed min

14 © 2000 M. CiesielskiDatapath Synthesis14 Post-processing Connectivity - no geometry info Geometry - no connectivity info Managing complexity Design Flow Initial relative placement Component grouping Geometric placement Final layout Well minimization Net length minimization Pre-processing Input files

15 © 2000 M. CiesielskiDatapath Synthesis15 Pre-processing Connectivity analysis Initial component merging (to minimize number of objects to place)

16 © 2000 M. CiesielskiDatapath Synthesis16 Initial Relative Placement Derive a relative initial placement – connectivity to components and bristles – geometry is ignored Standard force-directed technique – component locations: centers of net gravity

17 © 2000 M. CiesielskiDatapath Synthesis17 Initial Relative Placement Generates relative placement of components based on electrical connectivity

18 © 2000 M. CiesielskiDatapath Synthesis18 Component Grouping Limit the number of relations between components by grouping them together for placement before grouping – 6 relations after grouping – 3 relations

19 © 2000 M. CiesielskiDatapath Synthesis19 Geometric Placement Generate non-overlapping placement –component geometry –design rules –fixed connectivity (initial relative placement) Model: Mixed Integer Linear Program (MILP)

20 © 2000 M. CiesielskiDatapath Synthesis20 Component Modeling Component modeled as a pair of squares R i = orientation parameter X i2, Y i2 X i1, Y i1 R i = 1 R i = 0 X i1 - X i2 = (D i - d i ) * (1- R i ) Y i1 - Y i2 = (D i - d i ) * R i d i = min (W i, H i ) D i = max (W i, H i ) where

21 © 2000 M. CiesielskiDatapath Synthesis21 Geometric Orientation R i = orientation parameter X, Y R i = 1 Xdim Ydim Xdim – perpendicular to poly Ydim – along poly gate WiWi HiHi X, Y R i = 0 Xdim Ydim W i = Xdim i R i + Ydim (1- R i ) H i = Ydim i R i + Xdim (1- R i )

22 © 2000 M. CiesielskiDatapath Synthesis22 Modeling of L-shape Components Modeled as a pair of abutting rectangles H2H2 W1W1 W2W2 H1H1 P i = P j = 1 W1W1 H1H1 H2H2 W2W2 P i = P j = 0 X 2 – X 1 = W 2 P - (H 1 – H 2 ) (1- P) Y 2 – Y 1 = W 2 (1 - P) - (H 1 - H 2 ) P P = P 1 = P 2

23 © 2000 M. CiesielskiDatapath Synthesis23 Selection of Component Instances Selection parameter, S i (k = 2 instances) Easy extension to arbitrary k. S i = 0S i = 1

24 © 2000 M. CiesielskiDatapath Synthesis24 Boundary Constraints  bi < 0 for sharable components  bi > 0 for others  bi Margin: X i – W i >  bi X i < X0 –  bi Y i – H i >  bi Y i < Y0 –  bi For each component i Recall: W i, H i = f(R i )

25 © 2000 M. CiesielskiDatapath Synthesis25 Non-overlapping Constraints i Q ij = 0 j Q ij = 1 j Binary variable Q ij = 0 (vert), = 1 (horiz) X j - X i >= DimX j - L * (1 - Q ij ) +  sep Y j - Y i >= DimY j - L * Q ij +  sep

26 © 2000 M. CiesielskiDatapath Synthesis26 Optimization Problem (MILP) Minimize –the cell height, Y0 Subject to – boundary constraints – non-overlapping constraints – component shape constraints – component selection constraints fixed Y0

27 © 2000 M. CiesielskiDatapath Synthesis27 Sample Flow

28 © 2000 M. CiesielskiDatapath Synthesis28 Final layout

29 © 2000 M. CiesielskiDatapath Synthesis29 MILP: Complexity Issues Reduce number of placeable components and variables – merging (pre-processing) Reduce number of integer variables – component grouping Q AB Group AGroup B Q xy = Q AB for  x  A and  y  B

30 © 2000 M. CiesielskiDatapath Synthesis30 Results - routed layouts PG9PB7CS15MU9 Cell height

31 © 2000 M. CiesielskiDatapath Synthesis31 Conclusion & Future Work Automation of datapath layout – fast – within acceptable area overhead (5 - 10%) Post-processing Iterative improvement Hierarchical placement Grouping algorithm

32 © 2000 M. CiesielskiDatapath Synthesis32 Post-processing Improve the result of geometric placement Well minimization: improve manufacturability Mirroring along both axes Efficient MILP model and formulation Net length minimization: simplify routing Mirroring along both axes Constrained optimization problem Simple but effective MILP model and formulation

33 © 2000 M. CiesielskiDatapath Synthesis33 Post-processing –Net length minimization Mirroring Swapping Moving –Well minimization Mirroring –Layout compaction

34 © 2000 M. CiesielskiDatapath Synthesis34 Well minimization – Model

35 © 2000 M. CiesielskiDatapath Synthesis35 Well minimization – overlap weights Mirroring affects the overlap weights

36 © 2000 M. CiesielskiDatapath Synthesis36 Well minimization – Formulation Objective: Max  Z ij subject to Z ij = (1 - m i - m j + m ij ) v ij 0 + (m i - m ij ) v ij 1 + (m j - m ij ) v ij 2 + m ij v ij 3 where m i = 1 if i is mirrored 0 otherwise (i,j) m ij = m i AND m j m ij <= m i m ij <= m j m ij  m i + m j - 1

37 © 2000 M. CiesielskiDatapath Synthesis37 Well minimization – Example

38 © 2000 M. CiesielskiDatapath Synthesis38 Net length minimization - Approach Net length model –Half perimeter of the bounding box of the net scope (pins) Minimize the weighted sum of net length

39 © 2000 M. CiesielskiDatapath Synthesis39 Net length minimization - Modeling Mirroring effects the pin location

40 © 2000 M. CiesielskiDatapath Synthesis40 Net length minimization - Formulation Objective: Min  L i subject to Xp j = Xc q - (1 - Mx q - My q + Mxy q ) d x + (Mx q – Mxy q ) d x - (My q – Mxy q ) d x + Mxy q d x where : j  Pins, q  Comps,Mxy = Mx AND My Xc q = center coordinate of component q i  Nets

41 © 2000 M. CiesielskiDatapath Synthesis41 Net length minimization – Example

42 © 2000 M. CiesielskiDatapath Synthesis42 Results - interval overlaps Interval overlap PG9PB7CS15MU9CMU82X

43 © 2000 M. CiesielskiDatapath Synthesis43 Results - net length PG9PB7CS15MU9 Net length CMU82X

44 © 2000 M. CiesielskiDatapath Synthesis44 Conclusions & Future Work Automation of datapath layout – fast within acceptable area overhead Improvement –routability, manufacturability –delay, area Component swapping Global routing phase after post-processing Iterative group relaxation Efficient algorithms for grouping


Download ppt "© 2000 M. CiesielskiDatapath Synthesis1 ANALYTICAL APPROACH TO CUSTOM DATAPATH SYNTHESIS Serkan Askar, Maciej Ciesielski Department of Electrical & Computer."

Similar presentations


Ads by Google