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FPGA 99 1 Universität Tübingen Technische Informatik Karlheinz Weiß UT Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System.

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Presentation on theme: "FPGA 99 1 Universität Tübingen Technische Informatik Karlheinz Weiß UT Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System."— Presentation transcript:

1 FPGA 99 1 Universität Tübingen Technische Informatik Karlheinz Weiß UT Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System Karlheinz Weiß Thorsten Steckstor Gernot Koch Wolfgang Rosenstiel

2 FPGA 99 2 Universität Tübingen Technische Informatik Karlheinz Weiß UT Outline  Introduction  Emulation environment SPYDER-CORE-P1  Benchmark example: Actuator-Sensor-Interface (ASI) master unit  Embedded system performance analysis  Improving hw/sw partitioning  Analysis results of different FPGAs  Conclusion

3 FPGA 99 3 Universität Tübingen Technische Informatik Karlheinz Weiß UT Introduction  Embedded systems in the industrial automation - Application specific software running on a microcontroller - Application specific hardware implementation using a FPGA - Constraints + Systems per year: <1000 (ASIC design to expensive) + Typical gate range: < gates + Cost sensitive applications needs best exploitation of all FPGA resources + Hard real-time requirements (reaction times of about 200µs)  Motivation from a embedded system designers point of view - Novel FPGAs getting rising importance - FPGA evaluation (chip architectures and design tools) - Show advantages through exploitation of on-chip features - Give feedback to FPGA architecture designers

4 FPGA 99 4 Universität Tübingen Technische Informatik Karlheinz Weiß UT Emulation  Embedded system with complex internal system behavior  Emulation is very close to the final target system to get a detailed internal view  Emulation gives answers to the following questions: - What is the minimum clock speed? - How much performance is consumed by the RTOS? - What is the best hw/sw partitioning to solve the bottleneck? - What is the best FPGA architecture and the effect of on-chip features?

5 FPGA 99 5 Universität Tübingen Technische Informatik Karlheinz Weiß UT Emulation environment: SPYDER-CORE-P1 DRAM 1-128MB Embedded PowerPC PPC MHz 32 bit microcontroller bus microcontroller core CORE-P1 AT-ISA add-on board extension headers Actel add-on II FPGA architectures Xilinx XC6000 Xilinx XC4000 I 8 Bit I/O bus peripherie devices Internet AT-ISA bus III FLASH 8MB Ethernet 10MBit 2 serial ports DPRAM 2KB driver analog module

6 FPGA 99 6 Universität Tübingen Technische Informatik Karlheinz Weiß UT Benchmark example: ASI master unit  Novel microcontroller in combination with dedicated hw inplemented on different FPGA architectures  Fast response times to external events  Sensitive hw/sw partitioning, which heavily influences the entire system  Sophisticated software architecture  Typical embedded system, which shows the benefit of exploiting FPGA on-chip features ASI master 0SBA4A3A2A1A0I4I3I2I1PB1 master call 0I4I3I2I1I0PB1 slave answer ASI power supply ASI slave ASI slave ASI communication system ASI real-time critical constant (220µs) 4O 4I 4O up to 32 slaves

7 FPGA 99 7 Universität Tübingen Technische Informatik Karlheinz Weiß UT Benchmark example: Initial Implementation DRAM 1-128MB Embedded PowerPC PPC MHz 32 bit microcontroller bus microcontroller core CORE-P1 AT-ISA add-on board extension headers Actel add-on II FPGA architectures Xilinx XC6000 Xilinx XC4000 I 8 Bit I/O bus peripherie devices Internet AT-ISA bus III FLASH 8MB Ethernet 10MBit 2 serial ports DPRAM 2KB driver analog module microcontroller register interface tele_receive tele_send ASI-UART from to analog module Initial ASI hardware (single channel) Target chip: XC4005E, 166 CLBs, utilization: 85% SPYDER-CORE-P1 hardware VxWorks real-time operating system int_servicecontrolC-server http- server ASI application sofware TCP/ IP Target chip: A1225XL 436 logic mod. utilization: 94% Target chip: XC cells utilization: 37%

8 FPGA 99 8 Universität Tübingen Technische Informatik Karlheinz Weiß UT Embedded system performance analysis

9 FPGA 99 9 Universität Tübingen Technische Informatik Karlheinz Weiß UT Embedded system performance analysis  Two motivations to improve embedded system performance - first: multi master design + performance gap - second: reduce system cost + reduce CPU clock speed < 33Mhz + shorten external bus size < 32 Bit + slower memory access times  Solution: improve hw/sw partitioning - slightly increasing FPGA costs - exploiting on-chip features

10 FPGA Universität Tübingen Technische Informatik Karlheinz Weiß UT Improving hw/sw partitioning

11 FPGA Universität Tübingen Technische Informatik Karlheinz Weiß UT Improving hw/sw partitioning improved hardware implemtation

12 FPGA Universität Tübingen Technische Informatik Karlheinz Weiß UT Analysis results of different FPGAs XC4000 (CLB)XC6000 (cells)Actel (logic modules) 436 A1225XL 94% XC % XC4005E 85% initial resources target chip utilization int_service FSM on-chip memory additional resources28%127%187% new target chipXC4006EXC6209A32100DX new utilization83% 35% / 89% initial implementation improved implementation

13 FPGA Universität Tübingen Technische Informatik Karlheinz Weiß UT Conclusion  Actel antifuse technology - advantage: no external PROM decreases costs and space - disadvantage: no on-chip RAM in devices < gates + neccessary in a wide area of cost effective applications + we recommed to introduce on-chip RAM features in smaller devices  Xilinx XC4000 SRAM-based technology - disadvantage: external PROMs - advantage: fine grained on-chip SRAM feature + very good scalable to the requirement of the application + easy to implement different SRAM functionality  Xilinx XC6000 partial reconfigurable SRAM technology - recommendation: embedded flip flops in the address space of a microcontroller should be considered in future FPGAs

14 FPGA Universität Tübingen Technische Informatik Karlheinz Weiß UT Demonstrator: Industrial shelf model


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