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Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models Peter Feldmann*, Soroush Abbaspour, Debjit Sinha, Gregory.

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Presentation on theme: "Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models Peter Feldmann*, Soroush Abbaspour, Debjit Sinha, Gregory."— Presentation transcript:

1 Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models Peter Feldmann*, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta IBM T.J. Watson Research, Yorktown Heights, NY* IBM Systems & Technology Group, Hopewell Junction, NY June 11, 2008 DAC 2008, Anaheim, CA

2 2 Introduction  Traditional gate delay characterization Capacitive loads only Output signal assumed to be a ramp Delays and slews functions of input slew and capacitive load  Sources of inaccuracy Non-ramp-like waveforms Highly resistive modern day interconnects Inductive effects

3 3 Concept of effective capacitance (C eff ) Ideally match output waveform using C eff instead of RC load  Match charge in interval [t v=0, t v=0.5Vdd ] Single number – not accurate enough Time (ps) Current / Voltage at A RC Line C eff A A

4 4 Recent industry trends  Non-linear current source models (CSM) Effective Current Source Model (ECSM)  Cadence, Magma  Driving current I = f I (V, C dyn )  For given input slew, characterization data stored as: Time =  T (V, C) CLoad InSlew dotLib + ECSM Op Voltage Waveform Table t1t1 t2t2 t3t3 t4t4 t5t5 t6t6 v1v1 v2v2 v3v3 v4v4 v5v5 v6v6 Op Voltage Time PWL* *PWL = Piece Wise Linear

5 5 Recent industry trends (contd.)  Non-linear current source models Composite Current Source (CCS)  Synopsys  Driving current I = f I (V, C dyn )  For given input slew, characterization data stored as: I =  I (T, C) CLoad InSlew dotLib + CCS Op Current Waveform Table PWL t1t1 t2t2 t3t3 t4t4 t5t5 t6t6 I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 Io t0t0 Output Current Time

6 6 Simulating current source models  For a given input ramp (slew) Transformations required (T ~ time)  T =  T (V, C)  I = f I (V, C)  I =  I (T, C)  I = f I (V, C)  Approximation, accuracy loss Accurate transformation requires  High degree of continuity  Smoothness

7 7 Contributions  Accurate and efficient analytical framework for driver waveform computation Novel algorithm for simulation of CSM  Simulation along V axis and not T axis Avoids time domain integration (requires smooth data, time step control etc.) Requires model in MVTM * form: T=  T (V, C)  Same as industry standard characterized data  No transformation to I = f I (V, C)  Eliminates approximations  Assumes monotonic piecewise linear output voltage waveform * Multiple Voltage Threshold Model

8 8 Dynamic capacitance concept (C dyn )  A driver’s time varying instantaneous equivalent load capacitance  Generalization for multiple voltage threshold model RC Line i(t) v(t) Time

9 9 Driver waveform computation  Assume current state T p, V p  Goal: Given V p+1, calculate T p+1  Charge supplied by driver Assuming change in V linear for T p Output Voltage Time TpTp unknown

10 10 Driver waveform computation (contd.)  Charge flowing into load in T p : Q p Can be expressed analytically as f(T p+1 )  Equate charge Unknowns: T p+1, C d,p  Use information from driver model (characterization table) RC Line EQ1 EQ2

11 11 Small testcase setup  Test common gates (INV, BUFF, AND, XOR) driving RC interconnect loads Compare near-end waveforms  SPICE  Traditional C eff approach  Proposed approach denoted as MVTM (Multi voltage threshold model) Ramp of 20ps slew at gate input Krylov method used to compute interconnect delay

12 12 Results Cn (fF) R  (Ohms) Cf (fF) Gate DelayNear-end SlewWire Delay CeffMVTMSpiceCeffMVTMSpiceCeffMVTMSpice Delay and slew values are in psecs RR CnCn CfCf 100  m RC Line

13 13 Small testcase results (contd.) In this experiment, the CMOS gate under test is a NAND2. The C n =20fF, C f =480fF, R  =500. This experiment shows that MVTM follow SPICE while the Ceff technique incurs about 20% error in gate delay and about 40% in slew calculation.

14 14 Large testcase setup and results  Tested on large microprocessor units 65 nm designs  Design, runtime and memory stats +5% +20%

15 15 Large testcase results (contd.)  Timing comparison with traditional C eff based gate delay calculation Largest difference paths analyzed in SPICE Observed MTVM models more accurate  Within 3% of SPICE Design Num. timing points compared Comparison type Max diff (ps) Avg. diff (ps) 12.45M Arrival time Slew M Arrival time Slew

16 16 Summary  Accurate and efficient timing analysis Based on Multiple Voltage Threshold Models Realistic load models can be handled  Novel algorithm for simulation of CSMs Eliminates need of intermediate transformation of models to I = f I (V, C) Compatible with industry standards Acceptable runtime  Limitations, assumptions Driver input voltage waveform ramp Monotonic output voltage waveform


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