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© H. Heck 2008Section 2.21 Module 2:Transmission Lines Topic 2: Basic I/O Circuits OGI ECE564 Howard Heck
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.22 Where Are We? 1.Introduction 2.Transmission Line Basics 1.Transmission Line Theory 2.Basic I/O Circuits 3.Reflections 4.Parasitic Discontinuities 5.Modeling, Simulation, & Spice 6.Measurement: Basic Equipment 7.Measurement: Time Domain Reflectometry 3.Analysis Tools 4.Metrics & Methodology 5.Advanced Transmission Lines 6.Multi-Gb/s Signaling 7.Special Topics
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.23 Contents Push-Pull Transmitters (Drivers) Operation Modeling Open Drain Transmitters Operation Modeling Receivers Operation CMOS Receivers Modeling Driving a Transmission Line Summary References Appendix
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.24 Push-Pull Transmitters V SS V CC VssV CC V in V out 0.00.51.01.52.02.5 V out [V] I out -100 -80 -60 -40 -20 0 20 40 60 80 100 [mA] nMOS pMOS time [ns] 02468101214161820 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V out [V]
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.25 Modeling Push-Pull Transmitters RSRS V out V SS VSVS R pmos R nmos V out V SS V CC Elements Transient voltage source Output resistance Known parasitics (usually capacitance) Thevenin Equivalent Asymmetric Switched Resistors Elements DC voltage source Output resistances (pull-up & pull down) Known parasitics (usually capacitance) Use the asymmetric model when your output transistors may have different impedances.
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.26 Open Drain Transmitters Characteristics (e.g. V-T curve) are specified into a standard load. V in V out I out V TT R TT V SS V CC V SS V CC V in V out V OL time [ns] 0 0.5 1 1.5 2 02468101214 V out [V] -10 0 10 20 30 40 50 60 70 80 90 0.0 0.51.01.52.02.5 V out [V] I out [mA] nMOS I out [mA] pMOS I out [mA]
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.27 Model elements Time varying current source in parallel with resistance…or A switch in series with a resistance connected to ground Parasitics External termination supply ( V TT ) and resistor ( R TT ) Modeling Open Drain Transmitters I out V TT R TT V V in V out V TT R CC P1 N1 N2 N4 N3 Example: GTL circuit (1991).
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.28 Receivers The input buffer (receiver) is an amplifier. It takes the input signal and restores it to on-chip signal levels CLK D Q Receiver To Core Differential receivers require two input signals. A differential receiver can be converted to a single ended receiver by connecting one of the inputs to a reference signal ( V ref ). V in + V - V out V in V ref V out
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.29 Single Ended ReceiversInverter Used for full swing signals (TTL, CMOS). Resistor and diodes are for ESD protection. Diodes “shunt” large voltage spikes into the supplies. Resistor limits the amount of current that is sunk in an ESD event. V CC Current limiting resistor (40 -200 ) ESD diodes Input pad (100mm x 100mm) Current Mirror Made by connecting one of the diff amp inputs to a stable reference input voltage. Often used in low swing designs, such as GTL+. V in V ref V out
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.210 Modeling Receivers As long as we’re using FETs (CMOS), the models that we use for interconnect analysis and simulation can be pretty simple. Gate oxide acts as an insulator, so the input transistor represents a high impedance to a static signal (usually an infinite resistance). However, the ESD protection circuitry and the gate of the receiver can contain significant capacitance (2-5 pF). So, our simplest receiver model is a capacitor. As we’ve seen, the package is often modeled using lumped R, L, and C elements C pkg R L C rcv Example
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.211 Driving a Transmission Line: Voltage Divider Analogy A transmission line presents an impedance ( ) to the output driver (transmitter). Push-pull example: As a result, the circuit behaves like a voltage divider: VSVS trtr RSRS Z0Z0 V i, I i VSVS trtr RSRS Z0Z0 ViVi IiIi + - [2.3.1] [2.3.2]
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.212 Load Line Analysis A more general method is load line analysis: Model the output buffer as an I - V curve. For linear transmitter model, Ohm’s law says slope = -1/ R S for a pull-up device From Ohm’s law, the transmission line has slope = 1/ Z 0 (rising edge). The initial current/voltage waves are defined by the intersection of the two curves. Load line analysis = graphical technique for solving simultaneous equations in I & V.
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.213 Load Line Example 5V 12.5 50 I 012345 V [V] 0 50 100 150 200 250 300 350 400 I [mA] T-Line V=50I Driver V=5-12.5I 4.0V, 80 mA
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.214 More On Load Lines The voltage divider equation can be derived by solving the Ohm’s law equations for the output buffer and the transmission line. It is equivalent to a load line analysis for a low-high transition when there is no initial current flow. The slopes reverse for a high-to-low transition. We must also take into account initial voltage and current. So what? Why bother with load line analysis?
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.215 Summary Push-Pull and Open Drain drivers are both used in high speed designs. Receivers are amplifiers. We can use passive circuits to make approximate models for drivers and receivers. The output buffer and impedance (for a voltage mode driver) of the transmission line look like a voltage divider to the driven signal. Load line analysis provides a general method for predicting the initial signal amplitude on a transmission line. I will use the following terms synonymously: Transmitter Driver Output Buffer Receiver Input Buffer Transceiver I/O Buffer
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.216 References S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), New York, 2000. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998. S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998. N. Wang, Digital MOS Integrated Circuits: Design for Applications, Prentice Hall, Englewood Cliffs, NJ, 1989. R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1 st edition, 1995. H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.
Basic I/O Circuits ECE 564 © H. Heck 2008 Section 2.217 Appendix: Tri-State Transmitters Tri-state drivers are used for bi-directional and/or multi- drop buses. They are push-pull circuits with enable/disable logic. When multiple components can drive the same circuit, we need a way to disconnect inactive drivers. V out Output Enable Data OEDataV out 00X 01X 101 110 When output is enabled (OE=1), the circuit acts as an inverter. When output is disabled (OE=0), both output transistors are cut-off.
© H. Heck 2008Section 2.31 Module 2:Transmission Lines Topic 3: Reflections OGI ECE564 Howard Heck.
© H. Heck 2008Section 2.41 Module 2:Transmission Lines Topic 4: Parasitic Discontinuities OGI EE564 Howard Heck.
Module 4: Metrics & Methodology Topic 2: Signal Quality
© H. Heck 2008Section 3.21 Module 3:Analysis Techniques Topic 2: Bergeron Diagrams OGI EE564 Howard Heck.
© H. Heck 2008Section 2.71 Module 2:Measurement Topic 7:Time Domain Reflectometry OGI EE564 Howard Heck.
© H. Heck 2008Section 1.11 Module 1Introduction Topic 1Overview OGI EE564 Howard Heck I1I1 V1V1 I2I2 V2V2 dz.
© H. Heck 2008Section 4.11 Module 4:Metrics & Methodology Topic 1: Synchronous Timing OGI EE564 Howard Heck.
© H. Heck 2008Section 4.41 Module 4:Metrics & Methodology Topic 4: Recovered Clock Timing OGI EE564 Howard Heck.
© H. Heck 2008Section 5.21 Module 5:Advanced Transmission Lines Topic 2: Intersymbol Interference OGI EE564 Howard Heck.
Module 2: Transmission Lines Topic 1: Theory
© H. Heck 2008Section 3.11 Module 3:Analysis Techniques Topic 1: Lattice Diagrams OGI EE564 Howard Heck.
© H. Heck 2008Section 2.51 Module 2:Transmission Line Basics Topic 5: Modeling & Simulation OGI ECE564 Howard Heck.
Module 5: Advanced Transmission Lines Topic 3: Crosstalk
ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison
CMOS Logic Circuits.
© H. Heck 2008Section 5.41 Module 5:Advanced Transmission Lines Topic 4: Frequency Domain Analysis OGI ECE564 Howard Heck.
Chapter 4 Logic Families.
Chapter 1 Introduction to Electronics
Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
© H. Heck 2008Section 4.31 Module 4:Metrics & Methodology Topic 3: Source Synchronous Timing OGI EE564 Howard Heck.
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