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Combinatorial networks- II 1 Digital Systems M. Adder 2 Let’s see the truth table of a combinatorial network whose output values correspond to the numerical.

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Presentation on theme: "Combinatorial networks- II 1 Digital Systems M. Adder 2 Let’s see the truth table of a combinatorial network whose output values correspond to the numerical."— Presentation transcript:

1 Combinatorial networks- II 1 Digital Systems M

2 Adder 2 Let’s see the truth table of a combinatorial network whose output values correspond to the numerical values of a 2-bit adder (Half Adder) ab Sum Carry Sum = a  b = a exor b Carry=ab Sum Carry a b HA b aSum Carry Let’s see the truth table of a combinatorial network whose output values correspond to the numerical values of a 3-bit adder (Full Adder). Canonical synthesis SP abc Sum Carry R= !abc+a!bc+ab!c+abc = !abc+a!bc+ab!c+abc+abc+abc = ab(c+!c) + ac(b+!b) + bc(a+!a) = ab + ac + bc For the carry we have also Added terms (idempotence) (It could have been intuitively deduced since two 1’s are enough for generating a carry !!!) HA b a Sum1 = a exor b Carry1=ab HA c Sum Carry2=c(a exor b) Carry Full Adder Sum2 =a exor (b exor c) Sum = !a!bc+!ab!c+a!b!c+abc=!a(!bc+b!c)+a(!b!c+bc) =!a(b exor c)+a!(b exor c) = a exor (b exor c) Carry = !abc+a!bc+ab!c+abc = c(a exor b) + ab(c+!c) = c(a exor b) + ab

3 Adder 3 HA a0a0 S0S0 R b0b0 To add a binary number of n bit, n-1 FA e 1 HA must be used FA a1a1 S1S1 R b1b1 a2a2 S2S2 R b2b2 NB: Normally the integrated circuits provide 4 bit FAs. With this network a new logical level (delay) is introduced for each couple of bit to be added. It must be remembered however that this is a combinatorial network which corresponds to a truth table which can be always synthesised as a two levels network (minimum delay). In the 4 bit integrated FAs the carry is always generated with a two level network in order to accelerate the operations of the next level FA.

4 4 FA 4-bit 74X283 Analyse the circuit with Xilinx Schematic available in the examples

5 5 FA 8-bit Analyse the circuit with Xilinx Schematic available in the examples

6 Carry Look Ahead I 6 With 4 bit full-adders a fast carry generator is implemented Two carries are defined: carry generate (G) and carry propagate (P) Considering the sum of two binary numbers with A i and B i the bits in the i-th position we define G i the logical product A i *B i (1 only if both bit are 1) and P i the logical sum A i or B i which if A i =1 or B i =1 produces arithmetically always a carry (C i+1 ) if there is a carry (C i - index i-1) It follows that C i+1 =G i or P i C i (G i =1 if A i =B i =1; P i C i =1 if A i or B i =1 and C i =1) therefore if G i =1 then P i C i has no infuence. If G i =0 and P i =1 then P i C i =C i and therefore wr have (here symbols + indicate always or) C 1 =G 0 +P 0 C 0 C 2 =G 1 +P 1 C 1 = G 1 + P 1 (G 0 +P 0 C 0 )= G 1 + G 0 P 1 + C 0 P 0 P 1 etc. and then substituting C 4 = G 3 +G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 +C 0 P 0 P 1 P 2 P 3 (carry of the 4 0h bit) Two level network (SP)

7 7 Carry Look Ahead II A combinatorial 4-bit Carry Look Ahead generator produces CG 3 e CP 3 (FA 0-3 indexes) Carry Generate 4 CG 3 = G 3 +G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 Carry Propagate 4 CP 3 =P 0 P 1 P 2 P 3 C 4 = G 3 +G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 +C 0 P 0 P 1 P 2 P 3 to generate C 5 C 5 = G 4 + P 4 C 4 = G 4 + P 4 (G 3 +G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 +C 0 P 0 P 1 P 2 P 3 ) = G 4 + P 4 CG 3 + P 4 CP 3 C 0 where CG 3 and CP 3 are generated by the four of the preceding FA. Normally CG i the Cp i s and the C i s of several cascaded Fas are inserted in a combinatorial circuit which allows to speed up the operations. The are ohter methodologies for the Carry Look Ahead generation NB In the english texts very often CP is indicated as PG and CG as GG A 4 *B 4 A 4 +B 4 Two level expression(SP)

8 Full adder per adding n-bit 8 4-bit Full Adder B0B0 B1B1 B2B2 B3B3 A0A0 A1A1 A2A2 A3A3 C0C0 C4C4 B4B4 B5B5 B6B6 B7B7 A4A4 A5A5 A6A6 A7A7 C7C7

9 9 Arithmetic Logic Unit Multifunction Circuit (including a 4-bit FA)

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11 74LS181 11

12 S3 S2 S1 S0 Mode=1 12 (Partial ) analysis of the previous circuit Signals positive true (H=1, L=0) 0000!AAAplus1 0001!(A+B)A+B(A+B)plus1 0010!ABA+!B(A+!B)plus Minus 1zero 0100!(AB)A plus A!B(A+A!B) !B(A+B) plus A!B (A+B)plus A!B plus1 0110AxorBAminusBminus 1 A minusB 0111A!BA!Bminus1A!B 1000!A+BAplusABAplusABplus1 1001!(AxorB)AplusBAplusBplus1 1010B(A+!B)plusAB(A+!B)plusABplus ABABminus1AB AplusAAplusAplus1 1101Aor!B(A+B)plusA(A+B)plusAplus1 1110AorB(A+!B)plusA(A+!B)plusAplus1 1111AAminus 1A Mode=0 Cin=1Cin=0

13 13 M=1 all internal carries are inhibited and the device implements the table logical functions M=0 internal carries are enabled and the device implements the table arithmetic functions Three carries: Ripple Carry (Carry_Out = C 4 ), the «normal» arithmetic carry Two carry look-ahead carries : carry propagate (CP 3 ) and carry generate (CG 3 ) An output is available for AeqB (A equal B) open collector for wired AND. The equal is meaningful when S = 0110 with Mode=0 and Carry_in=1. AeqB is activated in fact if Output =1111. The performed operation A-B-1 has Output=1111 if A=B If S=0110 the Carry_Out can be used for the comparison of two absolute value numbers A and B 74LS181 Carry_InCarry_OutComparison 11 ABAB 10A>B 01A

14 14 Carry Propagate (CP 3 ) Carry Generate(CG 3 ) Carry_Out (C 4 ) Carry_In Mode A(3:0) B(3:0) S(3:0) AeqB Output(3:0)

15 15 N.B. Note 1 indicates that the datum is left shifted one position (2 multiply) Logical sum Somma numerica Numerical subtraction See next slide

16 16 S(3:0)=LHHH M=H Positive true Negative true Logic Logic A i B i Z i A i B i Z i p A i B i Z i n L L L L H L H L H H H L Z i p =A i !B i Z i n=A i +!A i !B i =A+!B i N.B. Here we consider ONLY the High and Low signal values. The logical intepretation is different if the logic is either positive or negative true Example Circuit electrical behaviour (check the schematic with Xilinx)

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18 18

19 19 Mux_8_to_1

20 20 entity MUX_8_1 is Port ( INPUT : in STD_LOGIC_VECTOR (7 downto 0); X : in STD_LOGIC_VECTOR (2 downto 0); Enable: in STD_LOGIC; Z : out STD_LOGIC); end MUX_8_1; architecture Behavioral of MUX_8_1 is begin processo: process(X,Input) begin if Enable = '0' then Z <= '0'; else case X is when "111" => Z <= Input(7); when "110" => Z <= Input(6); when "101" => Z <= Input(5); when "100" => Z <= Input(4); when "011" => Z <= Input(3); when "010" => Z <= Input(2); when "001" => Z <= Input(1); when "000" => Z <= Input(0); when others => null; -- always necessary end case; end if; end process processo; end Behavioral;

21 21 DEMUX (or decoder)  Two ways demultiplexer: the input logical value is redirected to one of the two outputs (Z 1 e Z 2 ) according to value of the control signal (C).  The truth table and the canonical function of a DEMUX with four outputs and two control signals C 1 e C 2 ?  This circuit is called also DECODER because if in n-way demux the input a is at logical value 1, only one output is at logical value 1, that corresponding to one of the 2 n control input binary configurations (only one in this figure – c). The circuit therefore “decodes” the input binary value (that is corresponds to the control signals binary value) A C Z1Z1 Z2Z2

22 22 Example Y2N = !((!AB!C)G1!G2AN!G2BN) Decoder 3:8. Control inputs are A,B and C the output YiN [corresponding to the binary value (i) of ABC (C=> 2 2, B=>2 1, A=>2 0 )] is 0 (Low) only if enable inputs G1=H and G2AN=G2BN=L otherwise all outputs are H.

23 23

24 comparator This 8 bit comparator is a combinatorial network whose inputs are two binary 8 bit numbers (absolute value). It checks whether they are identical and/or whether one is greater (or lower) than the other. It has two negative true inputs G1N e G2N which enable the two sections of the network. G1N enables to check whether the two numbers are identical while G2N enables the greater/lower section. The first section consists of XNORs of all bits with the same index (i.e. P 0 and Q 0 ). A XNOR is 1 if the bit are identical. The 8 outputs are NANDed with G1N: its output PEQN is 0, negative true, if all XNOR bis are 1. The second section is made of 8 ANDs with increasing number of inputs: they compare the bit starting from the most significant…. Analyze the network

25 25 See the examples Outputs negative true

26 26 process (P,Q,G1IN, G2IN) --- sensitivity list variable I : Integer; begin if G1IN='0' then if P=Q then PEQQN <= '0'; else PEQQN <= '1'; end if; else PEQQN <= '1'; -- G1IN=1 end if; if G2IN='0' then if P/=Q then if P>Q then PGRQN <= '0'; PLTQN <= '1'; elsif P

27 Minimum cost networks 27 The“cost” (which in this context means “complexity”) has no unique meaning and depends on many factors In our context the minimum cost refers to the minimum number of devices needed to implement a two levels combinatorial logical function. Notice that the minimum cost implementations can be more than one Minimum expression: an expression which corresponds to the minimum cost implementation Normal expression: an SP (or PS) expression. Two levels. The canonical expressions are normal but they are not the only normal expressions Non-redundant expression: a normal expression SP (or PS) whose terms are all necessary. Examples Example 1 F= ab+bc+ad: no product can be removed without modifying the truth table. Example 2 F=b!c+ac. Expression b!c+ab+ac (which corresponds to the same truth table) wouldn’t be non-redundant since term ab could be removed without altering the truth table A minimum cost network in our case is a normal non-redundant expression In the following slides we use only SP for sake of simplicity (being the extension to the PS straightforward– duality)

28 Minimum cost networks 28 Implicant: a product term of n or less input variables which is 1 only for input combinations where the function is not 0  Example F= abc + ac + cd + ad (all products are implicant) Prime implicant: an implicant which is not an implicant any more if a letter is removed  Esempio F= ac + cd (both products are prime implicants) Essential prime implicant: an implicant which is the only one having value 1 for some input configurations where the function must be 1 (that is there are no other prime implicants which cover one ore more «1s» of the function)  ExampleF= abc + ac + cd (abc is not essential)  It follows that a minimum cost network is an non-redundant sum of essential prime implicants (only those strictly necessary)

29 Karnaugh maps 29 Bi-dimensional representation of the truth table of a function of 2,3,4,5 and 6 variables, whose values are indicated on the border of the maps so that two adjacent input configurations (differing for one single bit) are topologically adjacent. Obviously the number of the map squares is a power of two (all possible input combinations) a b a bc ab cd ab cd ab cd e=0e=1

30 30 Karnaugh maps The Karnaugh maps can be easily used to underline the adjacences of the input configurations where the function is «1» allowing to graphically implement the algebra theorems (i.e. ab + a!b = a) The input adjacence in the Karnaugh maps must be interpreted in spherical sense. In the following example the square a=0, b=0, c=0 and d=1 (red) is adjacent to square a=1, b=0, c=0, d=1 (green) in addition to 0001 and The grahical representation allows to easily detect the input confgurations which differ for a single bit ab cd adjacent

31 31 Karnaugh maps Let’s consider the truth table of a three inputs function abc F = !a!b!c+!a!bc+!ab!c+a!b!c+abc = !a!b!c+!a!b!c+!a!b!c+!a!bc+!ab!c+a!b!c+abc = = !a!b+!b!c+!a!c+abc (much simpler) What was exploited ? The adiacences of the product terms of the canonical expression. But the same can be found it in a Karnaugh map!!! And the same operations executed using the algebra theorems can be derived by analyzing the adjacents groups. The greatest rectangular groups of «ones» must be found (a rectangular group is a group of 2 n squares each one having n adjacent squares) which cannot be enlarged without including zeroes. The product terms (implicants) of minimum complexity (prime implicants) can be obtained observing the input variables which do not change withing the group (taken as true if present with value 1 and viceversa). Spherical adjacences!! a bc Coverture: each “one” of the function must be covered at least by one group (but also by more than one – idempotence) F=+ abc!a!b !a!b!c+!a!bc + !b!c !a!b!c+a!b!c + !a!c !a!b!c+!ab!c Idempotence Mintermin alone !

32 32 Karnaugh maps a bc F 1 = !b+ac+!a!c ab cd Here we have no adjacent minterms => canonical synthesis !!! ab cd F 3 = !a!b!cd+!a!bc!d+!ab!c!d+!abcd+ab!cd+abc!d+a!b!c!d+a!bcd All product terms are prime implicants and are essential too since they cover «ones» not covered by other prime implicants !b!d + !bc + !ad +!a!c + b!cd + F2=F2= ac!d The implicant !a!b (dashed) would be prime but it is not essential

33 33 Karnaugh maps ab cd ab cd e=0e=1 The two 4 bits maps differ for the 5-th variable (e) and can be interpreted as two spherical surfaces having the same center F= !b!d + !a!c!e + a!bc + ade + ac!d + bcde

34 ab cd ab cd e=0e=1 F= In this case the prime rectangular groups of «zeros» must be found (prime implicated). The sum terms of minimum complexity can be derived by the squares variables which do not change, taken as negate if 1 and viceversa PS Synthesis (!a+c+!d+e) (!a+!b+c+d) (!a+!b+!d+e) (a+!b+!c+e) (a+b+!c+!d) (a+c+!d+!e) (a+!b+d+!e)

35 ab cd Karnaugh maps !b!d + bd + !a!bc F= ab cd !b!d + F= bd + !acd The two synthesized functions are equivalent, of the same complexity and both consisting of prime implicants. This can occur very often General rule: in the maps detect first the ones (zeros) which are covered by only one implicant (implicated) and use the corresponding rectangular group (essential). The the other ones (zeros) must be covered. There are however cases (as that of the figure) where there are no ones (zeros) covered by a single prime essential implicant (implicated)

36 36 Karnaugh maps Combinatorial neworks not fully specified: for some input combinations the outputs are not defined (normally this is the case of impossible input combinations:i.e. 7 segments where the only input values are 0 to 9). In this case the function in the map can be «don’t care» (normally indicated by x or - ) and the value can be used as “one” and “zero” in order to obtain implicants (implicated) of minimum complexity. The don’t cares can be in turn interpreted as zero or one according to the needs ab cd x1 x x1 11 F=!b + a+ !c!d ab cd The table which has been actually synthesized X => 1 X => 0

37 37 f e = A + !BC ab cd Seven segments

38 38 Design with the Karnaugh maps - starting from the truth table - a packed BCD to binary converter when the max value of the packed BCD code is (19) and the even numbers must not be converted (packed BCD => Binary for odd numbers). What are the don’t cares? BCD | Binary |  | edcba | | | | | | | | | | All other input configurations are don’t cares Input Output

39 39 BCD | Binario |  | edcba | | | | | | | | | | b=    Synthesize the other functions Packed BCD to binary for odd numbers (Let’s synthesize the b function) Synthesize with Xilinx (abcde and  as busses – Binary(4:0) and BCD(4.0))

40 X1X1 X2X X3X3 x4x4 40 Z2 = x1x2 + x2x4 + !x3x4 Z1= x1x3 + x1x4 + x2x3 Can we derive the Karnaugh map from the SP (PS) expressions ?

41 41 6 variables Karnaugh maps ba dc ba dc ez=00 ez= dc ba dc ba ez=10 ez=11 F = !a!b!c!z + bc + a!b!cz + !a!ez F = (b+!a+z) (!b+c+z) (!b+!a+c+!z) (b+!c) (a+!e+!z) And for more variables?

42 42 Quine – McCluskey method (I) Two steps procedure Prime implicants identification Minimum set covering the function detection Table (algorithmic) method No limit for the variables number Software synthesizable Easy «don’t» care handling Grouped minterms Each group includes minterms with the same number of variables either true or complemented The minterms are listed numerically within the groups

43 43 Metodo di Quine – McCluskey (II) Example => f (A,B,C,D)=  m(4,5,6,8,9,10,13) with don’t care  i(0,7,15) (  is the logic sum - 4 => 0100, 13 => 1101 etc.) (In the following example the minterms are represented with the numerical value corresponding to each input variables configuration) -1-1 (g&n,h&m)  The the terms of column II are «combined» again in the following column (III) (if possible) provided they have the don’t care in the same position and differ b a single «one» (they can produce – by couples – the same result). The don’t care are not recombined otherwise we would go back to square one.(i.e. by recombining a and b we wouldo btain 0000 !!) The aim of the combinations is to obtain in steps increasingly simpler implicants until prime implicants are produced 01-- (c&i,d&g)  **** ^^^^^^^^ **^*^^**^*^^ Al groups with * are prime implicants (which cannot be recombined) **** The process is repeated until no more combinations are possible. ABCD Minterms grouping in the first column (in red the don’t cares) according to the number of «ones». Successive groups differ for a single «one» 0000 (0) 0100 (4) 1000 (8) 0101 (5) 0110 (6) 1001 (9) 1010 (10) 0111 (7) 1101 (13) 1111 (15) 0 «ones» 1 «one» and 3 «zeros» 2 «ones» and 2 «zeros» Comparison in the column I between the elements with N «ones» and those with N+1 «ones» and their combination in order to obtain less complex terms (column II). The combination corresponds to the use of the property a!b + ab= a(!b + b)=a. Synbol ^ if combined, * if not (0 & 4) a ^ ^ ^ I column II columns III column -000 (0 & 8) b 010- (4 & 5) c 01-0 (4 & 6) d 100- (8 & 9) e 10-0 (8 & 10) f 01-1 (5 & 7) g -101 (5 & 13) h 011- (6 & 7) i 1-01 (9 & 13) l -111 (7 & 15) m 11-1 (13 & 15) n ^^^^^^^^^^^^^^^^ Combination (don’t care in the same position N.B.g can be combined with two different terms (4&5&6&7) (5&7&13&15)

44 44 Metodo di Quine – McCluskey (III) method Coverture table (minterms columns – prime implicants rows) Obviously ONLY the real minterms must be covered, NOT the don’t care NB If a column has a single X the corresponding prime implicant is obviously essential a 0,4(0-00) b 0,8(-000) e 8,9(100-) f 8,10(10-0) l 9,13(1-01)  4,5,6,7(01--)  5,7,13,15(-1-1) 4XX4XX 5XX5XX 6X6X 8XXX8XXX 9XX9XX 10 X 13 X f (A,B,C,D)=  m(4,5,6,8,9,10,13) On the left all found prime implicants and in the columns the function minterms to be synthesized: X indicate which prime implicants covers which minterms of the functon

45 45 Quine – McCluskey (IV) method f = A!B!D + A!CD + !AB f l  0,4(0-00) 0,8(\000) 8,9(100-) 8,10(10-0) 9,13(1-01) 4,5,6,7(01--) 5,7,13,15(-1-1) 9XX9XX 13 X Then we search for the minimum set covering 9 and 13 The already covered columns are removed Columns 4,5 and 8 are automatically covered by essential prime implicants (see previous slide) 0,4(0-00) 0,8(-000) 8,9(100-) 8,10(10-0) 9,13(1-01) 4,5,6,7(01--) 5,7,13,15(-1-1) 4XX4XX 5XX5XX 8XXX8XXX 9XX9XX 13 X Essential

46 46 Integrated BCD adder

47 47

48 48

49 49 NAND (NOR) circuits Although the elementary logic operators (AND, OR, NOT) are available as IC or FPGA etc. it can be useful sometimes to use only one type of operator: NAND or NOR XZ X y Z 1 X y Z X y Z 1 X Y 1 Z ZX 1 Any two levels SP (PS) circuit can be implemented using only NANDs (NORs). Example: SP two-ways multiplexer. ( De Morgan)!! z a b c a z b c 1 z = ![(!(a!c) !(bc)] = a!c + bc (De Morgan)

50 3-state drivers OE IU OE=0 I U OE=1 I U I OE U Voltage ? OE I U 0 1 Z Z ?

51 OE=0 0 1 U=? U value ? What must be granted in this network ? When U has a meaningful logical value ? 1 U=? OE1 OE2 I1 I2

52 52 Common bus circuits Very often (and in particular in microprocessors based systems) many devices must drive– in different times - the same wire (in case of many devices with multiple wires the name used is bus) and multiplexers (for instance with many inputs – say 30 or 40) can’t be practical because of the circuit complexity. In this case devices with tri-state outputs are used that is devices whose outputs can be enabled (and in this case the output follows the logic of the circuit) or disabled (and in this case the circuit output is electrically disconnected from output connected to output pin). Typically tri-state circuits are buffer XY C=1 X C Y Z 1 0 Z High impedance XY C=0 In case of C=0, Y wire is open, not connected to any voltage !!!!!!!!! The high impedance is NOT a logic state and does NOT propagate 0 0 Y Y is not in high impedance status but the output of the second inverter takes the value deriving from an unconnected input (which in general is interpreted as a «dirty» high level ) 0 0 Y

53 A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 EN1*EN2* 74XX244 ENx* ( negative true ) xAixAi xYixYi 8 bit 3-state driver (2 groups of 4 bit)

54 54

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56 56 EN* BiBi DIR AiAi A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 EN*DIR 74XX bit bidirectional driver (transceiver)

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60 60 Tristate based Mux X0X0 C0C0 X1X1 C1C1 XnXn CnCn C i are decoded signals each one enabling one signal source. If the bus is made of multiple wires, C i enables all outputs of the same source

61 61 Eprom Memories An EPROM memory (Erasable Programmable Read Only Memory) is a device with n binary inputs and 8 binary outputs. For each input combination of the 2 n possible combinations (which can be considered therefore as minterms) it is possible to define and permanently store in the device eight binary values which correpond to the 8 outputs. Each of the 8 outputs has value 0 or 1 for each of the 2 n combinations of the inputs and therefore the EPROM allows to synthesize in canonical form 8 functions on n variables

62 62 Eprom memories DECODERDECODER “0” “1” 2 n -1 01mn01mn Y0Y0 Y1Y1 Y7Y7 where “n” is the minterm expressed as binary number (see Quine-McCluskey method) and F j (n) is the function value for that minterm (0 or 1) With an EPROM is therefore possible to synthesize in canonical form 8 (eight) combinatorial functions of n variables (j=0..7) Y j =“0”F j (0)+”1”F j (1)+”2”F j (2) +… “i”F j (i)… “2 n -1 “ F j (2 n -1) minterms 10

63 EPROM 63 2 n -1 m a b c d f W Z 2 n -2

64 64 EPROM memories Non volatile read-only memories Capacity: multiple of 2: 32K, 64K, 128K, 256K…… Identification number: 27512, (the indicate the number of Kbits) VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND VCC PGM* NC A14 A13 A8 A9 A11 OE* A10 CE* D7 D6 D5 D4 D3 EPROM K  8 AiAi CE* OE* DiDi T ce T acc T oe CE* OE* Di Cell M/bit i

65 65 Implement through an EPROM a 6 bit Gray/Binary and Binary/Gray converter

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