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**Combinatorial networks- II**

Digital Systems M

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**Added terms (idempotence)**

Adder Let’s see the truth table of a combinatorial network whose output values correspond to the numerical values of a 2-bit adder (Half Adder) ab Sum Carry Sum = a Å b = a exor b Carry=ab Sum Carry a b HA a Sum b Carry Let’s see the truth table of a combinatorial network whose output values correspond to the numerical values of a 3-bit adder (Full Adder). Canonical synthesis SP Sum = !a!bc+!ab!c+a!b!c+abc=!a(!bc+b!c)+a(!b!c+bc) =!a(b exor c)+a!(b exor c) = a exor (b exor c) Carry = !abc+a!bc+ab!c+abc = c(a exor b) + ab(c+!c) = c(a exor b) + ab abc Sum Carry HA b a Sum1 = a exor b Carry1=ab c Sum Carry2=c(a exor b) Carry Full Adder Sum2 =a exor (b exor c) R= !abc+a!bc+ab!c+abc = !abc+a!bc+ab!c+abc+abc+abc = ab(c+!c) + ac(b+!b) + bc(a+!a) = ab + ac + bc For the carry we have also Added terms (idempotence) (It could have been intuitively deduced since two 1’s are enough for generating a carry !!!)

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Adder To add a binary number of n bit, n-1 FA e 1 HA must be used HA a0 S0 NB: Normally the integrated circuits provide 4 bit FAs. With this network a new logical level (delay) is introduced for each couple of bit to be added. It must be remembered however that this is a combinatorial network which corresponds to a truth table which can be always synthesised as a two levels network (minimum delay). In the 4 bit integrated FAs the carry is always generated with a two level network in order to accelerate the operations of the next level FA. R b0 FA S1 a1 R b1 FA S2 a2 R b2

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**Analyse the circuit with Xilinx Schematic available in the examples**

FA 4-bit 74X283 Analyse the circuit with Xilinx Schematic available in the examples

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**Analyse the circuit with Xilinx Schematic available in the examples**

FA 8-bit Analyse the circuit with Xilinx Schematic available in the examples

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**Carry Look Ahead I Two level network (SP)**

With 4 bit full-adders a fast carry generator is implemented Two carries are defined: carry generate (G) and carry propagate (P) Considering the sum of two binary numbers with Ai and Bi the bits in the i-th position we define Gi the logical product Ai*Bi (1 only if both bit are 1) and Pi the logical sum Ai or Bi which if Ai =1 or Bi=1 produces arithmetically always a carry (Ci+1) if there is a carry (Ci - index i-1) It follows that Ci+1=Gi or PiCi (Gi =1 if Ai=Bi=1; PiCi =1 if A ior Bi=1 and Ci =1) therefore if Gi =1 then PiCi has no infuence. If Gi =0 and Pi=1 then PiCi =Ci and therefore wr have (here symbols + indicate always or) C1=G0+P0C0 C2=G1+P1C1 = G1 + P1(G0+P0C0)= G1 + G0P1 + C0P0P1 etc. and then substituting C4= G3+G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3 (carry of the 40h bit) Two level network (SP)

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Carry Look Ahead II A combinatorial 4-bit Carry Look Ahead generator produces CG3 e CP3 (FA 0-3 indexes) Carry Generate4 CG3= G3+G2P3+G1P2P3+G0P1P2P3 Carry Propagate4 CP3=P0P1P2P3 C4= G3+G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3 to generate C5 C5= G P4C4 = G4 + P4(G3+G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3) = G4 + P4CG3 + P4CP3C0 where CG3 and CP3 are generated by the four of the preceding FA. Normally CGi the Cpis and the Cis of several cascaded Fas are inserted in a combinatorial circuit which allows to speed up the operations. The are ohter methodologies for the Carry Look Ahead generation NB In the english texts very often CP is indicated as PG and CG as GG A4*B4 A4+B4 Two level expression(SP)

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**Full adder per adding n-bit**

4-bit Full Adder B0 B1 B2 B3 A0 A1 A2 A3 4-bit Full Adder B4 B5 B6 B7 A4 A5 A6 A7 C4 C7 C0

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Arithmetic Logic Unit Multifunction Circuit (including a 4-bit FA)

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74LS181

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**(Partial ) analysis of the previous circuit**

S S S S0 Mode=1 Mode=0 Cin=1 Cin=0 !A A Aplus1 1 !(A+B) A+B (A+B)plus1 !AB A+!B (A+!B)plus1 0000 Minus 1 zero !(AB) A plus A!B (A+A!B)+1 !B (A+B) plus A!B (A+B)plus A!B plus1 AxorB AminusBminus1 A minusB A!B A!Bminus1 !A+B AplusAB AplusABplus1 !(AxorB) AplusB AplusBplus1 B (A+!B)plusAB (A+!B)plusABplus1 AB ABminus1 1111 AplusA AplusAplus1 Aor!B (A+B)plusA (A+B)plusAplus1 AorB (A+!B)plusA (A+!B)plusAplus1 Aminus 1 (Partial ) analysis of the previous circuit Signals positive true (H=1, L=0)

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**74LS181 Carry_In Carry_Out Comparison 1 A£B A>B A<B A³B**

M=1 all internal carries are inhibited and the device implements the table logical functions M=0 internal carries are enabled and the device implements the table arithmetic functions Three carries: Ripple Carry (Carry_Out = C4), the «normal» arithmetic carry Two carry look-ahead carries : carry propagate (CP3) and carry generate (CG3) An output is available for AeqB (A equal B) open collector for wired AND. The equal is meaningful when S = 0110 with Mode=0 and Carry_in=1. AeqB is activated in fact if Output =1111. The performed operation A-B-1 has Output=1111 if A=B If S=0110 the Carry_Out can be used for the comparison of two absolute value numbers A and B Carry_In Carry_Out Comparison 1 A£B A>B A<B A³B

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S(3:0) Carry Propagate (CP3) B(3:0) Carry_Out (C4) Carry Generate(CG3) AeqB Output(3:0) A(3:0) Mode Carry_In

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See next slide Numerical subtraction Logical sum Somma numerica N.B. Note 1 indicates that the datum is left shifted one position (2 multiply)

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**Circuit electrical behaviour (check the schematic with Xilinx)**

Example S(3:0)=LHHH M=H Positive true Negative true Logic Logic AiBi Zi AiBi Zip AiBi Zin L L L L H L H L H H H L Zip =Ai!Bi Zin=Ai+!Ai!Bi=A+!Bi N.B. Here we consider ONLY the High and Low signal values. The logical intepretation is different if the logic is either positive or negative true

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Mux_8_to_1

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entity MUX_8_1 is Port ( INPUT : in STD_LOGIC_VECTOR (7 downto 0); X : in STD_LOGIC_VECTOR (2 downto 0); Enable : in STD_LOGIC; Z : out STD_LOGIC); end MUX_8_1; architecture Behavioral of MUX_8_1 is begin processo: process(X,Input) if Enable = '0' then Z <= '0'; else case X is when "111" => Z <= Input(7); when "110" => Z <= Input(6); when "101" => Z <= Input(5); when "100" => Z <= Input(4); when "011" => Z <= Input(3); when "010" => Z <= Input(2); when "001" => Z <= Input(1); when "000" => Z <= Input(0); when others => null; -- always necessary end case; end if; end process processo; end Behavioral;

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**DEMUX (or decoder) A Z1 C Z2**

Two ways demultiplexer: the input logical value is redirected to one of the two outputs (Z1 e Z2) according to value of the control signal (C). The truth table and the canonical function of a DEMUX with four outputs and two control signals C1 e C2 ? This circuit is called also DECODER because if in n-way demux the input a is at logical value 1, only one output is at logical value 1, that corresponding to one of the 2n control input binary configurations (only one in this figure – c). The circuit therefore “decodes” the input binary value (that is corresponds to the control signals binary value) A C Z1 Z2

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**Example Y2N = !((!AB!C)G1!G2AN!G2BN)**

Decoder 3:8. Control inputs are A,B and C the output YiN [corresponding to the binary value (i) of ABC (C=> 22, B=>21, A=>20)] is 0 (Low) only if enable inputs G1=H and G2AN=G2BN=L otherwise all outputs are H. Example Y2N = !((!AB!C)G1!G2AN!G2BN)

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**Analyze the network 74686 comparator**

This 8 bit comparator is a combinatorial network whose inputs are two binary 8 bit numbers (absolute value). It checks whether they are identical and/or whether one is greater (or lower) than the other. It has two negative true inputs G1N e G2N which enable the two sections of the network. G1N enables to check whether the two numbers are identical while G2N enables the greater/lower section. The first section consists of XNORs of all bits with the same index (i.e. P0 and Q0). A XNOR is 1 if the bit are identical. The 8 outputs are NANDed with G1N: its output PEQN is 0, negative true , if all XNOR bis are 1. The second section is made of 8 ANDs with increasing number of inputs: they compare the bit starting from the most significant…. Analyze the network

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See the examples Outputs negative true

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**process (P,Q,G1IN, G2IN) --- sensitivity list**

variable I : Integer; begin if G1IN='0' then if P=Q then PEQQN <= '0'; else PEQQN <= '1'; end if; else PEQQN <= '1'; G1IN=1 if G2IN='0' then if P/=Q then if P>Q then PGRQN <= '0'; PLTQN <= '1'; elsif P<Q then PGRQN <= '1'; PLTQN <= '0'; else -- P=Q else G2IN='1' end process;

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Minimum cost networks The“cost” (which in this context means “complexity”) has no unique meaning and depends on many factors In our context the minimum cost refers to the minimum number of devices needed to implement a two levels combinatorial logical function. Notice that the minimum cost implementations can be more than one Minimum expression: an expression which corresponds to the minimum cost implementation Normal expression: an SP (or PS) expression. Two levels. The canonical expressions are normal but they are not the only normal expressions Non-redundant expression: a normal expression SP (or PS) whose terms are all necessary. Examples Example 1 F= ab+bc+ad: no product can be removed without modifying the truth table . Example 2 F=b!c+ac. Expression b!c+ab+ac (which corresponds to the same truth table) wouldn’t be non-redundant since term ab could be removed without altering the truth table A minimum cost network in our case is a normal non-redundant expression In the following slides we use only SP for sake of simplicity (being the extension to the PS straightforward– duality)

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Minimum cost networks Implicant: a product term of n or less input variables which is 1 only for input combinations where the function is not 0 Example F= abc + ac + cd + ad (all products are implicant) Prime implicant: an implicant which is not an implicant any more if a letter is removed Esempio F= ac + cd (both products are prime implicants) Essential prime implicant: an implicant which is the only one having value 1 for some input configurations where the function must be 1 (that is there are no other prime implicants which cover one ore more «1s» of the function) ExampleF= abc + ac + cd (abc is not essential) It follows that a minimum cost network is an non-redundant sum of essential prime implicants (only those strictly necessary)

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**Karnaugh maps 00 01 11 10 ab cd 1 00 01 11 10 1 a bc 1 a b 00 01 11 10**

Bi-dimensional representation of the truth table of a function of 2,3,4,5 and 6 variables, whose values are indicated on the border of the maps so that two adjacent input configurations (differing for one single bit) are topologically adjacent. Obviously the number of the map squares is a power of two (all possible input combinations) 00 01 11 10 ab cd 1 00 01 11 10 1 a bc 1 a b 00 01 11 10 ab cd 1 00 01 11 10 ab cd 1 e=0 e=1

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Karnaugh maps The Karnaugh maps can be easily used to underline the adjacences of the input configurations where the function is «1» allowing to graphically implement the algebra theorems (i.e. ab + a!b = a) The input adjacence in the Karnaugh maps must be interpreted in spherical sense. In the following example the square a=0, b=0, c=0 and d=1 (red) is adjacent to square a=1, b=0, c=0, d=1 (green) in addition to 0001 and The grahical representation allows to easily detect the input confgurations which differ for a single bit adjacent 00 01 11 10 ab cd 1 adjacent adjacent

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**Karnaugh maps bc 00 01 11 10 1 a 1 F= !a!b + !b!c + !a!c + abc**

Let’s consider the truth table of a three inputs function abc F = !a!b!c+!a!bc+!ab!c+a!b!c+abc = !a!b!c+!a!b!c+!a!b!c+!a!bc+!ab!c+a!b!c+abc = = !a!b+!b!c+!a!c+abc (much simpler) Idempotence What was exploited ? The adiacences of the product terms of the canonical expression. But the same can be found it in a Karnaugh map!!! And the same operations executed using the algebra theorems can be derived by analyzing the adjacents groups. The greatest rectangular groups of «ones» must be found (a rectangular group is a group of 2n squares each one having n adjacent squares) which cannot be enlarged without including zeroes. The product terms (implicants) of minimum complexity (prime implicants) can be obtained observing the input variables which do not change withing the group (taken as true if present with value 1 and viceversa) . Spherical adjacences!! bc 00 01 11 10 1 F= !a!b !a!b!c+!a!bc + !b!c !a!b!c+a!b!c + !a!c !a!b!c+!ab!c + abc a 1 Mintermin alone ! Coverture: each “one” of the function must be covered at least by one group (but also by more than one – idempotence)

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**Here we have no adjacent minterms => canonical synthesis !!!**

Karnaugh maps !bc + cd 00 01 11 10 1 a bc ab !b!d + 00 01 11 10 The implicant !a!b (dashed) would be prime but it is not essential 00 !a!c + 1 !ad + 1 1 1 01 b!cd + 1 1 1 11 1 1 ac!d 10 1 F1= !b+ac+!a!c F2= 00 01 11 10 ab cd 1 Here we have no adjacent minterms => canonical synthesis !!! All product terms are prime implicants and are essential too since they cover «ones» not covered by other prime implicants F3= !a!b!cd+!a!bc!d+!ab!c!d+!abcd+ab!cd+abc!d+a!b!c!d+a!bcd

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**Karnaugh maps 00 01 11 10 ab cd 1 00 01 11 10 ab cd 1 !b!d + !a!c!e +**

00 01 11 10 ab cd 1 !b!d + !a!c!e + bcde ac!d + ade + a!bc + e=0 e=1 F= The two 4 bits maps differ for the 5-th variable (e) and can be interpreted as two spherical surfaces having the same center

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**PS Synthesis 00 01 11 10 ab cd 1 00 01 11 10 ab cd 1 e=0 e=1**

In this case the prime rectangular groups of «zeros» must be found (prime implicated). The sum terms of minimum complexity can be derived by the squares variables which do not change, taken as negate if 1 and viceversa (a+b+!c+!d) 00 01 11 10 ab cd 1 00 01 11 10 ab cd 1 (a+c+!d+!e) (a+!b+d+!e) (a+!b+!c+e) (!a+!b+c+d) (!a+c+!d+e) (!a+!b+!d+e) e=0 e=1 F=

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**Karnaugh maps cd cd ab ab 00 01 11 10 00 01 11 10 00 00 1 1 1 1 1 1 01**

!b!d + ab !b!d + 00 01 11 10 00 01 11 10 00 00 1 1 !a!bc 1 1 !acd 1 1 01 01 bd + 1 1 bd + 1 1 11 11 1 1 1 1 10 1 10 1 F= F= The two synthesized functions are equivalent, of the same complexity and both consisting of prime implicants. This can occur very often General rule: in the maps detect first the ones (zeros) which are covered by only one implicant (implicated) and use the corresponding rectangular group (essential). The the other ones (zeros) must be covered. There are however cases (as that of the figure) where there are no ones (zeros) covered by a single prime essential implicant (implicated)

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**The table which has been actually synthesized**

Karnaugh maps Combinatorial neworks not fully specified: for some input combinations the outputs are not defined (normally this is the case of impossible input combinations:i.e. 7 segments where the only input values are 0 to 9). In this case the function in the map can be «don’t care» (normally indicated by x or - ) and the value can be used as “one” and “zero” in order to obtain implicants (implicated) of minimum complexity. The don’t cares can be in turn interpreted as zero or one according to the needs 00 01 11 10 ab cd 1 x 00 01 11 10 ab cd 1 X => 0 X => 1 F=!b + a+ !c!d The table which has been actually synthesized

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Seven segments 00 01 11 10 ab cd 1 fe = A + !BC

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**All other input configurations are don’t cares**

Output BCD | Binary | dcba | edcba | | | | | | | | | | All other input configurations are don’t cares Design with the Karnaugh maps - starting from the truth table - a packed BCD to binary converter when the max value of the packed BCD code is (19) and the even numbers must not be converted (packed BCD => Binary for odd numbers). What are the don’t cares?

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**Packed BCD to binary for odd numbers (Let’s synthesize the b function)**

BCD | Binario | dcba | edcba | | | | | | | | | | 00 01 11 10 dc ba - 1 e=0 e=1 !eb e!b + b= = e Å b Synthesize the other functions Synthesize with Xilinx (abcde and abcde as busses – Binary(4:0) and BCD(4.0))

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**Can we derive the Karnaugh map from the SP (PS) expressions ?**

Z1= x1x3 + x1x4 + x2x3 Z2 = x1x2 + x2x4 + !x3x4 00 01 11 10 X1 X2 X3 x4 1 1

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**ba 00 01 11 10 dc 6 variables Karnaugh maps 1 - ez=00 ez=01 ez=10**

- ez=00 ez=01 ez=10 ez=11 F = a!b!cz + !a!b!c!z + (!b+c+z) (!b+!a+c+!z) (b+!a+z) !a!ez (b+!c) bc + (a+!e+!z) F = And for more variables?

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**Quine – McCluskey method (I)**

Two steps procedure Prime implicants identification Minimum set covering the function detection Table (algorithmic) method No limit for the variables number Software synthesizable Easy «don’t» care handling Grouped minterms Each group includes minterms with the same number of variables either true or complemented The minterms are listed numerically within the groups

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**(don’t care in the same position**

Metodo di Quine – McCluskey (II) (In the following example the minterms are represented with the numerical value corresponding to each input variables configuration) Example => f (A,B,C,D)= Sm(4,5,6,8,9,10,13) with don’t care Si(0,7,15) (S is the logic sum - 4 => 0100, 13 => 1101 etc.) -000 (0 & 8) b 010- (4 & 5) c 01-0 (4 & 6) d 100- (8 & 9) e 10-0 (8 & 10) f 01-1 (5 & 7) g -101 (5 & 13) h 011- (6 & 7) i 1-01 (9 & 13) l -111 (7 & 15) m 11-1 (13 & 15) n ^ Combination (don’t care in the same position ABCD Minterms grouping in the first column (in red the don’t cares) according to the number of «ones». Successive groups differ for a single «one» 0000 (0) 0100 (4) 1000 (8) 0101 (5) 0110 (6) 1001 (9) 1010 (10) 0111 (7) 1101 (13) 1111 (15) 0 «ones» 1 «one» and 3 «zeros» 2 «ones» and 2 «zeros» (4&5&6&7) The the terms of column II are «combined» again in the following column (III) (if possible) provided they have the don’t care in the same position and differ b a single «one» (they can produce – by couples – the same result). The don’t care are not recombined otherwise we would go back to square one.(i.e. by recombining a and b we wouldo btain 0000 !!) The aim of the combinations is to obtain in steps increasingly simpler implicants until prime implicants are produced 01-- (c&i,d&g) a * ^ Comparison in the column I between the elements with N «ones» and those with N+1 «ones» and their combination in order to obtain less complex terms (column II). The combination corresponds to the use of the property a!b + ab= a(!b + b)=a. Synbol ^ if combined, * if not. 0-00 (0 & 4) a ^ Al groups with * are prime implicants (which cannot be recombined) * -1-1 (g&n,h&m) b (5&7&13&15) The process is repeated until no more combinations are possible. I column II columns III column N.B.g can be combined with two different terms

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**Metodo di Quine – McCluskey (III) method**

Coverture table (minterms columns – prime implicants rows) Obviously ONLY the real minterms must be covered, NOT the don’t care a 0,4(0-00) b 0,8(-000) e 8,9(100-) f 8,10(10-0) l 9,13(1-01) a 4,5,6,7(01--) b 5,7,13,15(-1-1) 4 X 5 6 8 9 10 13 f (A,B,C,D)= Sm(4,5,6,8,9,10,13) On the left all found prime implicants and in the columns the function minterms to be synthesized: X indicate which prime implicants covers which minterms of the functon NB If a column has a single X the corresponding prime implicant is obviously essential

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**Then we search for the minimum set**

Quine – McCluskey (IV) method The already covered columns are removed Columns 4,5 and 8 are automatically covered by essential prime implicants (see previous slide) 0,4(0-00) 0,8(-000) 8,9(100-) 8,10(10-0) 9,13(1-01) 4,5,6,7(01--) 5,7,13,15(-1-1) 4 X 5 8 9 13 Essential 0,4(0-00) 0,8(\000) 8,9(100-) 8,10(10-0) 9,13(1-01) 4,5,6,7(01--) 5,7,13,15(-1-1) 9 X 13 Then we search for the minimum set covering 9 and 13 f = A!B!D + A!CD + !AB f l a

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Integrated BCD adder

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**NAND (NOR) circuits a z b c 1 z a b c**

Although the elementary logic operators (AND, OR, NOT) are available as IC or FPGA etc. it can be useful sometimes to use only one type of operator: NAND or NOR X Z X Z 1 X X Z Z y y 1 1 X Y X Z Z y ( De Morgan)!! Any two levels SP (PS) circuit can be implemented using only NANDs (NORs). Example: SP two-ways multiplexer. a z b c 1 z a b c z = ![(!(a!c) !(bc)] = a!c + bc (De Morgan)

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**? 3-state drivers I U I U OE=0 I U OE OE=1 OE I U I 1 OE 1 1 1 Z U 1 Z**

OE 1 1 1 ? Z U 1 Z Voltage ?

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U value ? 1 U=? OE=0 What must be granted in this network ? When U has a meaningful logical value ? I1 OE1 U=? 1 I2 OE2

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Common bus circuits Very often (and in particular in microprocessors based systems) many devices must drive– in different times - the same wire (in case of many devices with multiple wires the name used is bus) and multiplexers (for instance with many inputs – say 30 or 40) can’t be practical because of the circuit complexity. In this case devices with tri-state outputs are used that is devices whose outputs can be enabled (and in this case the output follows the logic of the circuit) or disabled (and in this case the circuit output is electrically disconnected from output connected to output pin). Typically tri-state circuits are buffer C=1 X C Y Z Z X Y C=0 High impedance X Y In case of C=0, Y wire is open, not connected to any voltage !!!!!!!!! The high impedance is NOT a logic state and does NOT propagate Y is not in high impedance status but the output of the second inverter takes the value deriving from an unconnected input (which in general is interpreted as a «dirty» high level ) Y Y

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**8 bit 3-state driver (2 groups of 4 bit)**

244 74XX244 8 bit 3-state driver (2 groups of 4 bit) 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2A1 2Y1 ENx* (negative true) xAi xYi 2A2 2Y2 2A3 2Y3 2A4 2Y4 EN1* EN2*

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**8 bit bidirectional driver**

245 74XX245 8 bit bidirectional driver (transceiver) A1 B1 A2 B2 A3 B3 A4 B4 EN* Bi DIR Ai A5 B5 A6 B6 A7 B7 A8 B8 EN* DIR

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Tristate based Mux C0 C1 Cn X0 X1 Xn Ci are decoded signals each one enabling one signal source. If the bus is made of multiple wires, Ci enables all outputs of the same source

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Eprom Memories An EPROM memory (Erasable Programmable Read Only Memory) is a device with n binary inputs and 8 binary outputs. For each input combination of the 2n possible combinations (which can be considered therefore as minterms) it is possible to define and permanently store in the device eight binary values which correpond to the 8 outputs. Each of the 8 outputs has value 0 or 1 for each of the 2n combinations of the inputs and therefore the EPROM allows to synthesize in canonical form 8 functions on n variables

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**Yj =“0”Fj (0)+”1”Fj(1)+”2”Fj (2) +… “i”Fj (i)… “2n-1“Fj (2n-1)**

Eprom memories D E C O R “0” “1” 2 n-1 1 m n 1 1 1 1 Y0 Y1 Y7 With an EPROM is therefore possible to synthesize in canonical form 8 (eight) combinatorial functions of n variables (j=0..7) Yj =“0”Fj (0)+”1”Fj(1)+”2”Fj (2) +… “i”Fj (i)… “2n-1“Fj (2n-1) minterms where “n” is the minterm expressed as binary number (see Quine-McCluskey method) and Fj (n) is the function value for that minterm (0 or 1)

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EPROM 2n-1 Z 2n-2 W m f 3 d 2 c 1 b a

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**EPROM memories EPROM Non volatile read-only memories**

Capacity: multiple of 2: 32K, 64K, 128K, 256K…… Identification number: 27512, (the indicate the number of Kbits) EPROM VCC 1 VPP 32 PGM* 2 A16 31 NC 3 A15 30 4 A12 A14 29 A13 5 A7 28 A6 A8 6 27 Ai CE* OE* Di Tce Tacc Toe A9 7 A5 26 A4 A11 8 25 A3 OE* 9 24 A10 10 A2 23 CE* 11 A1 22 D7 12 A0 21 13 D0 D6 20 14 D1 D5 19 15 D2 D4 18 CE* OE* Di Cell M/bit i GND D3 16 17 128K 8

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**Implement through an EPROM a 6 bit Gray/Binary and Binary/Gray converter**

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