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Synchronous logical networks I Digital Systems M 1.

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1 Synchronous logical networks I Digital Systems M 1

2 Asynchronous network problems The behaviour depends on the feedback delays with all related possible malfunctionings (different delays) The behaviour depends on the input hazards (which in any case can’t be exactly concurrent) and prevents the detection of repeated input sequences (i.e. the sequence is the same as ) SOLUTION An «artificial» input concurrency detection and forced and controlled feedback delays 2

3 Synchronism signal If the pulse is short enough and less than the combinatorial network delay (that is the combinatorial network minimum delay) the new s/r 0..k produced by the combinatorial network do not reach the blocking AND before the AND outputs are zeroed making the SR FF stable (the SR FF with both inputs zero doesn’t change status). Only during the following  pulse the new FF outputs values are transmitted to the combinatorial network with no feedabck effets again. Forced feedback alignment. It must be noticed that this way the combinatorial networks inputs too are forcibly «aligned» as far as the status is concerned. No «race» problems (but for the output in the Mealy case) The outputs are almost perfectly aligned (that is they are synchronous) if the sequential machine is Moore type (the outputs depend only from the state variables) and the FFs switch concurrently (which is very likely) Combinatorial network X 0..n Z 0..m s/r 0..k Y 0..k  FF SR 0..k Synchronism signal 3

4 The synchronism signal is always referred to as clock Normally the clock signal is a regular repetitive square (or rectangular) wave of T period (but not necessarily) A SR FF with a clock signal is referred to as synchronous SR (which in the real systems is never used) What problems arise with the clock signal of the figure ? The pulse duration should be extremely narrow since a combinatorial network can consist even of a single wire and in this case the delay is only the wire propagation delay! In practice it cannot be implemented Clock T 4

5 The synchronous FFs There are several synchronous FFs but nowadays only the DFF is used whose behaviour was previously analysed as an asynchronous network but which here is used as a synchronous FF (in its 74xx74 version) DQ !Q CK D The DFF has this name name because D stands for Delay. In fact the output Q follows the input D with a T period delay (if the input signal is synchronous – that is is generated concurrently with the clock – respecting however setup and hold times – for instance by a network controlled by other DFFs using the same clock) or in presence of the first clock rising edge. The triangle on the clock input (CK) indicates that the FF is edge triggered that is it switches on the positive edge of the clock DQ !Q CK D PR CL The signals !CL(ear) and !PR(eset) act asynchronously that is immediately, independently from the clock 5

6 6 The DFF switches ONLY during the transition of CK fro 0 o 1. This corresponds to the very short pulse  seen before. If the transition is fast enough the combinatorial network cannot react before the CK transition is finished Combinatorial network X 0..n Z 0..m y 0..k Y 0..k Clock D 0..k Q 0..k FFD 0..k CK D 0..k Q 0..k CK The clock of the DFF must switch from 0 to 1 only when the combinatorial network is stable (quiet). The transfer of the DFF input to its outputs (transition time) must fast enough to grant the the new D inputs generated by the combinatorial network because of the new values of Y i arrive after the end of the CK transition. Then there is a solid time period for the combinatorial network to reach a new stable state. The period of the CK must be in any case greater than the time required by the combinatorial network to reach its stable state.

7 VHDL Let’s consider the DFF DFF D CK Q Q* D CK Q QN CK D Q 7

8 entity DFF_1 is Port ( D : in std_logic ; CK : in std_logic ; Q : out std_logic; QN : out std_logic ); end DFF_1; architecture Behavioral of DFF_1 is begin process_FF: process(CK,D) begin if (CK'event) and (CK='1') then Q <= D; QN <= not(D); -- Careful! QN <= not(Q) must not be used !!!!!! -- otherwise QN switch would not be concurrent with Q end if; end process process_FF; end Behavioral; “if (CK'event) and (CK='1')” means that the switch occurs in presence of an edge of CK and the final value is 1 (CK=1). Rising edge ! 8

9 Behavioural simulation 9

10 Asynchronous commands A_SET and A_RES have precedence over the other inputs The two signals must not be activated concurrently (nonsense) In our case we want to model the DFF so as A_RES has precedence over A_SET DFF D CK Q Q* D CK Q QN A_SET A_RES A_SET A_RES DFF with Set and Reset (VHDL) 10

11 entity DFF_asynchronous_commands is Port ( CK : in std_logic; D : in std_logic; A_SET : in std_logic; A_RES : in std_logic; Q : out std_logic; QN : out std_logic); end DFF_asynchronous_commands; architecture Behavioral of DFF_asynchronous_commands is begin Process_FF: process(CK, A_SET, A_RES, D) begin -- positive logice if (A_RES='1') then Q <='0'; QN <='1'; elsif (A_SET = '1') then -- only if A_RES inactive Q <='1'; QN <='0'; elsif (CK='1') and (CK'event) then Q <= D; QN <= not(D); end if; end process process_FF; end Behavioral; 11

12 Asynchronous Reset (A_RES=1, A_SET=0) Both asynchronous commands active (A_RES=1, A_SET=1): asynchronous reset has higher priority (see VHDL) Asynchronous Set (A_RES=0, A_SET=1) Positive logic ! 12

13 Synchronous sequential networks The synthesis is performed as in the case of an asynchronous network with direct feedback but inputs remaining constant are considered by the network as different since they are considered in different periods and therefore in presence of possible different states of the FFs What matters in this case is the clock positive edge: the time distance between two consecutive rising edges (respecting setup e hold times) DOESN’T count Clock period (frequency) must be greater (smaller) than the max combinatorial network delay. The combinatorial network must be stable after a clock positive edge before a new clock positive edge can occur The clock rising edge differentiates input and output (it separates them from the time point of view) Combinatorial network X 0..n Z 0..m y 0..k Y 0..k Clock D 0..k Q 0..k FFD 0..k CK D 0..k Q 0..k CK See the architecture of the asynchronous networks with SR FF feedback where S=!R 13

14 Synchronous Sequential Networks (SSN ) k feedback DFFs All with the same clock of T period In this case: Moore or Mealy ? S O S*S* I tt+ T t+2· T t- T CK k (k) DFF SS*S* CK RC I O 14

15 The DFF as fundamental SSN element If a periodic signal is sent to CK (clock) input, the DFF (D = Delay) delays the output signal Q a time equal to the period T if the change of D is logically (but not physically) concurrent with CK (but always respecting setup and hold times) Q n+1 = D n D CK Q TTTT DFF D CK Q Q* D CK Q Q* NB: The concept of concurrency could seem to be in contrast with the need of respecting setup and hold times. As a matter of fact the inputs of a synchronous network are in the great majority of cases the outputs of other networks which have the same clock and therefore with their delays which grant automatically the respect of setup and hold. Therefore the variations of the inputs are always a little later than the clock edge. See later the behaviour of the shift registers NB:since here the time is discrete, n and n+1 (periods) are used instead of T e T+  15

16 Synchronous Sequential Networks The states changes occur only with the rising edges of the clock and therefore with T period (if the clock is periodical) The network changes its outputs every T and therefore if a very responsive network is required, as far as the outputs are concerned, the Mealy model must be adopted The states evolution is independent from the combinatiorial network (provided the distance between the rising edges of the clock is greater that the maximum delay of the combinatorial network)! Thereofre no critical races problem Within the same system (i.e. a processor) more SSNs are present, not necessarily with the same clock SSNs can be more easily designed than the ASNs 16

17 Clock gating and clock glitch In the synchronous sequential networks unwanted clock glitches mus be avoided which could induce unwanted DFF switches. For instance because of the different delays of the n signals I[n-1..0] of a decoding network, hazards (glitches) can occur provoking the “clock gating“ effect CK P CK_G Clock glitches → possible unwanted DFF switch X CK Q Q* FFD D CK Q Q* CK_G Decoding network I[n-1..0] P t NO !! Obviously it depends on the spurious glich duration: if too narrow the FF could be not triggered (the clock pulse must always have a minimum width which depends on the FF technology: when too narrow either is not sensed by the FF or can cause metastability). The clock gating is not prohibited but is a risk to be avoided when possible. 17

18 For transitions which must or must not take place depending on a decoding network the solution of the figure must be adopted. If the decoding output is 1 Q n+1 = D n otherwise Q n+1 = Q n X CK Q Q* FFD D CK Q Q* I[n-1..0]P t 0 1 SEL 0 1 Decoding network 18 Clock gating and clock glitch

19 The clock gating, in addition to cause potential glitches produces also a “clock-skew” (disalignmento). Let’s consider two SSN, DFF1 and DFF2 Clock gating e clock-skew CK CK_G  AND The two networks clocks are out of phase beacuse of the inserted AND delay time  AND. This phenomenon - clock-skew - is potentially very dangerous since DFF-2 could sample the new (and not the previous) value of DFF-1 albeit the clock should be the same NB: The “clock-skew” is not only caused by the clock gating but also (for example) by different electrical paths I1 CK B B* CK_G P I2 CK A A*  AND DFF-1 D CK Q Q* DFF-2 D CK Q Q* 19

20 Input synchronization Up to now we have implicitly assumed that the inputs of a synchronous network switch synchronously with the clock This is true if the inputs come from a Moore type network where the outputs depend only from the state, which switches synchronously with the clock. X 0..n Combinatorial network Z 0..m y 0..k Y 0..k Clock D 0..k Q 0..k DFF 0..k CK D 0..k Q 0..k CK Combinatorial network AS a matter of fact, the real situation is normally different. Let’s consider for instance a push button as the input of a synchronous network. Its status change can occur any time. In the network of the figure (Moore) the outputs are in any case synchronous with the clock: if the input X 0..n change asynchronously from the clock their changes are detected by the network feedback FFs only at the clock positive edge and therefore the network behaviour is the same it would occur if the inputs were synchronous 20

21 Input synchronisation The situation is different however with a Mealy network Combinatorial network X 0..n Z 0..m y 0..k Y 0..k Clock D 0..k Q 0..k FFD 0..k CK D 0..k Q 0..k CK In this case an asynchronous input change triggers, in general, an asynchronous output change 21

22 Example: the safe (with a two keys keyboard) opens only if the inputs temporal sequence is Each sequence violation restarts the system. NB Since the inputs are sampled the sequence is possible and meaningful … Safe … synchronous…. NB: It can be assumed that the inputs change concurrently with the state variables but this is not necessary. If the network is Moore type even if the inputs change in the middle of a clock period the behaviour from the state point of view (and therefore from the outputs point of view) is in any case the same (each input variation is sampled only at the period end)) E, F,0 01 G, For each state ALL input configurations !! C,0A,0B,0D,0 The states are not necessarily stable for the input configurations which led to them 00 22

23 B FA G A BCAG B BDAG C BFAE D BFAG E BFAA-G F BFAG G X1X1 X2X2 C,0 E, A,0 11 D,0 10 F,0 01 G, B,0 00 Synchronous Safe 01 NB: in this esample there are not don’t cares for the states. Instead of compatibile states therefore there are equivalent states. In general when two states for the same inputs have the same outputs and lead to the same states or equivalent states they are called indistinguishable. Obviously the system description could include some impossible inputs configurations: in this case we go back to the compatibility concept. The same applies when one ore more outputs are don’t care (a very unlikley situation since all states last one period) 00 23

24 Synchronous Safe Equivalence (not compatibility) classes [AFG]=>   B]=>  [C]=>  [D]=>  [E]=>  B FA G A BCAG B BDAG C BFAE D BFAG E BFAA-G F BFAG G X1X1 X2X2 B C D E F G ABCDEF CF FDCD CF GE CF GE DF GE ---CFDFGE ---C FDFGE--             X1X1 X2X NB: In case of fully specified tables the maximal equivalence classes have NO states in common (the transitive property i valid). Since they are disjoint all of them must be used and therefore there is NO closure problem Obviously 5 states: 4 belongs to the correct sequence and one is out of it 24

25             X1X1 X2X Synchronous Safe            X1X1 X2X2       Y1Y1 Y2Y2 Y3Y3      D 1 = X 1 !X 2 Y 2 !Y 3 D 2 =!X 1 X 2 Y 3 D 3 =!X 1 !X 2 +!X 1 !Y 2 Y 3 Z =Y 1 Using DFFs the D inputs synthesis is achieved by synthesizing Y i (Y n+1 =D n ) No race problems: free states coding 25 NB: The synthesis is made on the assumption that the opening input configurations follow synchronously with a distance of a period. Should the safe open ONLY when the sequence is correct no matter how many times a single correct input is repeated an auto-ring must be provided in the corresponding state

26 Xilinx schematic 26

27 Behavioural Simulation 27 Post-route Simulation

28 If Mealy ? B FA G A BCAG B BDAG C BFAE D BFAG E BFAA-G F BFAG G X1X1 X2X2 B, F,0A,0 G,0 A B,0C,0A,0G,0 B B,0D,0A,0G,0 C B,0F,0A,0E,1 D B,0F,0A,0G,0 E B,0F,0A,0A-G,0 F B,0F,0A,0G,0 G X1X1 X2X2 Synthesize and simulate with Xilinx 28 In this case the safe opens as soon as the input becomes 10 in state D. Obviously this implementations opens the safe one period in advance compared with the Moore implementation

29 Monoimpulsor A D1Q1 !Q1 CK DFF D2Q2 !Q2 CK DFF Z D Clock D Z Q1 !Q2 Here the asynchronous input D is synchronized by the DFFs.The output Z is synchronous with the clock The aim is to generate a synchronous output pulse lasting one period when a «1» of an asynchronous input is detected. A further output pulse can be generated only when a «0» input is sampled and then a «1» is sampled again and so on 29 Complement (time diagram starts after D=0 for several periods)

30 D1 Q1 !Q1 CK DFF D2 Q2 !Q2 CK DFF Z D Clock Monoimpulsor A A,0B,1C, A A A - B C C - D Q2Q2 Q1Q1 B 01 C - Z A D Q2Q2 Q1Q1 D C 11 B 10 Z A B C D A Q 1 =D Q 2 = Q 1 Z=Q 1 !Q 2 Moore necessarily if we want the output synchronous with the clock! Q 1 =D Q 2 = DQ 1 Z=Q 1 !Q 2 A B C D D Q2Q2 Q1Q Z Same behaviour! 30 Synchronous network: no races!! But using D … (A and D indistinguishable)

31 D1Q1 !Q1 CK DFF D2Q2 !Q2 CK DFF Z D Clock Monoimpulsor B Clock D Z Q1 !Q2 A Mealy network: with an asynchronous input we have an asynchronous output Z lasts a period plus the inizial phase (D>period) Here Z duration depends on the input only (D { "@context": "", "@type": "ImageObject", "contentUrl": "", "name": "D1Q1 !Q1 CK DFF D2Q2 !Q2 CK DFF Z D Clock Monoimpulsor B Clock D Z Q1 !Q2 A Mealy network: with an asynchronous input we have an asynchronous output Z lasts a period plus the inizial phase (D>period) Here Z duration depends on the input only (Dperiod) Here Z duration depends on the input only (D

32 D!Q Q CK DFF Z D Clock Monoimpulsor C Clock D Z Q Mealy network: with an asynchronous input we have an asynchronous output Z =1 if D=1 and is sampled 32 After the DFF has sampled a 1, if the input oscillates then the output oscillates until the DFF samples a 0 (time diagram start after D=0 for several periods)

33 Monoimpulsors A, B e C  The exact state diagram corresponding to the real behaviour of monoimpulsors B and C CANNOT be drawn because the two networks (Mealy type) are NOT synchronous. A synchronous state diagram implies that the inputs too are synchronous, which is not the case with B and C  This is not the case of the monoimpulsor A either, since although the input is asynchronous the output (Moore type) depends on the states only. The network behaviour makes internally synchronous the inputs which are physically asynchronous  A real state diagram of monoimpulsors B and C can be designed only using an asynchronous analysis, that is “opening” the DFF. Obviously it is always possible to design the two networks without the DFFs starting from an asynchronous traditional states diagram. 33

34 Q=1 Q=0 34 Monoimpulsor C (asynchronous description): design a network with two inputs C and D and an output Z. The output Z is zero if D=0 independently from C. A transition of C from 0 to 1 samples always D and Z=1 if both the sampled value and D are 1 10,0 B 01,1 F 01,0 D 11,- 11,0 C 10,- 11,1 E 00,0 A CD,ZCD,Z 11,0 10,0 11,1 00,0 01,0 00,0 11,1 00,0 G 01,1 10,0 H 00,0 01,0

35 A, D, B,0 A A, C,0B,0 B ---- D,0C,0 B,0 C A,0D,0E,----- D F,1E,1H,1 E G,1F,1E,1---- F G,1 F, B,- G C D G,1----E,1H,1 H [ABC] [AD] [EFH] [FG] [ABC] [D] [EFH] [G]           C D B C D E F G ABCDEF -- CE -- H G CE BH

36 36          C D This is the state table of the DFF (see asynchronous networks) with a different output Y 1 = y 2 C + y 1 !C Y 2 = y 2 C + D!C Z = y 1 D    C 00        D y2y2 y1y1     Post route simulation. Why the behavioural doesn’t function properly?

37 Input 37 Xilinx Monoimpulsors Input: X ( respecting setup and hold times) Multiple outputs: ZA monoimpulsor 'A' ZB monoimpulsor 'B' ZC monoimpulsor 'C‘

38 Behavioural simulation Post-route simulation 38 Arrow => sampling delay

39 39 A retriggerable one-shot (trigger => activation signal) is a circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X. When another positive edge of X occurs during the pulse Z, the circuit extends the pulse Z of another T time. Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to the clock (of frequency f=1/T) produces in a retriggerable way a pulse of 3 clock periods, synchronous with the clock. 3 Normal one-shot Retriggerable one-shot

40 X G,1 F,1 1 A,0 1 D,1C,1B,1 1 1 E,0 The outputs becomes 1 with the first clock positive edge sampling X=1. From each state the number of branches is equal to the number of input configurations !!! 40 NB Synchronous output With input=0 the three periods output is in any case produced, which is extended in case an input=1 is sampled again With X=1 at least a three periods output

41 0 1 X AA FCB AED GDC B AE G BF ABG E B D C E F A B C D E F G FG CD BE AF CE FG BC AG DE DB AG DB AG BE AG AF CB All states are distinguishable 41

42 0 1 X AA FCB AED GDC B AE G BF ABG E 0 1 X (Y 2 Y1Y1 Y0)nY0)n X Y2Y2 Y1Y1 Y0Y (D 2 D 1 D 0 ) n D 2 = !X!Y 1 Y 0 + XY 2 !Y 1 !Y 0 + XY 1 Y 0 + !X!Y 2 Y 1 !Y 0 D 1 = !X!Y 2 Y 1 !Y 0 + !XY 2 Y 0 + X!Y 2 !Y 1 Y 0 + X!Y 2 Y 1 !Y 0 D 0 = X!Y 2 !Y 1 Y 0 + XY 2 Y 0 + XY 1 !Y 0 + X!Y 2 !Y 0 Y2Y2 Y0Y Y1Y Z = Y0 + Y1 The circuit does’t fully respect the characteristics of a real one- shot since the output pulse doesn’t start immediately upon a an input positive edge but only when the clock samples the input (Y 2 Y 1 Y 0 ) n+1 42

43 1,1 0,1 0,0 X,Z 1,1 1,0 0,1 1,1 G F A DCB 1,0 E 0,0 Mealy solution 43

44 0 1 X A,0A F,1C,1B A,0E,0D G,1D,1C B,1 A,0E G,1 B,1F A,0B,1G E,0 B D C E F A B C D E F G FG CD FG BC DB Maximal classes A,B,C,(DE),F,G (  ) 0 1 X 000,0  100,1 010,1  000,0 011,0  101,1 011,1  001,1 101,1  000,0 001,1  001,1 Y1Y1 Y0Y0 In this case too this is not a perfect one-shot:  The circuit operates ONLY if the input is sampled (as is the case with Moore) which is not always the case  The pulse duration is 3 clocks plus the distance between the input activation and the clock  If during a period (i.e. in  G) there are input variation these impact directly on the output without waiting for the clock edge!  Greater is the clock frequency more the circuit approximates the analog one-shot 44

45 Counters ABCD Z Inputless circuits (but for the clock) in the simplest version D0 !Q0 Q0 CK DFF MUXMUX 1 0 D1 !Q1 Q1 CK DFF (The clock is almost always omitted in the synchronous networks drawings (it is implicit) U0 U1 Carry Q1 switches when Q0 is 1 (and at the first positive clock edge Q0 switches to 0) 45 Example: binary counter x 4 with decoding of 3 (zero…!) 00,001,010,011,1

46 CK Qu1 Q0Q0 Carry (0) (1)(2)(0) (1)(2) (3) Binary counter x 4 with decoding of 3 46

47 Non 2’s power counters ABCD E D0 !Q0 Q0 CK DFF MUXMUX D1 !Q1 Q1 CK DFF MUXMUX 1 0 D !Q2 Q2 CK DFF This counter counts by 8: but in order to count base 5, after 4 (0,1,2,3,4) the counter must be reset Base 5 binary counter N.B. Q 2 Q 1 Q 0 47

48 D0 !Q0 Q0 CK DFF D1 !Q1 Q1 CK DFF MUXMUX 1 0 D2 !Q2 Q2 CK DFF MUXMUX 1 0 ABCABC “4” Counter x 5 Decoder When the decoder reaches 4 its output becomes zero and therefore all DFF inputs become 0 and upon the first clock positive edge all FFs outpus become 0 Synthesize a counter x 100 starting from a set of decimal counters (that is a counter base to be synthesized ) How many FF for a decimal counter ? “3” 48

49 Counters with control inputs i.e. An integrated counter base 6 with Load and Enable The counter counts base 16 (0-15!!) if EN = 1. When LD is asserted the input data are inserted in the 4 DFFs (either synchronously or asynchronously). In the previous case the decoder output «4» (positive true) must be connected to LD with all D i zero if LD is synchronous otherwise it is the «5» decoder output which must be connected to LD («5» is therefore an unstable transient state – race problem see later) In general a counter generates a “carry” output which is asserted when the counter reaches the value F H (that is ). This output can be connected to the enable of a cascaded counter so as to implement a counter (00 to FF – never forget the zero!) and so on. EN Q0 Q1 Q2 Q3 CK LD D0 D1 D2 D3 EN Q0 Q1 Q2 Q3 CK CY LD D0 D1 D2 D3 There are UP/DOWN counters whose (U/!D) input selects if the counting is up or down. In case of down count the carry is generated when all counters FFs are zero. There is a wealth of different counters, each one with its specific behaviour, with or without RESET (normally asynchronous), U/!D, with or without LD etc. etc. NB: Each synchronous circuit (with non binary sequence too) whose state diagram can be assimilated to that of a counter IS in any case a counter Non binary counter x 5 Q2 Q1 Q0 49

50 74163: a counter with Load, Reset and two anded enables (T and P). The control signals are synchronous that is they act on the clock rising edge 74138: decoder 3:8 with negative true outputs if G2A and G2B zero and G1=1. Otherwise all outputs are 1 no matter what is the input Binary counter x 8 with decoding 50

51 Post-route simulation Disalignment 51

52 What happens for the previous base 5 counter upon the power-on if no RESET is avalable? Unpredictable state which could not belong to the expected cycle. NB The power-on state is absolutely random and depends on the electrical conditions of the circuit Let’ suppose the FFs state is 110 (6 10, out of the cycle). Let’s analyse the behaviour D0 !Q0 Q0 CK DFF D1 !Q1 Q1 CK DFF MUXMUX 1 0 D2 !Q2 Q2 CK DFF MUXMUX 1 0 ABCABC “4” In this case after a transient behaviour the system re-enters the regular wanted cycle but the behaviour depends on the implementation and with different implementations the three «external states» could be totally separated from the main cycle which would never be reached. RESET signal !!! Q2Q1Q0Q2Q1Q0 101

53 As a didactical example only (never to be used !!!!!!) let’s see the transition table of an Up/!Down base 6 10 counter (0-5 values) with Reset. The input signals are synchronous To compensate the power-on effect Sinthesize and simulate How should the Xilinx schematic modified so as to allow a presetting of the counter? Up/!Down Res ??111 ???? ?? 101 y 3 y 2 y Up/!Down Res y 3 y 2 y 1 53

54 UP/DOWN counter with Reset «Direct» y 2 synthesis Let’s find the states where y2 must assume the value «1» Up/!Down Res y 3 y 2 y 1 UP/!Down D0 Q0 CK FFD Clock y2y2 DecoderDecoder y3y2y1y3y2y1 “1” “2” “3” “4” MUX 54 DownUp

55 Safe again … Using a counter base 8 (but also base 16 etc.) with synchronous reset always enabled how can we implement the opening mechanism of the safe (sequence X 1 X ) Moore model ? Cx8 RES Q0 Q1 Q2 CK ABCABC “0” “1” “2” “3” “4” RL AND-OR X1X1 X2X2 RES Z Cx8 RES Q0 Q1 Q2 CK RES= ! (“0”!X 1 !X 2 + “1” !X 1 X 2 + “2” !X 1 X 2 + “3” X 1 !X 2 ) - counts «+1» if Reset is not active (it is disabled only if for each counter configuration the right input configuration is inserted) (in any case after the opening the counter is reset ) Z = “4” (“0”,”1”,”2”,”3”,”4” are the three outputs binary decoding) The counter is reset whenever the right input (for the particular state) is not fed into the network The counter therefore is reset and keeps reset but for the conditions indicated by the function RES After reaching 4 (Z=1) the counter is reset upon the following clock positive edge The synchronous logical networks are always designed as combinations of standard available blocks and random logic (and, or etc.)

56 Counters EN Q0 Q1 Q2 Q3 CK CY RESET Warning !!! Let’s consider the following counter (with asynchronous RESET ) and suppose we want to count base 5 (N.B. for the Reset we must use in this case «5” …. glitch..) ABCDABCD “5” “1” Why is this schematic wrong? But there is a possible critical race !! When a single DFF is reset (and not necessarily at the same instant) the decoder doesn’t decode “5” any more and therefore to some FFs the reset is cancelled. Then ? EN Q0 Q1 Q2 Q3 CK CY RESET ABCDABCD “5” “1” R S !Q “0” By so doing “5” activates the SET and the SR FF is not reset until the counter reaches “0”. NB the «wrong» schematic can be used only if the designer is sure of the reset speed of all counter FFS Verify with Xilinx (post route) 56

57 Safe synthesis with modules 57 Decoder RESET control network Synchronous RESET counter Decoder Output Initially the counter is reset with input 01, 10 o 11 (all AND outputs are 0 and therefore the NOR is 1 and the Reset is 1). With input 00 the first AND becomes 1, the reset becomes 0 and the counter counts to 1. If then the input is 01 the second AND becomes 1 and the reset is kept 0. Any other inputs reactivates the RESET. This behaviour is repeated until the counter reaches 3: the output becomes then 1 and at the next clock the counter is in any case reset waiting for a successive 00 input.

58 Post-Route simulation As forecasted there are delays between inputs and outputs of each device: the total delay is 10 ns. The initial signals high impedace indicates that the network needs an input for the initial stabilisation before a correct behaviour 58

59 59 Exercise n.1 – Synchronous networks A logical network must implement a synchronous network based on a binary counter base 4 with synchronous EN and U/!D commands so that the output sequence is (ripetitive) Direct synthesis (using DFFs, decoders etc) Formal Synthesis Transition table y3y2y1y3y2y1 z2z1z2z1 001,00 001,01001,11 001,10 001,11001,10 001,00001,01 y3y3 y2y1y2y Karnaugh Map Another alternative transition table y3y2y1y3y2y1 z2z1z2z1

60 EN= DEC1+DEC2+ DEC3*!(U/!D)+DEC0*U/!D Starting from 00 with U/!D=1 the counter counts up keeping EN=1 until 11 is reached (DEC3), when EN becomes 0 and therefore at the next clock the counter doesn’t count while U/!D switches activating DOWN=1 [that is !(U/!D) = 1]. EN becomes then 1 and the counter counts down (as long as DOWN is 1) until 00 when the stall occurs again 60 State tables(to be completed..) Q1 Q0 U/!D EN 1.. Cont x 4 Q1Q1 Q0Q0 U/D* EN Dec 3 0 FFD Q U/!D D MUXMUX 1010 SEL !Q EN The FF switches only if EN=0 What network for EN ? ?

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