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Synchronous logical networks I

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1 Synchronous logical networks I
Digital Systems M

2 Asynchronous network problems
The behaviour depends on the feedback delays with all related possible malfunctionings (different delays) The behaviour depends on the input hazards (which in any case can’t be exactly concurrent) and prevents the detection of repeated input sequences (i.e. the sequence is the same as ) SOLUTION An «artificial» input concurrency detection and forced and controlled feedback delays

3 Synchronism signal Z0..m Combinatorial network Y0..k s/r0..k X0..n t
FF SR0..k t Synchronism signal If the pulse is short enough and less than the combinatorial network delay (that is the combinatorial network minimum delay) the new s/r0..k produced by the combinatorial network do not reach the blocking AND before the AND outputs are zeroed making the SR FF stable (the SR FF with both inputs zero doesn’t change status). Only during the following t pulse the new FF outputs values are transmitted to the combinatorial network with no feedabck effets again. Forced feedback alignment. It must be noticed that this way the combinatorial networks inputs too are forcibly «aligned» as far as the status is concerned. No «race» problems (but for the output in the Mealy case) The outputs are almost perfectly aligned (that is they are synchronous) if the sequential machine is Moore type (the outputs depend only from the state variables) and the FFs switch concurrently (which is very likely)

4 Synchronism signal The synchronism signal is always referred to as clock Normally the clock signal is a regular repetitive square (or rectangular) wave of T period (but not necessarily) A SR FF with a clock signal is referred to as synchronous SR (which in the real systems is never used) What problems arise with the clock signal of the figure ? The pulse duration should be extremely narrow since a combinatorial network can consist even of a single wire and in this case the delay is only the wire propagation delay! In practice it cannot be implemented Clock T

5 The synchronous FFs There are several synchronous FFs but nowadays only the DFF is used whose behaviour was previously analysed as an asynchronous network but which here is used as a synchronous FF (in its 74xx74 version) D Q !Q CK The DFF has this name name because D stands for Delay. In fact the output Q follows the input D with a T period delay (if the input signal is synchronous – that is is generated concurrently with the clock – respecting however setup and hold times – for instance by a network controlled by other DFFs using the same clock) or in presence of the first clock rising edge. The triangle on the clock input (CK) indicates that the FF is edge triggered that is it switches on the positive edge of the clock D Q !Q CK PR CL The signals !CL(ear) and !PR(eset) act asynchronously that is immediately, independently from the clock

6 Combinatorial network
The DFF switches ONLY during the transition of CK fro 0 o 1. This corresponds to the very short pulse t seen before. If the transition is fast enough the combinatorial network cannot react before the CK transition is finished Combinatorial network X0..n Z0..m y0..k Y0..k Clock D0..k Q0..k FFD0..k CK The clock of the DFF must switch from 0 to 1 only when the combinatorial network is stable (quiet). The transfer of the DFF input to its outputs (transition time) must fast enough to grant the the new D inputs generated by the combinatorial network because of the new values of Yi arrive after the end of the CK transition. Then there is a solid time period for the combinatorial network to reach a new stable state. The period of the CK must be in any case greater than the time required by the combinatorial network to reach its stable state.

7 VHDL Let’s consider the DFF DFF D D Q Q CK CK Q* QN CK D Q

8 entity DFF_1 is Port ( D : in std_logic ; CK : in std_logic ; Q : out std_logic; QN : out std_logic ); end DFF_1; architecture Behavioral of DFF_1 is begin process_FF: process(CK,D) if (CK'event) and (CK='1') then Q <= D; QN <= not(D); -- Careful! QN <= not(Q) must not be used !!!!!! -- otherwise QN switch would not be concurrent with Q end if; end process process_FF; end Behavioral; “if (CK'event) and (CK='1')” means that the switch occurs in presence of an edge of CK and the final value is 1 (CK=1). Rising edge !

9 Behavioural simulation

10 DFF with Set and Reset (VHDL)
A_SET DFF A_SET D D Q Q CK CK Q* QN A_RES A_RES Asynchronous commands A_SET and A_RES have precedence over the other inputs The two signals must not be activated concurrently (nonsense) In our case we want to model the DFF so as A_RES has precedence over A_SET

11 entity DFF_asynchronous_commands is
Port ( CK : in std_logic; D : in std_logic; A_SET : in std_logic; A_RES : in std_logic; Q : out std_logic; QN : out std_logic); end DFF_asynchronous_commands; architecture Behavioral of DFF_asynchronous_commands is begin Process_FF: process(CK, A_SET, A_RES, D) -- positive logice if (A_RES='1') then Q <='0'; QN <='1'; elsif (A_SET = '1') then only if A_RES inactive Q <='1'; QN <='0'; elsif (CK='1') and (CK'event) then Q <= D; QN <= not(D); end if; end process process_FF; end Behavioral;

12 higher priority (see VHDL)
Asynchronous Reset (A_RES=1, A_SET=0) Both asynchronous commands active (A_RES=1, A_SET=1): asynchronous reset has higher priority (see VHDL) Asynchronous Set (A_RES=0, A_SET=1) Positive logic !

13 Synchronous sequential networks
Combinatorial network X0..n Z0..m y0..k Y0..k Clock D0..k Q0..k FFD0..k CK See the architecture of the asynchronous networks with SR FF feedback where S=!R The synthesis is performed as in the case of an asynchronous network with direct feedback but inputs remaining constant are considered by the network as different since they are considered in different periods and therefore in presence of possible different states of the FFs What matters in this case is the clock positive edge: the time distance between two consecutive rising edges (respecting setup e hold times) DOESN’T count Clock period (frequency) must be greater (smaller) than the max combinatorial network delay. The combinatorial network must be stable after a clock positive edge before a new clock positive edge can occur The clock rising edge differentiates input and output (it separates them from the time point of view)

14 S S* S O S* I CK RC k (k) DFF I O t t+T t+2·T t-T
Synchronous Sequential Networks (SSN) k (k) DFF S S* CK RC I O k feedback DFFs All with the same clock of T period S O S* I t t+T t+2·T t-T CK In this case: Moore or Mealy ?

15 The DFF as fundamental SSN element
If a periodic signal is sent to CK (clock) input, the DFF (D = Delay) delays the output signal Q a time equal to the period T if the change of D is logically (but not physically) concurrent with CK (but always respecting setup and hold times) Qn+1 = Dn DFF D CK Q Q* NB:since here the time is discrete, n and n+1 (periods) are used instead of T e T+t D CK Q T NB: The concept of concurrency could seem to be in contrast with the need of respecting setup and hold times. As a matter of fact the inputs of a synchronous network are in the great majority of cases the outputs of other networks which have the same clock and therefore with their delays which grant automatically the respect of setup and hold. Therefore the variations of the inputs are always a little later than the clock edge. See later the behaviour of the shift registers

16 Synchronous Sequential Networks
The states changes occur only with the rising edges of the clock and therefore with T period (if the clock is periodical) The network changes its outputs every T and therefore if a very responsive network is required, as far as the outputs are concerned, the Mealy model must be adopted The states evolution is independent from the combinatiorial network (provided the distance between the rising edges of the clock is greater that the maximum delay of the combinatorial network)! Thereofre no critical races problem Within the same system (i.e. a processor) more SSNs are present, not necessarily with the same clock SSNs can be more easily designed than the ASNs

17 Clock gating and clock glitch
In the synchronous sequential networks unwanted clock glitches mus be avoided which could induce unwanted DFF switches . For instance because of the different delays of the n signals I[n-1..0] of a decoding network, hazards (glitches) can occur provoking the “clock gating“ effect X CK Q Q* FFD D CK_G Decoding network I[n-1..0] P t NO !! CK P CK_G Clock glitches → possible unwanted DFF switch Obviously it depends on the spurious glich duration: if too narrow the FF could be not triggered (the clock pulse must always have a minimum width which depends on the FF technology: when too narrow either is not sensed by the FF or can cause metastability). The clock gating is not prohibited but is a risk to be avoided when possible.

18 Clock gating and clock glitch
For transitions which must or must not take place depending on a decoding network the solution of the figure must be adopted. If the decoding output is 1 Qn+1 = Dn otherwise Qn+1 = Qn 1 SEL FFD D CK Q Q* Q X 1 SEL t Decoding network Q* CK I[n-1..0] P

19 Clock gating e clock-skew
The clock gating, in addition to cause potential glitches produces also a “clock-skew” (disalignmento). Let’s consider two SSN, DFF1 and DFF2 I1 CK B B* CK_G P I2 A A* tAND DFF-1 D Q Q* DFF-2 The two networks clocks are out of phase beacuse of the inserted AND delay time tAND. This phenomenon - clock-skew - is potentially very dangerous since DFF-2 could sample the new (and not the previous) value of DFF-1 albeit the clock should be the same CK CK_G tAND NB: The “clock-skew” is not only caused by the clock gating but also (for example) by different electrical paths

20 Combinatorial network Combinatorial network
Input synchronization Up to now we have implicitly assumed that the inputs of a synchronous network switch synchronously with the clock This is true if the inputs come from a Moore type network where the outputs depend only from the state, which switches synchronously with the clock. X0..n y0..k Combinatorial network Y0..k DFF0..k D0..k D0..k Q0..k Q0..k CK CK Clock Combinatorial network Z0..m AS a matter of fact, the real situation is normally different. Let’s consider for instance a push button as the input of a synchronous network. Its status change can occur any time. In the network of the figure (Moore) the outputs are in any case synchronous with the clock: if the input X0..n change asynchronously from the clock their changes are detected by the network feedback FFs only at the clock positive edge and therefore the network behaviour is the same it would occur if the inputs were synchronous

21 Combinatorial network
Input synchronisation The situation is different however with a Mealy network Z0..m X0..n Combinatorial network Y0..k y0..k D0..k D0..k Q0..k Q0..k CK CK Clock FFD0..k In this case an asynchronous input change triggers, in general, an asynchronous output change

22 … Safe … synchronous…. Example: the safe (with a two keys keyboard) opens only if the inputs temporal sequence is Each sequence violation restarts the system. NB Since the inputs are sampled the sequence is possible and meaningful 11 00 11 00 00 00 01 A,0 B,0 C,0 D,0 10 E,1 For each state ALL input configurations !! 01 11 11 00 11 10 00 11 10 00 10 01 10 01 01 11 The states are not necessarily stable for the input configurations which led to them G,0 10 F,0 01 10 01 NB: It can be assumed that the inputs change concurrently with the state variables but this is not necessary. If the network is Moore type even if the inputs change in the middle of a clock period the behaviour from the state point of view (and therefore from the outputs point of view) is in any case the same (each input variation is sampled only at the period end))

23 Synchronous Safe 11 B 00 01 11 10 F A G C D E AA- 1 X1 X2 00 A,0 11 B,0 00 00 00 01 01 C,0 D,0 10 E,1 11 11 00 11 10 01 10 10 10 01 00 01 01 11 00 G,0 10 F,0 01 11 10 01 NB: in this esample there are not don’t cares for the states. Instead of compatibile states therefore there are equivalent states. In general when two states for the same inputs have the same outputs and lead to the same states or equivalent states they are called indistinguishable. Obviously the system description could include some impossible inputs configurations: in this case we go back to the compatibility concept. The same applies when one ore more outputs are don’t care (a very unlikley situation since all states last one period)

24 Equivalence (not compatibility) classes
Synchronous Safe B 00 01 11 10 F A G C D E AA- 1 X1 X2 B C D E F G A CF FD CD GE DF --- C F -- b 00 01 11 10 a g d e X1 X2 1 Equivalence (not compatibility) classes [AFG] => a [B] => b [C] => g [D] => d [E] => e Obviously 5 states: 4 belongs to the correct sequence and one is out of it NB: In case of fully specified tables the maximal equivalence classes have NO states in common (the transitive property i valid). Since they are disjoint all of them must be used and therefore there is NO closure problem

25 Synchronous Safe 00 01 11 10 1 a => 000 b => 001 g => 011
d e X1 X2 1 No race problems: free states coding 001 00 01 11 10 000 011 010 100 X1 X2 -- 101 111 110 1 Y1 Y2 Y3 a => 000 b => 001 g => 011 d => 010 e => 100 Using DFFs the D inputs synthesis is achieved by synthesizing Yi (Yn+1=Dn) D1= X1!X2Y2!Y3 D2=!X1X2Y3 D3=!X1!X2+!X1!Y2Y3 Z =Y1 NB: The synthesis is made on the assumption that the opening input configurations follow synchronously with a distance of a period. Should the safe open ONLY when the sequence is correct no matter how many times a single correct input is repeated an auto-ring must be provided in the corresponding state

26 Xilinx schematic

27 Behavioural Simulation
Post-route Simulation

28 If Mealy ? B 00 01 11 10 F A G C D E AA- 1 X1 X2 B,0 00 01 11 10 F,0 A,0 G,0 A C,0 B D,0 C E,1 D E A,0A- F G X1 X2 In this case the safe opens as soon as the input becomes 10 in state D. Obviously this implementations opens the safe one period in advance compared with the Moore implementation Synthesize and simulate with Xilinx

29 Monoimpulsor A D Z Clock Z !Q2 Q1 D Clock
The aim is to generate a synchronous output pulse lasting one period when a «1» of an asynchronous input is detected. A further output pulse can be generated only when a «0» input is sampled and then a «1» is sampled again and so on D D1 Q1 !Q1 CK DFF D2 Q2 !Q2 CK DFF Z Clock (time diagram starts after D=0 for several periods) Z !Q2 Complement Q1 D Clock Here the asynchronous input D is synchronized by the DFFs.The output Z is synchronous with the clock

30 (A and D indistinguishable)
Monoimpulsor A 1 A,0 B,1 1 Moore necessarily if we want the output synchronous with the clock! C,0 1 A - B C D Q2 Q1 1 Z 00 -- 10 11 D Q2 Q1 D 01 1 C 11 B 10 Z - A 00 Q1=D Q2= DQ1 Z=Q1!Q2 00 10 11 01 B C D A Synchronous network: no races!! A B C D 00 01 10 11 Q2 Q1 1 Z Same behaviour! But using D … (A and D indistinguishable) D1 Q1 !Q1 CK DFF D2 Q2 !Q2 Z D Clock Q1=D Q2= Q1 Z=Q1!Q2

31 Monoimpulsor B D Z Clock Z !Q2 Q1 D Clock D1 Q1 !Q1 CK DFF D2 Q2 !Q2
A Mealy network: with an asynchronous input we have an asynchronous output Z lasts a period plus the inizial phase (D>period) Here Z duration depends on the input only (D<period) Z (time diagram starts after D=0 for several periods) !Q2 Q1 D Clock

32 Monoimpulsor C D Z Clock Z Q D Clock
DFF Z Clock Mealy network: with an asynchronous input we have an asynchronous output Z =1 if D=1 and is sampled (time diagram start after D=0 for several periods) Z Q D Clock After the DFF has sampled a 1, if the input oscillates then the output oscillates until the DFF samples a 0

33 Monoimpulsors A, B e C The exact state diagram corresponding to the real behaviour of monoimpulsors B and C CANNOT be drawn because the two networks (Mealy type) are NOT synchronous. A synchronous state diagram implies that the inputs too are synchronous, which is not the case with B and C This is not the case of the monoimpulsor A either, since although the input is asynchronous the output (Moore type) depends on the states only. The network behaviour makes internally synchronous the inputs which are physically asynchronous A real state diagram of monoimpulsors B and C can be designed only using an asynchronous analysis, that is “opening” the DFF. Obviously it is always possible to design the two networks without the DFFs starting from an asynchronous traditional states diagram.

34 Monoimpulsor C (asynchronous description): design a network with two inputs C and D and an output Z. The output Z is zero if D=0 independently from C. A transition of C from 0 to 1 samples always D and Z=1 if both the sampled value and D are 1 Q=1 Q=0 01,0 00,0 A CD,Z 01,0 D 10,0 B 11,0 C 01,0 00,0 10,0 00,0 10,0 11,0 11,- 10,- 11,1 11,1 01,1 11,1 E 01,1 F 00,0 G 10,0 H 10,0 01,1 00,0 00,0

35 [ABC] [AD] [EFH] [FG] [ABC] [D] [EFH] [G] a b g d 00 01 11 10 A B C D
---- B,0 A C,0 B C E,- D F,1 E,1 H,1 E G,1 F B,- G H B C D E F G A -- CE H BH a,0 00 01 11 10 b,0 a g,- -- b d,1 g,1 g a,- d C D [ABC] [AD] [EFH] [FG] [ABC] [D] [EFH] [G] a b g d

36 Y1= y2C + y1!C Y2= y2C + D!C Z = y1D 00 01 11 10 a b g d
00,0 00 01 11 10 01,0 C 11,- -- 10,0 11,1 11,0 00,- D y2 y1 a b g d a,0 00 01 11 10 b,0 a g,- -- b d,1 g,1 g a,- d C D Y1= y2C + y1!C Y2= y2C + D!C Z = y1D This is the state table of the DFF (see asynchronous networks) with a different output Post route simulation. Why the behavioural doesn’t function properly?

37 Xilinx Monoimpulsors Input Input: X ( respecting setup and hold times)
Multiple outputs: ZA monoimpulsor 'A' ZB monoimpulsor 'B' ZC monoimpulsor 'C‘ Input Xilinx Monoimpulsors

38 Behavioural simulation
Post-route simulation Arrow => sampling delay

39 A retriggerable one-shot (trigger => activation signal) is a circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X. When another positive edge of X occurs during the pulse Z, the circuit extends the pulse Z of another T time. Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to the clock (of frequency f=1/T) produces in a retriggerable way a pulse of 3 clock periods, synchronous with the clock. Normal one-shot Retriggerable one-shot 3

40 E,0 A,0 B,1 C,1 D,1 F,1 G,1 NB Synchronous output 1 1 X 1 1 1 1 1
The outputs becomes 1 with the first clock positive edge sampling X=1. From each state the number of branches is equal to the number of input configurations !!! 1 With X=1 at least a three periods output E,0 1 X 1 1 1 A,0 B,1 C,1 D,1 1 1 F,1 G,1 With input=0 the three periods output is in any case produced, which is extended in case an input=1 is sampled again NB Synchronous output

41 All states are distinguishable
X 1 A A B B B F C 1 FG CD C C G D 1 AF CE AG DE D D A E 1 E BE E A E FG BC AG BE F DB F G B 1 AF CB AG DB G BE AG G A B 1 A B C D E F All states are distinguishable

42 1 1 1 1 - 1 Z = Y0 + Y1 (Y2 Y2 Y1 Y0)n Y1 Y0 X Y2 (Y2Y1Y0)n+1 Y1 Y0
1 Y1 1 Y2 Y0)n Y1 A A B 00 000 000 001 Y0 01 11 10 1 1 B F C 1 001 101 010 1 1 1 1 - 1 C G D 1 010 110 011 1 D A E 1 011 000 100 1 Z = Y0 + Y1 E A E 100 000 100 F G B 1 101 110 001 1 G A B 1 110 000 001 1 X Y2 Y1 (Y2Y1Y0)n+1 Y0 00 01 11 10 00 000 000 100 001 D2 = !X!Y1Y0 + XY2!Y1!Y0 + XY1Y0 + !X!Y2Y1!Y0 D1 = !X!Y2Y1!Y0 + !XY2Y0 + X!Y2!Y1Y0 + X!Y2Y1!Y0 D0 = X!Y2!Y1Y0 + XY2Y0 + XY1!Y0 + X!Y2!Y0 01 101 110 001 010 11 000 - - 100 The circuit does’t fully respect the characteristics of a real one-shot since the output pulse doesn’t start immediately upon a an input positive edge but only when the clock samples the input 10 110 000 001 011 (D2D1D0)n

43 Mealy solution E A B C D F G 0,0 1,0 0,0 1,0 X,Z 1,1 1,1 0,0 1,1 0,1

44 Maximal classes A,B,C,(DE),F,G (a,b,c,d,f,g)
1 Y1 1 Y0 A A,0 B,1 B a 000 000,0 001,1 B F,1 C,1 FG CD C b 001 100,1 010,1 C G,1 D,1 c 010 101,1 011,1 D D A,0 E,0 d 011 000,0 011,0 E E A,0 E,0 FG BC f 100 101,1 001,1 F DB F G,1 B,1 g 101 000,0 001,1 G G A,0 B,1 A B C D E F Maximal classes A,B,C,(DE),F,G (a,b,c,d,f,g) In this case too this is not a perfect one-shot: The circuit operates ONLY if the input is sampled (as is the case with Moore) which is not always the case The pulse duration is 3 clocks plus the distance between the input activation and the clock If during a period (i.e. in g -> G) there are input variation these impact directly on the output without waiting for the clock edge! Greater is the clock frequency more the circuit approximates the analog one-shot

45 Counters Inputless circuits (but for the clock) in the simplest version A B C D Z Example: binary counter x 4 with decoding of 3 (zero…!) 00,0 01,0 10,0 11,1 D0 !Q0 Q0 CK DFF M U X 1 D1 !Q1 Q1 (The clock is almost always omitted in the synchronous networks drawings (it is implicit) U0 U1 Carry Q1 switches when Q0 is 1 (and at the first positive clock edge Q0 switches to 0)

46 Binary counter x 4 with decoding of 3
CK Qu1 Q0 Carry (0) (1) (2) (3) (0) (1) (2) (3)

47 Non 2’s power counters Base 5 binary counter N.B. Q2Q1Q0 D0 !Q0 Q0 CK
000 001 010 011 100 Base 5 binary counter N.B. Q2Q1Q0 D0 !Q0 Q0 CK DFF M U X 1 D1 !Q1 Q1 D !Q2 Q2 This counter counts by 8: but in order to count base 5, after 4 (0,1,2,3,4) the counter must be reset

48 Counter x 5 M U X 1 D0 !Q0 M U X 1 D1 !Q1 Q1 CK DFF DFF D2 !Q2 Q2 CK DFF Q0 CK “3” A B C “4” Decoder When the decoder reaches 4 its output becomes zero and therefore all DFF inputs become 0 and upon the first clock positive edge all FFs outpus become 0 Synthesize a counter x 100 starting from a set of decimal counters (that is a counter base 1010 to be synthesized ) How many FF for a decimal counter ?

49 Counters with control inputs
EN Q0 Q1 Q2 Q3 CK LD D0 D1 D2 D3 i.e. An integrated counter base 6 with Load and Enable The counter counts base 16 (0-15!!) if EN = 1. When LD is asserted the input data are inserted in the 4 DFFs (either synchronously or asynchronously). In the previous case the decoder output «4» (positive true) must be connected to LD with all Di zero if LD is synchronous otherwise it is the «5» decoder output which must be connected to LD («5» is therefore an unstable transient state – race problem see later) In general a counter generates a “carry” output which is asserted when the counter reaches the value FH (that is 1510). This output can be connected to the enable of a cascaded counter so as to implement a counter (00 to FF – never forget the zero!) and so on. EN Q0 Q1 Q2 Q3 CK CY LD D0 D1 D2 D3 There are UP/DOWN counters whose (U/!D) input selects if the counting is up or down. In case of down count the carry is generated when all counters FFs are zero. There is a wealth of different counters, each one with its specific behaviour, with or without RESET (normally asynchronous) , U/!D, with or without LD etc. etc. NB: Each synchronous circuit (with non binary sequence too) whose state diagram can be assimilated to that of a counter IS in any case a counter Q2 Q1 Q0 101 010 000 111 110 Non binary counter x 5

50 Binary counter x 8 with decoding
74163: a 1610 counter with Load, Reset and two anded enables (T and P). The control signals are synchronous that is they act on the clock rising edge 74138: decoder 3:8 with negative true outputs if G2A and G2B zero and G1=1. Otherwise all outputs are 1 no matter what is the input

51 Post-route simulation

52 What happens for the previous base 5 counter upon the power-on if no RESET is avalable? Unpredictable state which could not belong to the expected cycle. NB The power-on state is absolutely random and depends on the electrical conditions of the circuit Let’ suppose the FFs state is 110 (610, out of the cycle). Let’s analyse the behaviour 000 001 010 011 100 110 111 Q2Q1Q0 101 M U X 1 D0 !Q0 M U X 1 DFF D1 !Q1 Q1 CK DFF D2 !Q2 Q2 CK DFF Q0 CK A B C “4” In this case after a transient behaviour the system re-enters the regular wanted cycle but the behaviour depends on the implementation and with different implementations the three «external states» could be totally separated from the main cycle which would never be reached. RESET signal !!!

53 Sinthesize and simulate
As a didactical example only (never to be used !!!!!!) let’s see the transition table of an Up/!Down base 610 counter (0-5 values) with Reset. The input signals are synchronous 00 01 11 10 Up/!Down Res 000 001 010 011 100 101 ? 111 110 y3 y2 y1 00 01 11 10 Up/!Down Res 000 001 010 011 100 101 111 110 y3 y2 y1 To compensate the power-on effect Sinthesize and simulate How should the Xilinx schematic modified so as to allow a presetting of the counter?

54 Clock Down Up UP/DOWN counter with Reset «Direct» y2 synthesis
Let’s find the states where y2 must assume the value «1» Up/!Down Res 00 01 11 10 y3 y2 y1 000 101 000 000 001 1 001 000 000 000 010 2 010 001 000 000 011 3 011 010 000 000 100 UP/!Down D0 Q0 CK FFD Clock y2 D e c o d r y3 y1 “1” “2” “3” “4” 1 MUX 4 100 011 000 000 101 101 100 000 000 000 110 000 000 000 000 111 000 000 000 000 Down Up

55 Safe again … Using a counter base 8 (but also base 16 etc.) with synchronous reset always enabled how can we implement the opening mechanism of the safe (sequence X1X ) Moore model ? Cx8 RES Q0 Q1 Q2 CK RES= !(“0”!X1!X2 + “1” !X1X2 + “2” !X1X2 + “3” X1 !X2) - counts «+1» if Reset is not active (it is disabled only if for each counter configuration the right input configuration is inserted) (in any case after the opening the counter is reset ) Z = “4” (“0”,”1”,”2”,”3”,”4” are the three outputs binary decoding) The counter is reset whenever the right input (for the particular state) is not fed into the network The counter therefore is reset and keeps reset but for the conditions indicated by the function RES After reaching 4 (Z=1) the counter is reset upon the following clock positive edge The synchronous logical networks are always designed as combinations of standard available blocks and random logic (and, or etc.) A B C “0” “1” “2” “3” “4” RL AND-OR X1 X2 RES Z Cx8 Q0 Q1 Q2 CK

56 Counters Warning !!! Let’s consider the following counter (with asynchronous RESET ) and suppose we want to count base 5 (N.B. for the Reset we must use in this case «5” …. glitch..) EN Q0 Q1 Q2 Q3 CK CY RESET “1” Why is this schematic wrong? A B C D “5” But there is a possible critical race !! When a single DFF is reset (and not necessarily at the same instant) the decoder doesn’t decode “5” any more and therefore to some FFs the reset is cancelled. Then ? EN Q0 Q1 Q2 Q3 CK CY RESET “1” A B C D R S !Q “5” “0” By so doing “5” activates the SET and the SR FF is not reset until the counter reaches “0”. NB the «wrong» schematic can be used only if the designer is sure of the reset speed of all counter FFS Verify with Xilinx (post route)

57 Safe synthesis with modules
Decoder RESET control network Synchronous RESET counter Output Initially the counter is reset with input 01, 10 o 11 (all AND outputs are 0 and therefore the NOR is 1 and the Reset is 1). With input 00 the first AND becomes 1, the reset becomes 0 and the counter counts to 1. If then the input is 01 the second AND becomes 1 and the reset is kept 0. Any other inputs reactivates the RESET. This behaviour is repeated until the counter reaches 3: the output becomes then 1 and at the next clock the counter is in any case reset waiting for a successive 00 input.

58 Post-Route simulation
As forecasted there are delays between inputs and outputs of each device: the total delay is 10 ns . The initial signals high impedace indicates that the network needs an input for the initial stabilisation before a correct behaviour

59 Direct synthesis (using DFFs, decoders etc)
Exercise n.1 – Synchronous networks A logical network must implement a synchronous network based on a binary counter base 4 with synchronous EN and U/!D commands so that the output sequence is (ripetitive) Direct synthesis (using DFFs, decoders etc) Formal Synthesis 001 000 010 100 011 00 01 10 11 101 110 111 Transition table y3y2y1 z2z1 001 000 011 010 110 00 01 10 11 100 101 111 Another alternative transition table y3y2y1 z2z1 001,00 001,01 001,11 001,10 y3 y2y1 1 00 01 11 10 Karnaugh Map

60 State tables(to be completed..)
Cont x 4 Q1 Q0 U/D* EN Dec 3 FFD Q U/!D D M U X 1 SEL !Q The FF switches only if EN=0 What network for EN ? ? Starting from 00 with U/!D=1 the counter counts up keeping EN=1 until 11 is reached (DEC3), when EN becomes 0 and therefore at the next clock the counter doesn’t count while U/!D switches activating DOWN=1 [that is !(U/!D) = 1]. EN becomes then 1 and the counter counts down (as long as DOWN is 1) until 00 when the stall occurs again State tables(to be completed..) Q1 Q0 U/!D EN 1 .. EN= DEC1+DEC2+ DEC3*!(U/!D)+DEC0*U/!D

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