Download presentation

Presentation is loading. Please wait.

Published byNoemi Farson Modified over 2 years ago

2
Design Methods and Circuit Techniques to Reduce Leakage in Deep Submicron Christian Piguet, CSEM, Neuchâtel, Switzerland Stefan Cserveny, CSEM Jean-Félix Perotto, CSEM Jean-Marc Masgonty, CSEM

3
C. Piguet :: 07.04.2015 :: Page 3 Leakage: Dramatic Situation From 1992 to 2002, most of the work in power reduction has been performed for dynamic power Today, for deep submicron, there is a clear shift: leakage or static power is a dramatic issue Leakage during active mode, leakage during Idle or Sleep mode, leakage is more dramatic for very long idle mode Ad Hoc networks

4
C. Piguet :: 07.04.2015 :: Page 4 130 nanometers technology I static (A)slow-slowtypicalfast-fast -10 o C2.1E-061.2E-057.0E-05 25 o C1.7E-058.2E-053.9E-04 50 o C6.1E-052.5E-041.1E-03 Circuit with 5 millions of MOS, 0.6 Volt: - 1 mA leakage is larger than the total specified current!!!!!

5
C. Piguet :: 07.04.2015 :: Page 5 Total Power with Vdd and VT Reduction Optimum at 50% dynamic and 50% static Dynamic power is reduced with Vdd 2 Static Power is increased exponentially with lower VT There is an optimum for a given Vdd But it is dependent on the activity At constant clock frequency

6
C. Piguet :: 07.04.2015 :: Page 6 Leakage Reduction Techniques Portables devices, Ad-Hoc networks: very low activity Leakage reduction factors of 100 are often required Circuit: Several VT, Variable VT, Shut down Gate: Stacked transistors, Input Vectors Architecture: Very few innovative techniques (a low activity is far from the optimum, the goal could be less transistors but higher activity) Techniques at Circuit, Gate and Architecture Levels

7
C. Piguet :: 07.04.2015 :: Page 7 Circuit Techniques I Deep Submicron Technologies provide low and high VT Low VT on the critical path, high VT elsewhere 10-20% of the gates are low VT (for industrial circuits) Achieved reduction factor of about 10 Factor 7 for a processor of Hitachi But factor 100 for its clock tree Several VT or MTCMOS

8
C. Piguet :: 07.04.2015 :: Page 8 Circuit Techniques II Bias voltages on substrates High VT in idle or low activity modes Low VT for speed performances Dynamic VT shift Variable VT or VTCMOS or SATS In deep submicron, the slope factor n is smaller and smaller Larger bias voltages are required for smaller VT variations SOI: the slope factor n is very close to 1 Problem Vdd=2 V. VTp= -0.2 V. active mode VTp= -0.6 V. idle mode VTn= 0.2 V. active mode VTm= 0.6 V. idle mode Bias 2 V. active mode 4 V. idle mode 0 V. active mode -2 V. idle mode

9
C. Piguet :: 07.04.2015 :: Page 9 Circuit Technique III Proposed for SOI Gate connected to MOS body VT is high when the MOS is off VT is low when the MOS is on DTMOS MOS in weak inversion, very low Vdd If Vdd smaller than VT, very slow Limited VTCMOS in direct and reverse polarization Weak Inversion Logic Vdd S Vss I VT VT Direct Diode substrate to source: input current Reverse

10
C. Piguet :: 07.04.2015 :: Page 10 Circuit Techniques IV Switches in supply wires Circuit voltage drop High VT for switches, low VT for the circuit Circuit MOS: source voltage at Vss’ higher than Vss: VT shift But the voltage drop could be large, flip-flops loose their data Shut down of the circuit (I) circuit Vss Vss’>Vss Vss Vss’ Vss Leakage Switch size Without switches low VT high VT switches Large Switches: - small leakage reduction but large speed Small Switches: - the contrary

11
C. Piguet :: 07.04.2015 :: Page 11 Circuit Techniques V Technique to keep the data Circuit drop is limited Various circuits available Discharge of Vss’ if too high Very good technique Applied to SRAM Shut down of the circuit (II) LIMITER for Vss’ Circuit with NMOS sources connected to Vss’ Vss MNS GS I C - I SW Vss’ Switch

12
C. Piguet :: 07.04.2015 :: Page 12 Gate-Level Techniques Just to list them: Logic families when leakage is very different for N-ch and P-ch N-MOS logic, or P-MOS logic, or precharge logic Stacked transistors A given input vector for a gate/circuit Many techniques, but they do not achieve large leakage reduction

13
C. Piguet :: 07.04.2015 :: Page 13 Architecture Techniques I A low activity is detrimental for the ratio static over dynamic power For a given logic function, various architectures Is it possible for this logic function to reduce the number of transistors (less leakage) by using more intensively the transistors, i.e. by increasing the activity? Are non-pipelined, pipelined, parallel, …, architectures better ? Assuming that this logic function require 100 gate transitions, how to design this function with the minimal number of MOS? If 10’000 MOS, a= 1%; if 1’000 MOS, 1/10 leakage, same dynamic power (100 transitions) but a=10% Paradigm Shift

14
C. Piguet :: 07.04.2015 :: Page 14 Architecture Techniques II Better use of transitions Efficiency = Td /period = Td * f (period=1/f) The number of gates in series or logical depth LD With 20 gates in series, using fully the reference period, each gate will use 1/20 of this period, and being idle during 19/20 So the efficiency = 1/20 = 5% Finally: = 1/LD Efficiency time reference period =0.5 Td idle Gate 1 Gate 2 Gate 3 Gate 4 Gate 5 Reference period

15
C. Piguet :: 07.04.2015 :: Page 15 Architecture Techniques III Used for comparing architectures for a given logic function: Activity a= nb of switching gates / total nb of gates Efficiency = 1/LD or the logical depth = LD The total number of gates N Load capacitance C of a logic gate I OFF leakage of a logic gate I ON dynamic power of a logic gate Design parameters for designing an architecture

16
C. Piguet :: 07.04.2015 :: Page 16 Architecture Techniques IV Circuit with N gates, in a given clock period: Edyn = a * N * C * Vdd 2 Estat = (1/f ) * N * Vdd * I 0FF Assuming full use of the clock period: fmax is the product of by fmax (1/delay) of a single gate, so fmax = * I ON /(C*Vdd) By uisng this expression in Estat, one has : Estat = (1/( * I ON )) * N * C * Vdd 2 * I 0FF So Etot = (a + 1/ * I 0FF /I ON ) * N * C * Vdd 2 Dynamic, static and total Energy (power*delay product) still to be reduced proportional to LD in critical path

17
C. Piguet :: 07.04.2015 :: Page 17 Architecture Techniques V Considering Etot = (a + 1/ * I 0FF /I ON ) * N * C * Vdd 2 50%-50% implies a = LD * I 0FF /I ON Or I 0N /I OFF = LD/a = 1/( *a) The ratio I 0N /I OFF could be small, i.e. 100, if LD=10 and a=0.1 I 0N /I OFF = 100 implies VT close to 0 Volt in 0.13 m at 27 C, Optimum total power at 50% dynamic and 50% static VTVddFrequency 500 mV1.2 V1 GHz 0 mV120 mV0.5 GHz 0 mV200 mV1 GHz 0 mV400 mV2 GHz If LD=100, a=0.01, high VT and high Vdd

18
C. Piguet :: 07.04.2015 :: Page 18 Architecture Techniques VI Assuming same speed performances VTVddDynamic.StaticTotal 370 mV1.533 mW0 mW33 mW 300 mV1.2525 mW0 mW25 mW 200 mV0.9715 mW4 mW19 mW 150 mV0.8310 mW7 mW17 mW 100 mV0.78 mW13 mW21 mW 50 mV0.557 mW26 mW33 mW [mV]

19
C. Piguet :: 07.04.2015 :: Page 19 Architecture Techniques VII To reduce drastically the total energy, one has to: To reduce Vdd and VT (to have reasonable speed) To have a low ratio I 0N /I OFF, for instance 100 50% - 50% dynamic versus static, i.e. I 0N /I OFF = LD/a Logic depth LD and activity a are the design parameters Architectures with small LD and high a Design rules at the architecture level

20
C. Piguet :: 07.04.2015 :: Page 20 Architecture Techniques VIII To reduce LD and increase a: Small LD requires pipelining or very fast architectures High activity is confusing, as many techniques for reducing activity have been proposed to reduce dynamic power It is not a non-useful increase of activity, such as glitches It has to be understood as reducing the total number of gates in the activity = nb switching gates / total nb gates, by keeping constant the number of switching gates (but activity depends also on modes) Design parameters LD and a

21
C. Piguet :: 07.04.2015 :: Page 21 Architecture Techniques IX To reduce LD ¼ LD Activity is the same Registers are neglected For the same throughput, i.e. same frequency for the two architectures, the same number of gates are switching. I 0N /I OFF = LD/a is 4 times smaller for the pipelined architecture Pipelined architectures

22
C. Piguet :: 07.04.2015 :: Page 22 Architecture Techniques X Does not reduce LD Same activity No effect Other architecture? Same number of transitions for a given logic function, but using less gates…. Parallel architectures

23
C. Piguet :: 07.04.2015 :: Page 23 Conclusion Has to be considered at circuit, gate and architecture levels Circuit Level: Reduction factors of about 100 achievable Gate Level. Only moderate reduction factors Architecture Level: to be checked Back to the old time ? When designers have to reduce the number of MOS, to re-use the same units, serial architectures? Leakage: Very important and interesting problem

24
T h a n k y o u f o r y o u r a t t e n t i o n.

Similar presentations

OK

©2004 Brooks/Cole FIGURES FOR CHAPTER 12 REGISTERS AND COUNTERS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

©2004 Brooks/Cole FIGURES FOR CHAPTER 12 REGISTERS AND COUNTERS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google