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High Performance Computer Architecture Lesson 60: Introduction to FPGAs All copyrighted figures are copyright of respective authors. Figures may be reproduced.

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Presentation on theme: "High Performance Computer Architecture Lesson 60: Introduction to FPGAs All copyrighted figures are copyright of respective authors. Figures may be reproduced."— Presentation transcript:

1 High Performance Computer Architecture Lesson 60: Introduction to FPGAs All copyrighted figures are copyright of respective authors. Figures may be reproduced only for classroom or personal educational use only when the above copyright line is included. They may not be otherwise reproduced, distributed, or incorporated into other works without the prior written consent of the publisher. Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 141

2 FPGA stands for “Field Programmable Gate Array” Yet Another Chip ! FPGA: what is it? Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 142 Courtesy XILINX

3 Temporal Computing (all chips we have seen so far) Software controls how to process data in a FIXED architecture Spatial Computing Software defines the ARCHITECTURE to process data FPGA: what’s new Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 143

4 Programmer specifies something like Example Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 144 Image could be subject to copyright

5 FPGA Synthesis Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 145 Image could be subject to copyright

6 Generalizing the Concept Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 146 Courtesy National Instruments

7 LUT stands for “Look Up Table” Definitions - LUT Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 147 Images courtesy of McGraw-Hill and Fundamentals of Digital Logic with VHDL Design, a highly recommended book.

8 LE stands for “Logic Element” Definitions - LE Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 148 Courtesy ALTERA

9 FPGA Logic Capability We can use LE as a unit to express the logic capability of the FPGA Traditionally: Altera: LE – Logic Element Xilinx: LC – Logic Cell 1 LC = 4-input LUT + D-FF + arithmetic/logic/register circuitry 1 LC = 1 LE Courtesy Prof. V. Milutinovic

10 FPGA Logic Capability (2) Improved functionality of "newer" FPGA architectures introduced new terms: ALM – Adaptive Logic Module for describing Altera's Stratix II family's adaptable structure CLB – Configurable Logic Block for describing Xilinx's FPGA families ELC – Equivalent Logic Cell Xilinx's new unit to better express logic density 1 ELC = LC 1 CLB has 8 LCs Courtesy Prof. V. Milutinovic

11 Example Chips Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 1411 Courtesy ALTERA

12 The Programmer prepares a description of the Architecture (e.g., VHDL, Verilog, but more recently “C” !) FPGA software Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 1412 VHDL SILICON COMPILER BITSTREAM FPGA

13 FPGA at work Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 1413 FPGA INPUT DATAOUTPUT DATA

14 Google “Prof VM” Click “teaching”, then VLSI, then PLD… Further References Roberto Giorgi, Universita' degli Studi di Siena, C215LEZ60-SL di 1414


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