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1 8086 Electronic Computers M. 2 “Logic” pinout of 8086 CPU Command bus Address bus Data bus ResetClockReady Int/Inta* Hold/Holda DMA.

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Presentation on theme: "1 8086 Electronic Computers M. 2 “Logic” pinout of 8086 CPU Command bus Address bus Data bus ResetClockReady Int/Inta* Hold/Holda DMA."— Presentation transcript:

1 Electronic Computers M

2 2 “Logic” pinout of 8086 CPU Command bus Address bus Data bus ResetClockReady Int/Inta* Hold/Holda DMA

3 3 SEGMENTS ACCUMULATORS CS DS SS ES AHAL BHBL CHCL DHDL AX BX CX DX 8086 (segmented !) Registers All memory addresses in the IAx architectures are computed as offsets from a base address stored in a segment register

4 4 SP BP SI DI BASE - STACK - INDEX IP FLAGShFLAGSl Registers

5 5 Segments FFFFF Stack Segment Word oriented Sstack X+2 X X-2 SS Segment base address SP (offset)Push Pop The stack grows downwards The BP is mainly used to address the stack segment as a memory data segment BP (offset) CS IP (offset) Code Segment Data Segment DS

6 TFDFIFOFSFZF Zero Sign Overflow Int. en. Direction Trap 4 AF 2 0 PFCF Carry Parity Aux. carry FLAGS

7 7 Address space: 1 MB Segmented memory Used segment: depends from the executed instruction Partitioning Relocation Protection 16 bit (offset) instructions Segment changes are rare (locality principle) Relocatable code Stack: word oriented Two operands instructions (i.e.mov AX,Mi) 8086 characteristics

8 8 OFFSET BASE OFFSET BASE B B 50460:2B 50460: : : :3 (Physical address = 5048B) SEGMENTS

9 FFFFF DS X CS Y SS Z ES W L X Z W K O N M Y E SEGMENTS

10 10 CS DS SS ES CS DS SS ES CODE STACK EXTRA DATA CODE DATA EXTRA STACK DYNAMIC RELOCATION

11 11 16 S + [(B + I + O) mod 64K] (0) 16 SEGMENT CS/DS/ES/SS Effective address 20 bits Modul 64K sum !!!!!! Each segment is therefore maximum 64K ! Address construction 16 BASE INDICE OFFSET SI/DI BP/BX

12 12 OPCODE MOD DISPL EFFECT. ADDR. BASED OPCODE MOD DISPL SI/DI EFFECT. ADDR. INDEXED DISPL EFFECT. ADDR. DIRECT OPCODEMOD BX/BP Address construction

13 13 OPCODEMODDISPL SI/DI EFFECT. ADDR. BASED INDEXED BX/BP OPCODE MOD BX/BP/SI/DI INDIRECT EFFECT. ADDR. Address construction

14 14 AX BX DX SP BP DI SI   CS DS SS ES IP Internal CS DS SS ES IP Internal registers BUS control Instruction queue EU control Temporary regs. ALU FLAGS EUBIU 4 bytes 8088 BIU-EU CX

15 (read) bus cycle Address Data in BUS CYCLE T1T2T3T4 CLOCK Memory: low, I/O: high AD0-AD19 ALE IO/M* RD* DT/R* DEN*

16 (write) bus cycles Address Status BUS CYCLE T1T2T3T4 CLOCK Memory: low, I/O: high A16-A19 AD0-AD15 ALE IO/M* WR* Data out Address DT/R* DEN*

17 17 Demultiplexed bus 7 3 BD[0:15) (Data bus) AD[0:15] A[16:19] BA [0:19] (Address bus) 8088 MN/MAX* ALE 4 16 DT/R* DEN* Vcc OE* CK EN*EN* DIR 16 To avoid bus conflicts

18 18 Readysignal Address Data in BUS CYCLE T1T2T3TW CLOCK AD0-AD15 ALE READY RD* TW T4 AddressStatus A16-A19

19 19 I/O interfacing I/O INTERFACE D[0:7] CS* RD* WR* A[0:n-1] Data Bus Command Bus Address Bus I/O peripheral Standard CPU interface Specific periheral interface Signals An interface adapts the system bus to the peripheral bus

20 20 I/O Interfaces Control Registers Within an interface there are several control registers addressed as memory cells (either with I/O or memory instructions) which instruct (program) the interface logical network on how it must behave to perform the interfacing Data Buffer Within the interface there are data buffers where transferred data (input or output) are temporarily stored for further forwarding to the destination (CPU or peripheral). Data Buffer are addressed as memory cells (either with I/O or memory instructions) Sincronization and Status Registers Normally the I/O peripherals work asincronously from the CPU. Therefore a synchronization mechanism must be implemented There are therefore Status Registers addressed as memory cells (either with I/O or memory instructions) which indicate the status of the transfer (i.e. a new data from the peripheral has been stored in the data buffer or the peripheral has read the data provided by the CPU but also whether the peripheral is OK etc.)

21 21 Generic I/O interface CS* RD* WR* Data Bus Command Bus Address Bus Peripheral DEC 01 EN* 2 3 OE* BufferIn CK BufferOut OE* Status CK Control A B Signals CK OE* CK OE* Port

22 22 I/O interface for 16 bit bus An 8 bit interface can be connected on the high or low bus If on the low bus only even addresses can be used for addressing the interface. He contrary for the high bus An example: two different intefaces located (CS* !!) at addresses 78 H (low bus) e 81 H (high bus alto) each one having 4 registers (read or write) A,B,C and D Proc. 16 bit D08-D15 D00-D07 Per-2 Per-1 ABCD 787A7C7E Registers Per-1 Per-2 As for the memories CS* depends also from A0 e BHE* Easy extension to 4(DLX) or 8 busses systems BLE* = A0 BHE*

23 23 Interrupts An interrupt is an event which “breaks” the normal program flow. The processor must start an appropriate procedure (interrupt handler) which handles the event causing the interrupt. An example is the transfer of data from an A/D converter: as soon as a new conversion is ready the A/D converter sends a signal to the computer which in turn must send the appropriate signal to the interface to read the new data and store them in an internal buffer. After the end of the interrupt handler the interrupted program flow must be resumed. «Normal» interrupts can be inhibited and un-inhibited by a proper machine instruction Interrupt classes: Hardware Interrupt : interrupt like the one previously described. The hardware interrupts can be inhibited by mean of a programmable internal flag IEN (interrupt enable/disable). Obviously there can be multiple external devices each one generating one or more interrupts and the 8086 has only one common interrupt pin. The intterrupts sources must be therefore detected Exceptions : internal processor occurrences: i.e. division by 0, unknown op- code, page-fault (see later) etc. Software Interrupt : a processor can willingly trigger an internal interrupt interrupt (for instance for initiating an OS service). There are specific instructions for this purpose.

24 24 Vectored interrupts Interrupt 0 pointer Interrupt 1 pointer Interrupt n pointer Each interrupt must be associated to a number (n: interrupt type – one byte - value ) which through a table residing in memory(Interrupt Vector Table) indicates the address of the first instruction of its interrupts handler. Upon an interrupt the CPU: 1)Inhibits the Interrupt Enable (no further interrupts allowed until explicit program command) 2)Reads n from the external device which has activated the highest priority signal interrupt and multiplies it by 4 (a pointer is 4 bytes long – CS:IP) 3)Saves on the stack the return address and the flags (three 16 bit words). 4)Jumps through the IVT to the interrupts handler 5)When the interrupt handler is completed (RTI instruction) interrupts are enabled again Interrupt Vector Table Memory address 0

25 25 n - INT TYPE ALE INTA* AD0-AD7 ALE for READY The first INTA* cycle freezes the interrupt situation 8086 Interrupts 8086 IR0 IR1 IR2 IRk (IRi or) Inta* Int Inta* n External interrupts Priority Network

26 26 i.e. INT TYPE b = 10h = 16d 68 Interrupt vector n. 16 (16x4)= CS8-CS15 CS0-CS7 IP8-IP15 IP0-IP interrupts N.B. stack downward oriented

27 27 PIC (Programmable Interrupt Controller) 8259 CS* A0 WR* RD* D0-7 CAS0-2 INT INTA* SP/EN* IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Up to 8 interrupt requests (IR0..IR7) which can be extended to 64 by a cascaded device 8259 INT/INTA* pins are connected to the same pins of the CPU provides the interrupt type during the second INTA* pulse (IRi) can be either positive edge or level Two IO address locations (A0). Notice that the addressing in the I/O space in 16 LSB only and the addressing mechanism is the same of the memory (but for IO/M pin) Interrupts can be masked and prioritized Like Memories For internal address

28 28 Priority resolution INT D0...D7 (Data pin connected through the bus to the CPU data pins) n IRi INTA* The PIC “freezes” the interrupt requests: non further requests are accepted until after the second INTA* The PIC, according to the freezed requests, provides the interrupt type associated to the max priority request

29 29 IR handling The basic 8259 behaviour allows an interrupt of higher priority to interrupt the handling of a lower priority interrupt (fully nested interrupts) provided the processor Interrupt Enable is «on». A further request on the same level is in any case inhibited until the service routine of this level is completed (which means. All IRi can be selectively masked Priority Resolution I M R I S R IRRIRR INT INTA* IR0 IR1 IR7 IMR: Interrupt Mask Register IRR: Interrupt Request Register (needed for rdge triggered interrupts) ISR: In-Service Register When the i-th request is serviced (its interrupt handler is started) the corresponding bit is set in ISR EOI (End of Interrupt) command: issued at the end of an interrupt handler to reset the corresponding ISR bit. Notice: a «command» is a byte sent to a specific address of PIC which is interpreted by the PIC as a command (see the generic interface slides)

30 30 Programmazione del PIC 8259 (1) 1=level 0=edge 1=single 0=cascaded 1 con 8086/88 ICW1 A XXX1LTIMXSNGLICW ICW4 A0 1 BUFM/SAEOISFNM =Special Fully Nested Mode 0=Normal Mode 1=AEOI 0=Norm.EOI 0 X ICW2 5 interrupt type MSbits A0 T3XXXT4T5T6T No ICW3 ?

31 PIC programming (2) A0 OCW M3M2M1M0M4M5M6M7 INTERRUPT MASK 0=RESET; 1=SET A0 OCW2 0 0L2L1L00EOISLH Livello interessato Specific EOI [lev] Non specific EOI Rotation on non specific EOI Rotation on AEOI (set) Rotation on AEOI (reset) Rotation on specific EOI [lev] Set priority [lev ] NOP Rotation => Priority rotation Lev => interrupt level upon which the operation is performed

32 32 PIC 8259 Priority (2) ISR Priority When ROTATE on specific EOI and then EOI specific (on level 3) we have the following situation Priority modification only upon ROTATION ISR Priority

33 33 Q* D CK INTREQ RESET* CL Q "1" I/O command IRi I.e. too narrow pulse Edge-level transformation

34 parallel interface Device implementing a programmable interface of three independent 8 bit bidirectional (input or output) parallel ports. Each port has 3 programmable possible behaviours CS* WR* RD* A0 A1 RESET D0 - D7 PA0-PA7 PB0-PB7 PC0-PC The interface has 4 internal registers for data and commands Ports

35 35 Internal registers Port A, B or C data read if selectively programmed as input ports Control register read Port A, B or C data write if selectively programmed as output ports. Control register write Inteface Programming

36 36 Behaviours All three ports (A, B, C) can be programmed Mode 0. Only ports can be programmed Mode 1. If port A is programmed Mode 1 the signals for the handshake (see next slides) are provided by pins PC7-PC4. If port B is programmed Mode 1 the signals for the handshake (see next slides) are provided by pins PC3-PC0. Mode 0: Basic Input/Output La CPU legge/scrive sulla porta senza alcun meccanismo di sincronizzazione con l’Unità Esterna ad essa connessa. Sono presenti dei latch sulle uscite ma non sugli ingressi. Modo 1: Strobed Input/Output La CPU legge/scrive sulla porta sincronizzandosi con l’Unità Esterna mediante un protocollo ad “handshake”. L’operazione di I/O può essere gestita sia a “interrupt” sia a “polling”. Sono presenti dei latch sia sulle uscite sia sugli ingressi. Modo 2: not examined

37 37 Control Word For instance: if port B must be programmed as mode 1-output, the free pins of the port C (lower) as inputs, port A mode 0-input and the pins of port C (upper) as outputs: ( 95H )

38 38 Set/Reset of port C bits

39 39 Mode 0 CS*,A1,A0 RD* INPUT D0-D7 WR* CS*,A1,A0 OUTPUT Input Output

40 40

41 41 Mode 1: “handshake” Strobed Input The peripheral must write its data in the input latch of port (A or B) through STB* (strobe) then signals to the CPU and the peripheral that the data was accepted activating IBF (Input Buffer Full). The 8255 activates the INTR (Interrupt Request): CPU will then read the written when. Upon CPU read IBF will be reset for a further transfer from the peripheral ACK* DATA_OUT OBF* 8255 STB* DATA_IN IBF Peripheral 8 INTR Strobed Output INTR Upon INTR activation the CPU writed the data on the latch output port (A or B); 8255 signals to the peripheral and the CPU that new data are ready activating OBF* (Output Buffer Full). The peripheral read then the data through ACK* (acknowledge) upon whihc INTR is set again Peripheral

42 42 Strobed Input : waveforms BD0: PA0:7 (PB0:7) Peripheral STB* IBF PC5 (1) PC4 (2) PC3 (0) RD* INTR CPU STB* IBF INTR RD* PA0:7 (PB0:7)

43 43 Strobed Output : waveforms BD0: PA0:7 (PB0:7) ACK* OBF* PC7 (1) PC6 (2) PC3 (0) WR* INTR CPU WR* INTR OBF* ACK* Peripheral PA0:7 (PB0:7)

44 44

45 45 Direct Memory Access Bus Transfers controlled by an external agent HOLD freezes the microprocesso which tristates RD*, WR*, INTA*, IO/M* The microprocessor bus controller must be therefore completely substituted

46 46 82(C)37 IORD* IOWR* MEMRD* MEMWR* READY HOLD HLDA AEN ADSTB CS* CLK RESET D0-7 A0-7 DREQ0 DACK0 DREQ1 DACK1 DREQ2 DACK2 DREQ3 DACK3 EOP*

47 47 Timing clock S0 S1 S2 S3 S4S0 HOLD/HOLDA AEN ADSTB DO-D7 (address) A0-A7 DACK IORD*-MEMWR* IOWR*-MEMRD*

48 48 CS* IORD* IOWR* D0-7 I/O device CS* MEMRD* MEMWR* D0-7 IORD* IOWR* MEMRD* MEMWR* DACK ADDR0-15 DMA Controller /244 EN* HOLDA DECODER DATA & CONTR. The DMA controller issues only memory addresses I/O and MEMORY commands simultaneous Memory Fly-by

49 49 DMA - FLY-BY CS_PERIPH = f(BADR0-15) * HOLDA! + DACKi * (HOLDA) (NB: HOLDA in the second term is implied by DACKi and then unnecessary CS_MEM = f(BADR0-19) * HOLDA! + f(BADR0-15) * DACKi Some DMA controllers do not provide fly-by mode. In this case the transfer is perfermed in two phases: first the data are read into a DMA controller register then the data are transferred to the destination Processor generated DMA controller generated Ai_PERIPH = BADRi * HOLDA! + Xi * DACKi Xi indicates the port or register of the transfer Processor generated

50 50 An example 8088 MEM 8255 DMA CNTR IOWR,DACK0 MEMRD DREQ0 INTb (78H) (0-64K) HOLD HOLDA Port B mode 1 DMA 0 channel Single memory chip CSmem = BADR19! *BADR18! *BADR17! *BADR16! *HOLDA! + DACK0 = BADR19! *BADR18! *BADR17! *BADR16! + DACK0 ; (Only one memory device and therefore its CS coincides with DACKi) CS8255 = Decod(78H)*HOLDA!+DACK0 = Decod(78H) + DACK0 ; A08255 = BADR0*HOLDA! + 1*DACK0 = BADR0*HOLDA! + DACK0 = BADR0 + DACK0 ; (Port B -> A0=1, A1=0) A18255 = BADR1*HOLDA! + 0*DACK0 = BADR1*HOLDA!

51 51 FLOW-THROUGH CS* IORD* IOWR* D0-7 I/O DEVICE CS* MEMRD* MEMWR* D0-7 IORD* IOWR* MEMRD* MEMWR* ADDR0-15 D0-7 DMA CNTR /244 EN* HOLDA DECODER DATA and CONTR Two successive cycles: one for MEM and one for I/O ……….. Temporary register Memory - I/O MEMORY DEVICE

52 52 FLOW-THROUGH CS* MEMRD* MEMWR* D0-7 MEMORY DEVICE 64 K D0-7 MEMRD* MEMWR* ADDR0-15 DMA CNTR /244 EN* HOLDA DECODER DATA and CONTR DMA addresses only memory Two successive MEMORY transfers Memory to memory

53 53 Behaviour In case of transfers between MEMORY and I/O the addressing cycle takes place every 256 transfers In case of MEMORY-MEMORy twice per cycle (source and destination) EOP* signal (bidirectional) indicates the end of a channel program IOWR*(MEMWR*) EOP* It can be sent directly to a 8259 (edge sensitive )

54 54 Single transfer mode After each transfer the bus is temporarily released at least for one cycle Demand mode Uninterrupted transfers until DREQ active Block mode Once the channel program is started it goes uninterrupted until its end Cascade mode Not analysed here Behaviour

55 55 CONTROL WORD COMMAND REGISTER MEM/MEM ENABLE CHAN. 0 HOLD ADDRESS CONTROLLER ENABLE COMPRESSED TIMING FIXED/ROT. PRIORITY LATE/EXT. WRITE DREQ HI/LO DACK HI/LO

56 56 Mode register MODE REGISTER CHANNEL X SELECT 00 (VERIFIY) 01 WRITE (TO MEM) 10 READ (FROM MEM) 11 ILLEGALE XX SE CASCADE MODE 0 AUTOINIT DISABLE 1 AUTOINIT ENABLE 0 AUTOINCR 1 AUTODECR 00 DEMAND 01 SINGLE 10 BLOCK 11 CASCADE

57 57 Request Register REQUEST REGISTER CHANNEL X SELECT 0 RESET REQUEST 1 SET REQUEST DON'T CARE

58 58 Control words MASK REGISTER 1 CHAN. SEL MASK BIT DON'T CARE MASK REGISTER 2 CHAN 0 CHAN 1 CHAN 2 CHAN 3

59 59 Status word STATUS WORD CHANNEL TC CHANNEL REQ

60 60 EOP* Open Drain STOP* INT EOP 8237 EOP* EXT EOP VCC 4K7

61 61 Internal Registers A3 A2 A1 A0 IOR* IOW* Read status register Write command register Illegale Write request register Illegale Write mask register Illegale Write mode register Illegale Clear byte flip flop Read temporary register Master clear Illegale Clear mask register Illegale Write mask register 2 Addresses with A3 =1 => control

62 62 Addresses A3 A2 A1 A Base/current word addr. Ch Base/current word count Ch Base/current word addr. Ch Base/current word count Ch Base/current word addr. Ch Base/current word count Ch Base/current word addr. Ch Base/current word count Ch. 3 Addresses with A3 =o => data registers


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