5Segments Stack Segment FFFFF Word oriented Sstack 00000 Data Segment X+2XPopX-2StackSegmentPushSP (offset)Word oriented SstackBP (offset)SSSegmentbase addressThe stack grows downwardsThe BP is mainly used to address the stack segment as a memory data segmentCodeSegmentIP (offset)CS00000
6FLAGS 8 10 9 11 7 6 TF DF IF OF SF ZF 4 2 AF PF CF Zero Sign Overflow Int. en.DirectionTrap42AFPFCFCarryParityAux. carry
78086 characteristics Address space: 1 MB Segmented memory Used segment: depends from the executed instructionPartitioningRelocationProtection16 bit (offset) instructionsSegment changes are rare (locality principle)Relocatable codeStack: word orientedTwo operands instructions (i.e.mov AX,Mi)
10DYNAMIC RELOCATION CODE CS CS EXTRA DS DS SS SS CODE STACK ES ES DATA
11Address construction S + [(B + I + O) mod 64K] 16SEGMENT(0)CS/DS/ES/SSBASE16BP/BX16INDICESI/DI16Modul 64K sum !!!!!!Each segment is therefore maximum 64K !OFFSETS + [(B + I + O) mod 64K]Effective address 20 bits
12Address construction DISPL EFFECT. ADDR. DIRECT OPCODE MOD OPCODE MOD BASEDBX/BPEFFECT. ADDR.OPCODEMODDISPLINDEXEDSI/DIEFFECT. ADDR.
13Address construction BASED INDEXED INDIRECT OPCODE MOD DISPL SI/DI BX/BPEFFECT. ADDR.OPCODEMODINDIRECTBX/BP/SI/DIEFFECT. ADDR.
158086 (read) bus cycle BUS CYCLE CLOCK T1 T2 T3 T4 AD0-AD19 ALE IO/M* AddressData in8086 (read) bus cycleALEIO/M*Memory: low, I/O: highRD*DT/R*DEN*
168086 (write) bus cycles BUS CYCLE CLOCK T1 T2 T3 T4 A16-A19 AD0-AD15 AddressStatusAD0-AD15AddressData out8086 (write) bus cyclesALEIO/M*Memory: low, I/O: highWR*DT/R*DEN*
17Demultiplexed bus 8088 7 3 3 7 2 4 5 ALE 4 BA [0:19] A[16:19] 16 CKALE4BA [0:19]A[16:19]73716(Address bus)AD[0:15]3OE*8088Vcc16MN/MAX*245BD[0:15)EN*(Data bus)DEN*DT/R*DIRTo avoid bus conflicts
18Readysignal BUS CYCLE CLOCK T1 T2 T3 TW TW TW T4 ALE A16-A19 AD0-AD15 AddressStatusAD0-AD15AddressData inRD*READY
19I/O interfacing I/O INTERFACE Standard CPU Specific periheral CommandBusAddressBusDataBusI/OINTERFACEI/O peripheralD[0:7]CS*SignalsRD*WR*A[0:n-1]Standard CPUinterfaceSpecific periheralinterfaceAn interface adapts the system bus to the peripheral bus
20I/O Interfaces Data Buffer Within the interface there are data buffers where transferred data (input or output) are temporarily stored for further forwarding to the destination (CPU or peripheral). Data Buffer are addressed as memory cells (either with I/O or memory instructions)Control RegistersWithin an interface there are several control registers addressed as memory cells (either with I/O or memory instructions) which instruct (program) the interface logical network on how it must behave to perform the interfacingSincronization and Status RegistersNormally the I/O peripherals work asincronously from the CPU. Therefore a synchronization mechanism must be implementedThere are therefore Status Registers addressed as memory cells (either with I/O or memory instructions) which indicate the status of the transfer (i.e. a new data from the peripheral has been stored in the data buffer or the peripheral has read the data provided by the CPU but also whether the peripheral is OK etc.)
21Generic I/O interface BufferIn BufferOut Status Control DEC Peripheral PortPeripheralDataBusAddressBusOE*BufferInCKCommandBusCKBufferOutOE*SignalsOE*StatusCKCKControlOE*RD*WR*123CS*EN*DECA B
22I/O interface for 16 bit bus An 8 bit interface can be connected on the high or low busIf on the low bus only even addresses can be used for addressing the interface. He contrary for the high bus An example: two different intefaces located (CS* !!) at addresses 78H (low bus) e 81H (high bus alto) each one having 4 registers (read or write) A,B,C and DProc.16 bitD08-D15D00-D07Per-2Per-1RegistersPer-1Per-2ABCD787A7C7EBLE* = A0BHE*81838587As for the memories CS* depends also from A0 e BHE*Easy extension to 4(DLX) or 8 busses systems
23InterruptsAn interrupt is an event which “breaks” the normal program flow. The processor must start an appropriate procedure (interrupt handler) which handles the event causing the interrupt. An example is the transfer of data from an A/D converter: as soon as a new conversion is ready the A/D converter sends a signal to the computer which in turn must send the appropriate signal to the interface to read the new data and store them in an internal buffer. After the end of the interrupt handler the interrupted program flow must be resumed. «Normal» interrupts can be inhibited and un-inhibited by a proper machine instructionInterrupt classes:Hardware Interrupt : interrupt like the one previously described. The hardware interrupts can be inhibited by mean of a programmable internal flag IEN (interrupt enable/disable). Obviously there can be multiple external devices each one generating one or more interrupts and the 8086 has only one common interrupt pin. The intterrupts sources must be therefore detectedExceptions : internal processor occurrences: i.e. division by 0, unknown op-code, page-fault (see later) etc.Software Interrupt : a processor can willingly trigger an internal interrupt interrupt (for instance for initiating an OS service). There are specific instructions for this purpose.
24Vectored interrupts Interrupt Vector Table Each interrupt must be associated to a number (n: interrupt type – one byte - value ) which through a table residing in memory(Interrupt Vector Table) indicates the address of the first instruction of its interrupts handler.Upon an interrupt the CPU:Inhibits the Interrupt Enable (no further interrupts allowed until explicit program command)Reads n from the external device which has activated the highest priority signal interrupt and multiplies it by 4 (a pointer is 4 bytes long – CS:IP)Saves on the stack the return address and the flags (three 16 bit words).Jumps through the IVT to the interrupts handlerWhen the interrupt handler is completed (RTI instruction) interrupts are enabled againInterruptVectorTableInterrupt n pointerInterrupt 1 pointerInterrupt 0 pointerMemory address 0
258086 Interrupts ALE INTA* AD0-AD7 n - INT TYPE n IR0 External interrupts8086IR1(IRi or)IntIR2Inta*Inta*PriorityNetworkIRknn - INT TYPEALEINTA*AD0-AD7ALE for READYThe first INTA* cycle freezes the interrupt situation
26N.B. stack downward oriented 8086 interruptsi.e. INT TYPE b = 10h = 16d68CS8-CS1567CS0-CS7Interrupt vector n. 16(16x4)=6466IP8-IP1565N.B. stack downward orientedIP0-IP764636261
27PIC (Programmable Interrupt Controller) 8259 For internal addressLike MemoriesCS*A0WR*RD*D0-7CAS0-2INTINTA*SP/EN*IR0IR1IR2IR3IR4IR5IR6IR7Up to 8 interrupt requests (IR0..IR7) which can be extended to 64 by a cascaded device8259 INT/INTA* pins are connected to the same pins of the CPU provides the interrupt type during the second INTA* pulse(IRi) can be either positive edge or levelTwo IO address locations (A0). Notice that the addressing in the I/O space in 16 LSB only and the addressing mechanism is the same of the memory (but for IO/M pin)Interrupts can be masked and prioritized
28Priority resolution IRi INT INTA* D0...D7 n (Data pin connected through the bus to the CPU data pins)nThe PIC “freezes” the interrupt requests: non further requests are accepted until after the second INTA*The PIC, according to the freezed requests, provides the interrupt type associated to the max priority request
29IR handling Priority Resolution I M R I INT R INTA* I S R The basic 8259 behaviour allows an interrupt of higher priority to interrupt the handling of a lower priority interrupt (fully nested interrupts) provided the processor Interrupt Enable is «on». A further request on the same level is in any case inhibited until the service routine of this level is completed (which means . All IRi can be selectively maskedI M RIMR: Interrupt Mask RegisterIR0PriorityResolutionIRIRR: Interrupt Request Register (needed for rdge triggered interrupts)IR1INTINTA*ISR: In-Service RegisterWhen the i-th request is serviced (its interrupt handler is started) the corresponding bit is set in ISRIR7I S REOI (End of Interrupt) command: issued at the end of an interrupt handler to reset the corresponding ISR bit.Notice: a «command» is a byte sent to a specific address of PIC which is interpreted by the PIC as a command (see the generic interface slides)
30Programmazione del PIC 8259 (1) ICW1A0XXX1LTIMXSNGLICW41=level1=single0=edge0=cascadedProgrammazione del PIC 8259 (1)1 con 8086/88ICW2A01T7T6T5T4T3XXX5 interrupt type MSbitsNo ICW3 ?ICW4A01SFNMBUFM/SAEOI11=AEOI0=Norm.EOI1=Special Fully Nested ModeX0=Normal Mode
318259 PIC programming (2) 7 6 5 4 3 2 1 0 OCW1 7 6 5 4 3 2 1 0 OCW2 A0 OCW11M7M6M5M4M3M2M1M0INTERRUPT MASK 0=RESET; 1=SETA0OCW2HSLEOIL2L1L0Livello interessatoNon specific EOISpecific EOI [lev]Rotation on non specific EOIRotation on AEOI (set)Rotation on AEOI (reset)Rotation on specific EOI [lev]Set priority [lev ]NOPRotation => Priority rotationLev => interrupt level upon which the operation is performed
32PIC 8259 Priority (2) 7 6 5 4 3 2 1 0 ISR Priority 7 6 5 4 3 2 1 0 ISR ISR11Priority7654321When ROTATE on specific EOI and then EOI specific (on level 3) we have the following situationISR1Priority2176543Priority modification only upon ROTATION
33Edge-level transformation "1"DQ*IRiINTREQCKQCLRESET*I/O commandI.e. too narrow pulse
348255 parallel interfaceDevice implementing a programmable interface of three independent 8 bit bidirectional (input or output) parallel ports. Each port has 3 programmable possible behavioursPorts8255CS*8PA0-PA7WR*RD*8PB0-PB7A0A18PC0-PC7RESETD0 - D78The interface has 4 internal registers for data and commands
35Internal registers Inteface Programming Port A, B or C data read if selectively programmed as input portsControl register readPort A, B or C data write if selectively programmed as output ports.Control register writeInteface Programming
36Behaviours Mode 0: Basic Input/Output Modo 1: Strobed Input/Output La CPU legge/scrive sulla porta senza alcun meccanismo di sincronizzazione con l’Unità Esterna ad essa connessa. Sono presenti dei latch sulle uscite ma non sugli ingressi.Modo 1: Strobed Input/OutputLa CPU legge/scrive sulla porta sincronizzandosi con l’Unità Esterna mediante un protocollo ad “handshake”. L’operazione di I/O può essere gestita sia a “interrupt” sia a “polling”. Sono presenti dei latch sia sulle uscite sia sugli ingressi.Modo 2: not examinedAll three ports (A, B, C) can be programmed Mode 0.Only ports can be programmed Mode 1.If port A is programmed Mode 1 the signals for the handshake (see next slides) are provided by pins PC7-PC4.If port B is programmed Mode 1 the signals for the handshake (see next slides) are provided by pins PC3-PC0.
37Control WordFor instance: if port B must be programmed as mode 1-output, the free pins of the port C (lower) as inputs, port A mode 0-input and the pins of port C (upper) as outputs:1111( 95H )
41Mode 1: “handshake” Strobed Input Strobed Output INTR STB* DATA_IN IBF 8Peripheral8255The peripheral must write its data in the input latch of port (A or B) through STB* (strobe) then signals to the CPU and the peripheral that the data was accepted activating IBF (Input Buffer Full). The 8255 activates the INTR (Interrupt Request): CPU will then read the written when . Upon CPU read IBF will be reset for a further transfer from the peripheralStrobed OutputINTRACK*DATA_OUTOBF*88255PeripheralUpon INTR activation the CPU writed the data on the latch output port (A or B); signals to the peripheral and the CPU that new data are ready activating OBF* (Output Buffer Full). The peripheral read then the data through ACK* (acknowledge) upon whihc INTR is set again
45Direct Memory Access Bus Transfers controlled by an external agent HOLD freezes the microprocesso which tristates RD*, WR*, INTA*, IO/M*The microprocessor bus controller must be therefore completely substituted
48Fly-by The DMA controller issues only memory addresses I/O deviceCS*IORD*IOWR*D0-78088245/244IORD*DATA&CONTR.IOWR*MEMRD*DMAControllerMEMWR*DACKEN*ADDR0-15HOLDACS*MEMRD*MEMWR*DECODERD0-7The DMA controller issues only memory addressesI/O and MEMORY commands simultaneousMemory
49DMA - FLY-BYCS_PERIPH = f(BADR0-15) * HOLDA! + DACKi * (HOLDA)(NB: HOLDA in the second term is implied by DACKi and then unnecessaryCS_MEM = f(BADR0-19) * HOLDA! + f(BADR0-15) * DACKiProcessor generatedDMA controller generatedAi_PERIPH = BADRi * HOLDA! + Xi * DACKiProcessor generatedXi indicates the port or register of the transferSome DMA controllers do not provide fly-by mode. In this case the transfer is perfermed in two phases: first the data are read into a DMA controller register then the data are transferred to the destination
50An example Port B mode 1 DMA 0 channel 8088 Single memory chip MEM DMA HOLDAMEMHOLD(0-64K)MEMRDDMACNTRIOWR,DACK08255(78H)DREQ0INTbCSmem = BADR19! *BADR18! *BADR17! *BADR16! *HOLDA! + DACK0 =BADR19! *BADR18! *BADR17! *BADR16! + DACK0 ;(Only one memory device and therefore its CS coincides with DACKi)CS8255 = Decod(78H)*HOLDA!+DACK0 = Decod(78H)+DACK0;A08255 = BADR0*HOLDA! + 1*DACK0 = BADR0*HOLDA! + DACK0 = BADR0 + DACK0 ;(Port B -> A0=1, A1=0)A18255 = BADR1*HOLDA! + 0*DACK0 = BADR1*HOLDA!
51FLOW-THROUGH Memory - I/O CS*IORD*IOWR*D0-78088245/244I/O DEVICEIORD*DATAandCONTRIOWR*MEMRD*MEMWR*EN*ADDR0-15D0-7HOLDADMA CNTRCS*MEMRD*MEMWR*DECODERD0-7Two successive cycles: one for MEM and one for I/O……….. Temporary registerMEMORY DEVICE
52FLOW-THROUGH Memory to memory DMA addresses only memory 8088245/244DATAandCONTRD0-7MEMRD*MEMWR*ADDR0-15EN*HOLDADMA CNTRCS*MEMRD*MEMWR*D0-7DECODERDMA addresses only memoryMEMORY DEVICE 64 KTwo successive MEMORY transfers
53Behaviour IOWR*(MEMWR*) EOP* In case of transfers between MEMORY and I/O the addressing cycle takes place every 256 transfersIn case of MEMORY-MEMORy twice per cycle (source and destination)EOP* signal (bidirectional) indicates the end of a channel programIOWR*(MEMWR*)EOP*It can be sent directly to a 8259 (edge sensitive )
54Behaviour Single transfer mode After each transfer the bus is temporarily released at least for one cycleDemand modeUninterrupted transfers until DREQ activeBlock modeOnce the channel program is started it goes uninterrupted until its endCascade modeNot analysed here
62Addresses A3 A2 A1 A0 0 0 0 0 Base/current word addr. Ch. 0 Base/current word count Ch. 0Base/current word addr. Ch. 1Base/current word count Ch. 1Base/current word addr. Ch. 2Base/current word count Ch. 2Base/current word addr. Ch. 3Base/current word count Ch. 3Addresses with A3 =o => data registers