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Electronic Computers M

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1 Electronic Computers M
8086 Electronic Computers M

2 CPU “Logic” pinout of 8086 Int/Inta* Command bus Address bus
Hold/Holda DMA Data bus Reset Clock Ready

3 8086 (segmented !) Registers
SEGMENTS CS DS SS ES ACCUMULATORS AX AH AL BX BH BL CX CH CL DX DH DL All memory addresses in the IAx architectures are computed as offsets from a base address stored in a segment register

4 Registers BASE - STACK - INDEX SP BP SI DI IP FLAGSh FLAGSl

5 Segments Stack Segment FFFFF Word oriented Sstack 00000 Data Segment
X+2 X Pop X-2 Stack Segment Push SP (offset) Word oriented Sstack BP (offset) SS Segment base address The stack grows downwards The BP is mainly used to address the stack segment as a memory data segment Code Segment IP (offset) CS 00000

6 FLAGS 8 10 9 11 7 6 TF DF IF OF SF ZF 4 2 AF PF CF Zero Sign Overflow
Int. en. Direction Trap 4 2 AF PF CF Carry Parity Aux. carry

7 8086 characteristics Address space: 1 MB Segmented memory
Used segment: depends from the executed instruction Partitioning Relocation Protection 16 bit (offset) instructions Segment changes are rare (locality principle) Relocatable code Stack: word oriented Two operands instructions (i.e.mov AX,Mi)

8 SEGMENTS (Physical address = 5048B) OFFSET 000B BASE 5048 OFFSET 002B
50460:3 50460:2 BASE 5046 50460:1 50460:0

9 SEGMENTS FFFFF L M DS X X Y CS Y E Z SS Z O ES W K N 00000 W

10 DYNAMIC RELOCATION CODE CS CS EXTRA DS DS SS SS CODE STACK ES ES DATA

11 Address construction S + [(B + I + O) mod 64K]
16 SEGMENT (0) CS/DS/ES/SS BASE 16 BP/BX 16 INDICE SI/DI 16 Modul 64K sum !!!!!! Each segment is therefore maximum 64K ! OFFSET S + [(B + I + O) mod 64K] Effective address 20 bits

12 Address construction DISPL EFFECT. ADDR. DIRECT OPCODE MOD OPCODE MOD
BASED BX/BP EFFECT. ADDR. OPCODE MOD DISPL INDEXED SI/DI EFFECT. ADDR.

13 Address construction BASED INDEXED INDIRECT OPCODE MOD DISPL SI/DI
BX/BP EFFECT. ADDR. OPCODE MOD INDIRECT BX/BP/SI/DI EFFECT. ADDR.

14 BIU-EU Internal registers Temporary regs. Instruction queue AX BX CX S
DX SP BP DI CS CS SI DS DS SS SS ES ES IP IP Internal registers Internal BUS control Temporary regs. Instruction queue EU control ALU 4 bytes 8088 FLAGS EU BIU

15 8086 (read) bus cycle BUS CYCLE CLOCK T1 T2 T3 T4 AD0-AD19 ALE IO/M*
Address Data in 8086 (read) bus cycle ALE IO/M* Memory: low, I/O: high RD* DT/R* DEN*

16 8086 (write) bus cycles BUS CYCLE CLOCK T1 T2 T3 T4 A16-A19 AD0-AD15
Address Status AD0-AD15 Address Data out 8086 (write) bus cycles ALE IO/M* Memory: low, I/O: high WR* DT/R* DEN*

17 Demultiplexed bus 8088 7 3 3 7 2 4 5 ALE 4 BA [0:19] A[16:19] 16
CK ALE 4 BA [0:19] A[16:19] 7 3 7 16 (Address bus) AD[0:15] 3 OE* 8088 Vcc 16 MN/MAX* 2 4 5 BD[0:15) E N * (Data bus) DEN* DT/R* DIR To avoid bus conflicts

18 Readysignal BUS CYCLE CLOCK T1 T2 T3 TW TW TW T4 ALE A16-A19 AD0-AD15
Address Status AD0-AD15 Address Data in RD* READY

19 I/O interfacing I/O INTERFACE Standard CPU Specific periheral
Command Bus Address Bus Data Bus I/O INTERFACE I/O peripheral D[0:7] CS* Signals RD* WR* A[0:n-1] Standard CPU interface Specific periheral interface An interface adapts the system bus to the peripheral bus

20 I/O Interfaces Data Buffer
Within the interface there are data buffers where transferred data (input or output) are temporarily stored for further forwarding to the destination (CPU or peripheral). Data Buffer are addressed as memory cells (either with I/O or memory instructions) Control Registers Within an interface there are several control registers addressed as memory cells (either with I/O or memory instructions) which instruct (program) the interface logical network on how it must behave to perform the interfacing Sincronization and Status Registers Normally the I/O peripherals work asincronously from the CPU. Therefore a synchronization mechanism must be implemented There are therefore Status Registers addressed as memory cells (either with I/O or memory instructions) which indicate the status of the transfer (i.e. a new data from the peripheral has been stored in the data buffer or the peripheral has read the data provided by the CPU but also whether the peripheral is OK etc.)

21 Generic I/O interface BufferIn BufferOut Status Control DEC Peripheral
Port Peripheral Data Bus Address Bus OE* BufferIn CK Command Bus CK BufferOut OE* Signals OE* Status CK CK Control OE* RD* WR* 1 2 3 CS* EN* DEC A B

22 I/O interface for 16 bit bus
An 8 bit interface can be connected on the high or low bus If on the low bus only even addresses can be used for addressing the interface. He contrary for the high bus An example: two different intefaces located (CS* !!) at addresses 78H (low bus) e 81H (high bus alto) each one having 4 registers (read or write) A,B,C and D Proc. 16 bit D08-D15 D00-D07 Per-2 Per-1 Registers Per-1 Per-2 A B C D 78 7A 7C 7E BLE* = A0 BHE* 81 83 85 87 As for the memories CS* depends also from A0 e BHE* Easy extension to 4(DLX) or 8 busses systems

23 Interrupts An interrupt is an event which “breaks” the normal program flow. The processor must start an appropriate procedure (interrupt handler) which handles the event causing the interrupt. An example is the transfer of data from an A/D converter: as soon as a new conversion is ready the A/D converter sends a signal to the computer which in turn must send the appropriate signal to the interface to read the new data and store them in an internal buffer. After the end of the interrupt handler the interrupted program flow must be resumed. «Normal» interrupts can be inhibited and un-inhibited by a proper machine instruction Interrupt classes: Hardware Interrupt : interrupt like the one previously described. The hardware interrupts can be inhibited by mean of a programmable internal flag IEN (interrupt enable/disable). Obviously there can be multiple external devices each one generating one or more interrupts and the 8086 has only one common interrupt pin. The intterrupts sources must be therefore detected Exceptions : internal processor occurrences: i.e. division by 0, unknown op-code, page-fault (see later) etc. Software Interrupt : a processor can willingly trigger an internal interrupt interrupt (for instance for initiating an OS service). There are specific instructions for this purpose.

24 Vectored interrupts Interrupt Vector Table
Each interrupt must be associated to a number (n: interrupt type – one byte - value ) which through a table residing in memory(Interrupt Vector Table) indicates the address of the first instruction of its interrupts handler. Upon an interrupt the CPU: Inhibits the Interrupt Enable (no further interrupts allowed until explicit program command) Reads n from the external device which has activated the highest priority signal interrupt and multiplies it by 4 (a pointer is 4 bytes long – CS:IP) Saves on the stack the return address and the flags (three 16 bit words). Jumps through the IVT to the interrupts handler When the interrupt handler is completed (RTI instruction) interrupts are enabled again Interrupt Vector Table Interrupt n pointer Interrupt 1 pointer Interrupt 0 pointer Memory address 0

25 8086 Interrupts ALE INTA* AD0-AD7 n - INT TYPE n IR0
External interrupts 8086 IR1 (IRi or) Int IR2 Inta* Inta* Priority Network IRk n n - INT TYPE ALE INTA* AD0-AD7 ALE for READY The first INTA* cycle freezes the interrupt situation

26 N.B. stack downward oriented
8086 interrupts i.e. INT TYPE b = 10h = 16d 68 CS8-CS15 67 CS0-CS7 Interrupt vector n. 16 (16x4)=64 66 IP8-IP15 65 N.B. stack downward oriented IP0-IP7 64 63 62 61

27 PIC (Programmable Interrupt Controller) 8259
For internal address Like Memories CS* A0 WR* RD* D0-7 CAS0-2 INT INTA* SP/EN* IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Up to 8 interrupt requests (IR0..IR7) which can be extended to 64 by a cascaded device 8259 INT/INTA* pins are connected to the same pins of the CPU provides the interrupt type during the second INTA* pulse (IRi) can be either positive edge or level Two IO address locations (A0). Notice that the addressing in the I/O space in 16 LSB only and the addressing mechanism is the same of the memory (but for IO/M pin) Interrupts can be masked and prioritized

28 Priority resolution IRi INT INTA* D0...D7 n
(Data pin connected through the bus to the CPU data pins) n The PIC “freezes” the interrupt requests: non further requests are accepted until after the second INTA* The PIC, according to the freezed requests, provides the interrupt type associated to the max priority request

29 IR handling Priority Resolution I M R I INT R INTA* I S R
The basic 8259 behaviour allows an interrupt of higher priority to interrupt the handling of a lower priority interrupt (fully nested interrupts) provided the processor Interrupt Enable is «on». A further request on the same level is in any case inhibited until the service routine of this level is completed (which means . All IRi can be selectively masked I M R IMR: Interrupt Mask Register IR0 Priority Resolution I R IRR: Interrupt Request Register (needed for rdge triggered interrupts) IR1 INT INTA* ISR: In-Service Register When the i-th request is serviced (its interrupt handler is started) the corresponding bit is set in ISR IR7 I S R EOI (End of Interrupt) command: issued at the end of an interrupt handler to reset the corresponding ISR bit. Notice: a «command» is a byte sent to a specific address of PIC which is interpreted by the PIC as a command (see the generic interface slides)

30 Programmazione del PIC 8259 (1)
ICW1 A0 X X X 1 LTIM X SNGL ICW4 1=level 1=single 0=edge 0=cascaded Programmazione del PIC 8259 (1) 1 con 8086/88 ICW2 A0 1 T7 T6 T5 T4 T3 X X X 5 interrupt type MSbits No ICW3 ? ICW4 A0 1 SFNM BUF M/S AEOI 1 1=AEOI 0=Norm.EOI 1=Special Fully Nested Mode X 0=Normal Mode

31 8259 PIC programming (2) 7 6 5 4 3 2 1 0 OCW1 7 6 5 4 3 2 1 0 OCW2 A0
OCW1 1 M7 M6 M5 M4 M3 M2 M1 M0 INTERRUPT MASK 0=RESET; 1=SET A0 OCW2 H SL EOI L2 L1 L0 Livello interessato Non specific EOI Specific EOI [lev] Rotation on non specific EOI Rotation on AEOI (set) Rotation on AEOI (reset) Rotation on specific EOI [lev] Set priority [lev ] NOP Rotation => Priority rotation Lev => interrupt level upon which the operation is performed

32 PIC 8259 Priority (2) 7 6 5 4 3 2 1 0 ISR Priority 7 6 5 4 3 2 1 0 ISR
ISR 1 1 Priority 7 6 5 4 3 2 1 When ROTATE on specific EOI and then EOI specific (on level 3) we have the following situation ISR 1 Priority 2 1 7 6 5 4 3 Priority modification only upon ROTATION

33 Edge-level transformation
"1" D Q* IRi INTREQ CK Q CL RESET* I/O command I.e. too narrow pulse

34 8255 parallel interface Device implementing a programmable interface of three independent 8 bit bidirectional (input or output) parallel ports. Each port has 3 programmable possible behaviours Ports 8255 CS* 8 PA0-PA7 WR* RD* 8 PB0-PB7 A0 A1 8 PC0-PC7 RESET D0 - D7 8 The interface has 4 internal registers for data and commands

35 Internal registers Inteface Programming
Port A, B or C data read if selectively programmed as input ports Control register read Port A, B or C data write if selectively programmed as output ports . Control register write Inteface Programming

36 Behaviours Mode 0: Basic Input/Output Modo 1: Strobed Input/Output
La CPU legge/scrive sulla porta senza alcun meccanismo di sincronizzazione con l’Unità Esterna ad essa connessa. Sono presenti dei latch sulle uscite ma non sugli ingressi. Modo 1: Strobed Input/Output La CPU legge/scrive sulla porta sincronizzandosi con l’Unità Esterna mediante un protocollo ad “handshake”. L’operazione di I/O può essere gestita sia a “interrupt” sia a “polling”. Sono presenti dei latch sia sulle uscite sia sugli ingressi. Modo 2: not examined All three ports (A, B, C) can be programmed Mode 0. Only ports can be programmed Mode 1. If port A is programmed Mode 1 the signals for the handshake (see next slides) are provided by pins PC7-PC4. If port B is programmed Mode 1 the signals for the handshake (see next slides) are provided by pins PC3-PC0.

37 Control Word For instance: if port B must be programmed as mode 1-output, the free pins of the port C (lower) as inputs, port A mode 0-input and the pins of port C (upper) as outputs: 1 1 1 1 ( 95H )

38 Set/Reset of port C bits

39 Mode 0 CS*,A1,A0 RD* INPUT D0-D7 CS*,A1,A0 WR* D0-D7 OUTPUT Input

40

41 Mode 1: “handshake” Strobed Input Strobed Output INTR STB* DATA_IN IBF
8 Peripheral 8255 The peripheral must write its data in the input latch of port (A or B) through STB* (strobe) then signals to the CPU and the peripheral that the data was accepted activating IBF (Input Buffer Full). The 8255 activates the INTR (Interrupt Request): CPU will then read the written when . Upon CPU read IBF will be reset for a further transfer from the peripheral Strobed Output INTR ACK* DATA_OUT OBF* 8 8255 Peripheral Upon INTR activation the CPU writed the data on the latch output port (A or B); signals to the peripheral and the CPU that new data are ready activating OBF* (Output Buffer Full). The peripheral read then the data through ACK* (acknowledge) upon whihc INTR is set again

42 Strobed Input : waveforms
PA0:7 (PB0:7) 8255 BD0:7 Peripheral INTR IBF CPU PC3 (0) PC5 (1) RD* STB* PC4 (2) STB* IBF INTR RD* PA0:7 (PB0:7)

43 Strobed Output : waveforms
8255 PA0:7 (PB0:7) BD0:7 Peripheral INTR OBF* CPU PC3 (0) PC7 (1) WR* ACK* PC6 (2) WR* INTR OBF* ACK* PA0:7 (PB0:7)

44

45 Direct Memory Access Bus Transfers controlled by an external agent
HOLD freezes the microprocesso which tristates RD*, WR*, INTA*, IO/M* The microprocessor bus controller must be therefore completely substituted

46 82(C)37 IORD* IOWR* MEMRD* DREQ0 MEMWR* DACK0 READY DREQ1 HOLD DACK1
HLDA DREQ2 AEN DACK2 ADSTB DREQ3 CS* DACK3 CLK EOP* RESET D0-7 A0-7

47 Timing S0 S1 S2 S3 S4 S0 clock HOLD/HOLDA AEN ADSTB DO-D7 (address)
DACK IORD*-MEMWR* IOWR*-MEMRD*

48 Fly-by The DMA controller issues only memory addresses
I/O device CS* IORD* IOWR* D0-7 8088 245/244 IORD* DATA & CONTR. IOWR* MEMRD* DMA Controller MEMWR* DACK EN* ADDR0-15 HOLDA CS* MEMRD* MEMWR* DECODER D0-7 The DMA controller issues only memory addresses I/O and MEMORY commands simultaneous Memory

49 DMA - FLY-BY CS_PERIPH = f(BADR0-15) * HOLDA! + DACKi * (HOLDA) (NB: HOLDA in the second term is implied by DACKi and then unnecessary CS_MEM = f(BADR0-19) * HOLDA! + f(BADR0-15) * DACKi Processor generated DMA controller generated Ai_PERIPH = BADRi * HOLDA! + Xi * DACKi Processor generated Xi indicates the port or register of the transfer Some DMA controllers do not provide fly-by mode. In this case the transfer is perfermed in two phases: first the data are read into a DMA controller register then the data are transferred to the destination

50 An example Port B mode 1 DMA 0 channel 8088 Single memory chip MEM DMA
HOLDA MEM HOLD (0-64K) MEMRD DMA CNTR IOWR,DACK0 8255 (78H) DREQ0 INTb CSmem = BADR19! *BADR18! *BADR17! *BADR16! *HOLDA! + DACK0 = BADR19! *BADR18! *BADR17! *BADR16! + DACK0 ; (Only one memory device and therefore its CS coincides with DACKi) CS8255 = Decod(78H)*HOLDA!+DACK0 = Decod(78H)+DACK0; A08255 = BADR0*HOLDA! + 1*DACK0 = BADR0*HOLDA! + DACK0 = BADR0 + DACK0 ; (Port B -> A0=1, A1=0) A18255 = BADR1*HOLDA! + 0*DACK0 = BADR1*HOLDA!

51 FLOW-THROUGH Memory - I/O
CS* IORD* IOWR* D0-7 8088 245/244 I/O DEVICE IORD* DATA and CONTR IOWR* MEMRD* MEMWR* EN* ADDR0-15 D0-7 HOLDA DMA CNTR CS* MEMRD* MEMWR* DECODER D0-7 Two successive cycles: one for MEM and one for I/O ……….. Temporary register MEMORY DEVICE

52 FLOW-THROUGH Memory to memory DMA addresses only memory
8088 245/244 DATA and CONTR D0-7 MEMRD* MEMWR* ADDR0-15 EN* HOLDA DMA CNTR CS* MEMRD* MEMWR* D0-7 DECODER DMA addresses only memory MEMORY DEVICE 64 K Two successive MEMORY transfers

53 Behaviour IOWR*(MEMWR*) EOP*
In case of transfers between MEMORY and I/O the addressing cycle takes place every 256 transfers In case of MEMORY-MEMORy twice per cycle (source and destination) EOP* signal (bidirectional) indicates the end of a channel program IOWR*(MEMWR*) EOP* It can be sent directly to a 8259 (edge sensitive )

54 Behaviour Single transfer mode
After each transfer the bus is temporarily released at least for one cycle Demand mode Uninterrupted transfers until DREQ active Block mode Once the channel program is started it goes uninterrupted until its end Cascade mode Not analysed here

55 CONTROL WORD 7 6 5 4 3 2 1 0 COMMAND REGISTER DACK MEM/MEM HI/LO
DACK MEM/MEM HI/LO ENABLE DREQ CHAN. 0 HOLD HI/LO ADDRESS LATE/EXT. CONTROLLER WRITE ENABLE FIXED/ROT. COMPRESSED PRIORITY TIMING

56 Mode register 7 6 5 4 3 2 1 0 MODE REGISTER 00 DEMAND CHANNEL X SELECT
00 DEMAND CHANNEL X 01 SINGLE SELECT 10 BLOCK 11 CASCADE 00 (VERIFIY) 01 WRITE (TO MEM) 10 READ (FROM MEM) 0 AUTOINCR 11 ILLEGALE 1 AUTODECR XX SE CASCADE MODE 0 AUTOINIT DISABLE 1 AUTOINIT ENABLE

57 Request Register 7 6 5 4 3 2 1 0 DON'T CARE REQUEST REGISTER CHANNEL X
CHANNEL X SELECT 0 RESET REQUEST 1 SET REQUEST DON'T CARE

58 Control words 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MASK REGISTER 1
CHAN. SEL MASK BIT MASK REGISTER 2 CHAN 0 DON'T CARE CHAN 1 CHAN 2 CHAN 3

59 Status word STATUS WORD CHANNEL REQ CHANNEL TC

60 EOP* Open Drain 8237 VCC STOP* 4K7 EOP* INT EOP EXT EOP

61 Internal Registers A3 A2 A1 A0 IOR* IOW*
Read status register Write command register Illegale Write request register Illegale Write mask register Illegale Write mode register Illegale Clear byte flip flop Read temporary register Master clear Illegale Clear mask register 2 Illegale Write mask register 2 Addresses with A3 =1 => control

62 Addresses A3 A2 A1 A0 0 0 0 0 Base/current word addr. Ch. 0
Base/current word count Ch. 0 Base/current word addr. Ch. 1 Base/current word count Ch. 1 Base/current word addr. Ch. 2 Base/current word count Ch. 2 Base/current word addr. Ch. 3 Base/current word count Ch. 3 Addresses with A3 =o => data registers


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