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Courseware Introduction to Multiprocessor System-on-Chip Prof. Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard.

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Presentation on theme: "Courseware Introduction to Multiprocessor System-on-Chip Prof. Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard."— Presentation transcript:

1 courseware Introduction to Multiprocessor System-on-Chip Prof. Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard Petersens Plads, Building 321 DK2800 Lyngby, Denmark

2 SoC-MOBINET courseware(c) Jan Madsen2 Embedded systems CPU mem rom if... then...else... for {.....} func io bit-pattern

3 SoC-MOBINET courseware(c) Jan Madsen3 Embedded systems  Systems which use a computer to perform a specific function, but are neither used nor perceived as a computer  They are embedded within larger electronic devices  Repeatedly carrying out a particular function  Often completely unrecognized by the device’s user

4 SoC-MOBINET courseware(c) Jan Madsen4 Embedded systems design hardwaresoftware validation hardware prototype software prototype Several design groups Separated validations Prototype realization hardware model software model Problems arise at a very late point in the design process

5 SoC-MOBINET courseware(c) Jan Madsen5 Principples of Codesign void UnitControl() { up = down = 0; open = 1; while (1) { while (req == floor); open = 0; if (req > floor) { up = 1;} else {down = 1;} while (req != floor); open = 1; delay(10); } void UnitControl() { up = down = 0; open = 1; while (1) { while (req == floor); open = 0; if (req > floor) { up = 1;} else {down = 1;} while (req != floor); open = 1; delay(10); } SW synthesis CPU ASIC HW synthesis Interface synthesis

6 SoC-MOBINET courseware(c) Jan Madsen6 Overview  Technology  Processors  IC fabric  Codesign for speed-up  component execution timing (SW and HW)  Building sub-system  Hardware/software partitioning  Building system  System-level issues of codesign

7 SoC-MOBINET courseware(c) Jan Madsen7 Software  Elements of computation  Store data  Transform data  Move data if... then...else... for {.....} func pe

8 SoC-MOBINET courseware(c) Jan Madsen8 Processor  Architecture components  Processing elements – transform data  Memories – store data  Interconnect – move data if... then...else... for {.....} func

9 SoC-MOBINET courseware(c) Jan Madsen9 Processor: General Purpose  Availability  Low cost (mass production)  Simple design flow  High flexibility if... then...else... for {.....} func inst memcontrollerdatapathdata mem func pc ir cu reg +/- *

10 SoC-MOBINET courseware(c) Jan Madsen10 Processor: General Purpose - example if... then...else... for {.....} func inst memcontrollerdatapathdata mem func pc ir cu reg +/- x = x + A[i] * p1 * A[i] p1 5 cycles

11 SoC-MOBINET courseware(c) Jan Madsen11 Processor: Custom (ASIC)  High performance  Low power  Complex design flow  No flexibility if... then...else... for {.....} func controllerdatapath cu +/- * + mem

12 SoC-MOBINET courseware(c) Jan Madsen12 Processor: Custom (ASIC) – example if... then...else... for {.....} func controllerdatapath cu +/- * + mem A[i] p1 x = x + A[i] * p11 cycle

13 SoC-MOBINET courseware(c) Jan Madsen13 Processor: Semicustom (ASIP)  Costumized datapath – 16, 8 or 4 bit  Optimized for particular class of programs - MACC  ”Simple” design flow  High flexibility if... then...else... for {.....} func inst memcontrollerdatapathdata mem func pc ir cu reg +/- + *

14 SoC-MOBINET courseware(c) Jan Madsen14 Processor: Semicustom - example if... then...else... for {.....} func inst memcontrollerdatapathdata mem func pc ir cu reg +/- + * p1 A[i] x = x + A[i] * p12 cycles

15 SoC-MOBINET courseware(c) Jan Madsen15 IC fabrics  IC is an interconnection of transistors following one of several possible styles – fabrics  The fabric defines how and when transistors are composed  ”the material of processors”  IC fabrics differ in terms of customizability and generality

16 SoC-MOBINET courseware(c) Jan Madsen16 IC fabrics: Custom  Exact implementation of processor components  High NRE cost – mask set ~ 1M$

17 SoC-MOBINET courseware(c) Jan Madsen17 IC fabrics: Semicustom  Several semicustom fabrics  Library of standard cells  Cell arrays (sea-of-gates)  Most processing steps are pre manufactured (high volume)

18 SoC-MOBINET courseware(c) Jan Madsen18 IC fabrics: Programmable  Set of interconnected modules  Set of modules programmed to implement different components  FPGA  Programmable logic modules, storage and interconnect

19 SoC-MOBINET courseware(c) Jan Madsen19 Chips: Implementing IC fabric

20 SoC-MOBINET courseware(c) Jan Madsen20 Hardware/software codesign?  Many possible mappings  Processor may not exist yet!  Exploring the design space  Need to estimate if... then...else... for {.....} func

21 SoC-MOBINET courseware(c) Jan Madsen21 Hardware/Software Codesign  Optimizing  Timing (high performance, hard deadlines)  Area (cost)  Power consumption  Flexibility  Reliability ...  We will focus on timing

22 SoC-MOBINET courseware(c) Jan Madsen22 Processing element timing  Execution path  Control data dependent  Input data dependent  Function implementation  Component architecture  Compiler or synthesis if... then...else... for {.....} func

23 SoC-MOBINET courseware(c) Jan Madsen23 Formal execution path timing analysis then... else {... } for {.....} if... b1b1 b3b3 b4b4 b2b2 b i basic block or program segment t pe (b i, pe j ) execution time of b i on processing element pe j c(b i )execution frequency of b i  worst/best case timing bounds )c(b,pe ) (bF,pe )t i I i   ( pe j t j

24 SoC-MOBINET courseware(c) Jan Madsen24 Formal execution path timing analysis then... b2b2,pe ) (b i t pe j ** model * * hardware * * software

25 SoC-MOBINET courseware(c) Jan Madsen25 Memory models  Access time  Control overhead  Burst access (packets)  Cache  hit/miss time overhead  Based on execution history PE D$I$ Flash RAM SDRAM

26 SoC-MOBINET courseware(c) Jan Madsen26 Advanced architectures  Modern high performance processors includes architectural features which complicates timing analysis  Dynamic instruction scheduling  Speculative execution  Though fast, it makes  the processor very power hungry  tight bounds on timing very difficult  Computation less predictable  Issues which are important for embedded systems

27 SoC-MOBINET courseware(c) Jan Madsen27 Building sub-systems  Initial codesign problem  Hardware/software partitioning  the LYCOS cosynthesis tool  Automatic partitioning from C (subset) and VHDL (single process)  Developed at DTU if... then...else... for {.....} func processorASIC

28 SoC-MOBINET courseware(c) Jan Madsen28 Hardware/Software partitioning if... then...else... for {.....} func CPUASIC 4 3 b1b1 b3b3 b4b4 b2b2 2 1 CPUASIC mapping

29 SoC-MOBINET courseware(c) Jan Madsen29 Architectural choices  Which processor should be selected and how fast should it be?  Which ASIC technology should be chosen and how fast should the ASIC be?  How large an ASIC can we afford and which functions should it execute?  How should the processor and ASIC communicate?

30 SoC-MOBINET courseware(c) Jan Madsen30 Partitioning Model  Determines granularity and simplifying assumptions w.r.t. communication, HW sharing, etc Specification BB Model SWHW

31 SoC-MOBINET courseware(c) Jan Madsen31 Estimation SWHW SW Estimator S a t S SW Lib t H Estimator HW Lib HW a H t C EstimatorLib Com C a

32 SoC-MOBINET courseware(c) Jan Madsen32 Process communication then... else { send(...); receive(...);... } for {.....} if... b1b1 b2b2 b3b3 b4b4 s(b i ) sent data in b i r(b i ) received data in b i c(b i ) execution frequency of b i Communication time s(b i ) and r(b i ) determined by  data volume  Data encoding  Communication protocol

33 SoC-MOBINET courseware(c) Jan Madsen33 Solving the Partitioning Problem SWHW Just try all combinations...

34 SoC-MOBINET courseware(c) Jan Madsen34 Solving the Partitioning Problem Knapsack Stuffing No communication interleaved exec. additive areas Parallel execution non-additive areas Interleaved communication additive areas Large scale linear/nonlinear integer programming Heuristics needed! SWHW SWHW SW

35 SoC-MOBINET courseware(c) Jan Madsen35 LYCOS Design Flow Partitioning Comm. Estim. HW Estim. SW Estim. HWSW AssemblerNetlistSW/HW Synthesis Comm. Synthesis Translate Specification SW Model Comm. HW Analysis RequireFunctional CDFG

36 SoC-MOBINET courseware(c) Jan Madsen36 Building Systems  Platform architectures are heterogeneous  Different processing element types  Different interconnection networks and communication protocols  Different memory types  Different scheduling and synchronization strategies M CoP M M PDSP M P

37 SoC-MOBINET courseware(c) Jan Madsen37 Managing HW platform complexity  Development of APIs to hide complexity from application programmer and improve portability  Specialized RTOS to control resource sharing and interfaces   Complex multi-level HW/SW architecture

38 SoC-MOBINET courseware(c) Jan Madsen38 Software architecture Bus RTOS CPU I/OInt Bus- CTRL Timer drivers RTOS-APIs Periphery Cache mem private shared Hardware Software HW/SW Plattform application ce 1 application pe 1

39 SoC-MOBINET courseware(c) Jan Madsen39 Platform design challenges  Integration  Design process integration  Heterogeneous component and language integration  Design space exploration and optimization  Verification

40 SoC-MOBINET courseware(c) Jan Madsen40 Complex run-time interdependencies  Run-time dependencies of independent components via communication  Influence on timing and power  Need to handle resource sharing  Process/task scheduling  Communication scheduling  Scheduling strategies (static, dynamic, time or priority driven) CoP PE

41 SoC-MOBINET courseware(c) Jan Madsen41 Interdependency example  Complex non-functional interdependencies  Periodic task executing on PE  Task writes to bus at the end of each periodic execution PE Short execution time  high bus load long execution time  low bus load Local decision on improving performance may impact the global system performance

42 SoC-MOBINET courseware(c) Jan Madsen42 System-on-Chip challenge processor memory io router

43 SoC-MOBINET courseware(c) Jan Madsen43 Network-on-Chip a b c d M M M  Multi-hop  Segmented communication  Concurrency  Multiple simultaneous communications

44 SoC-MOBINET courseware(c) Jan Madsen44 Network-on-Chip  Multi-hop  Segmented communication  Concurrency  Multiple simultaneous communications  Sharing  Quasi-simultaneous resource usage  Multiple communication events occupying some or all resources in an interleaved fashion a b c d M M M

45 SoC-MOBINET courseware(c) Jan Madsen45 System-on-Chip design abc 1 2 os 3 4 abc mapping L1L1 L2L2 L3L3 R1R1 R2R2 R3R3

46 SoC-MOBINET courseware(c) Jan Madsen46 platform designPlatform-based design New design paradigme... platform specification IP re-configure re-design Mapping

47 SoC-MOBINET courseware(c) Jan Madsen47


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