# Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add \$4 \$6 \$1... loop sub.

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Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add \$4 \$6 \$1... loop sub

Datorteknik DelayedBranch bild 2 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = B loopAdd

Datorteknik DelayedBranch bild 3 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = B loopAddsub

Datorteknik DelayedBranch bild 4 Delayed Branch - Throughput might decrease, (nop). - Assembler/Compiler dependent. + Keep critical path short

Datorteknik DelayedBranch bild 5 All problems solved now? NO, what will happen if........ bal loop add \$4 \$6 \$1 xor.... loop: sub..... j \$ra

Datorteknik DelayedBranch bild 6 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = > ADDR 0x00400000 bal loop bal loop ADDR 0x00400004

Datorteknik DelayedBranch bild 7 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = ADDR 0x00400000 bal loop > ADDR 0x00400004 add ADDR 0x00400004 bal loop add

Datorteknik DelayedBranch bild 8 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = ADDR 0x00400004 bal loop add ADDR 0x00400000 bal loop ADDR 0x00400004 add >loop: sub sub

Datorteknik DelayedBranch bild 9 Branch logic Sgn/Ze extend Zero ext. sub.. j \$ra ALU A B 31 0 4 + + = = = = ADDR 0x00400004 jr \$ra

Datorteknik DelayedBranch bild 10 Branch logic Sgn/Ze extend Zero ext. Oooh not again!!! ALU A B 31 0 4 + + = = = = 0x00400004 add

Datorteknik DelayedBranch bild 11 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 4 4 + + = = = = ADDR 0x00400004 ADDR 0x00400008 Continue at 0x00400008 bal loop add sub

Datorteknik DelayedBranch bild 12 Branch logic Sgn/Ze extend Zero ext. sub.. j \$ra ALU A B 31 0 4 + + = = = = ADDR 0x00400008 jr \$ra

Datorteknik DelayedBranch bild 13 All Hazards Fixed but: One “delayed branch” slot

Datorteknik DelayedBranch bild 14 What about “delayed Branch” Can we avoid it? How?

Datorteknik DelayedBranch bild 15 IM Reg DMReg Delayed Branch Direct Branch Branch Logic IM Reg DMReg Branch Logic

Datorteknik DelayedBranch bild 16 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = Delayed Branch

Datorteknik DelayedBranch bild 17 Branch logic Sgn/Ze extend Zero ext. ALU A B 31 0 4 + + = = = = Branch logic Direct Branch

Datorteknik DelayedBranch bild 18 What about the instruction set? beq \$t0 \$t0 label? jr \$ra? NO, DE is not in path! b label? OK, but the new branch logic needs an ALU to compute the address

Datorteknik DelayedBranch bild 19 Different branch logic? Can both branch types coexist? Yes, no problem, but: Old type still uses “delay slot”

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