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Ain Shams University Faculty of Engineering Integrated Circuits Lab VLSI Design and Implementation of ASICs for the Security Core of BLUETOOTH Wireless.

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Presentation on theme: "Ain Shams University Faculty of Engineering Integrated Circuits Lab VLSI Design and Implementation of ASICs for the Security Core of BLUETOOTH Wireless."— Presentation transcript:

1 Ain Shams University Faculty of Engineering Integrated Circuits Lab VLSI Design and Implementation of ASICs for the Security Core of BLUETOOTH Wireless Communication System Standard Presented By: Sameh Assem Ibrahim Ahmad Abdelhameed

2 16 – July /16 IntroductionAuth. & Key gen.EncryptionSecurity coreASIC/FPGA Introduction Bluetooth Security Key generation EncryptionAuthentication Bluetooth Baseband Correction Error Correction Hop Selection SecurityOthers BluetoothArchitecture Bluetooth ArchitectureRF Baseband Manager Link Manager SoftwareLayers Software Layers

3 16 – July /16 Authentication & Key Generation Design Goals E 1, E 21, E 22 and E 3 algorithms implementation IntroductionEncryptionSecurity coreASIC/FPGA

4 16 – July /16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA Ar/Ar’ Controller Input preparation Feedback operations output Block Diagram

5 16 – July /16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA Key Schedule SAFER+ Encryption Round Controller output Final round operations Feedback operations In case of Ar’ Ar/Ar'

6 16 – July /16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA SequentialCombinational Key Schedule

7 16 – July /16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA Sequential SAFER+ Encryption Round Combinational

8 16 – July /16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA GUI MATLAB program for simulation

9 16 – July /16 Encryption Input Shuffling (confusion and diffusion)Input Shuffling (confusion and diffusion) Summation Stream Cipher (Massey - Rueppel)Summation Stream Cipher (Massey - Rueppel) Encryption Engine IntroductionAuth. & Key gen.Security coreASIC/FPGA

10 16 – July /16 Encryption Block Diagram IntroductionAuth. & Key gen.Security coreASIC/FPGA

11 16 – July /16 Security CoreFeatures: Key generation : E 21, E 22, E 3Key generation : E 21, E 22, E 3 Authentication : E 1Authentication : E 1 Encryption : E 0Encryption : E 0 Built in PRNG : 128 bitsBuilt in PRNG : 128 bits Built in S/P & P/SBuilt in S/P & P/S Built in ControllerBuilt in Controller Pseudo-Random Number Generator Proposed Design IntroductionAuth. & Key gen.EncryptionASIC/FPGA

12 16 – July /16 ASIC/FPGA Back Annotation All Controls (Modified) S10PC84 IntroductionAuth. & Key gen.EncryptionSecurity core

13 16 – July /16 ASIC/FPGA FPGA tests IntroductionAuth. & Key gen.EncryptionSecurity core

14 16 – July /16 ASIC/FPGA FPGA Reports *************************************************** Device Utilization for S10PC84 *************************************************** Resource Used Avail Utilization IOs % FG Function Generators % H Function Generators % CLB Flip Flops % Clock Frequency Report Clock : Frequency CLK : 55.3 MHz S10PC84 EncryptionEngine Number of ports : 45 Total accumulated area : Number of Dffs or Latches : 2553 Number of Function Generators : 4948 Number of MUX CARRYs : 1006 Number of MUXF5 : 367 Number of MUXF6 : 110 Number of gates : 4752 *************************************************** Device Utilization for v1000fg680 *************************************************** Resource Used Avail Utilization IOs % Function Generators % CLB Slices % Dffs or Latches % Clock : Frequency clk : 66.2 MHz V1000FG680 SecurityCore IntroductionAuth. & Key gen.EncryptionSecurity core

15 16 – July /16 ASIC/FPGA ASIC flow AMS 0.6 µm technology Double metal layers Single poly Core Area: mm 2 IntroductionAuth. & Key gen.EncryptionSecurity core

16 16 – July /16


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