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EXAMPLE 3 DIV Unit is not Pipelined. So second instruction waits in ID stage although it is independent. DIV.D F0,F1,F2 IFID DIV1DIV1 DIV2DIV2 DIV3DIV3.

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Presentation on theme: "EXAMPLE 3 DIV Unit is not Pipelined. So second instruction waits in ID stage although it is independent. DIV.D F0,F1,F2 IFID DIV1DIV1 DIV2DIV2 DIV3DIV3."— Presentation transcript:

1 EXAMPLE 3 DIV Unit is not Pipelined. So second instruction waits in ID stage although it is independent. DIV.D F0,F1,F2 IFID DIV1DIV1 DIV2DIV2 DIV3DIV3 DIV4DIV4 DIV5DIV5 oooooo D I V 24 MEME WB ADD.D F5,F6,F7 IFID oooooo DIV1DIV1

2 Example 4 - Out Of Order Execution L.D F10,0(R2) IFIDEXEMEMWB ADD.D F0,F1,F2 IFIDA1A2A3A4MEMWB ADDI R5, R5, 10 IFIDEXEMEMWB Mul.D F9,F6,F7 IFIDM1M2M3M4 M5M5 M6M6 M7MEMWB Add R3,R9,R10 IFIDEXEMEMWB Sub R7,R8,R10 IFIDEXEMEMWB Note All Instructions Independent Out Of Order Completion

3 Example 5 Clock Cycle Number Mul.DIFIDM1M2M3M4M5M6M7MEMWB o o oIFIDEXMEMWB o o oIFIDEXEMEMWB Add.DIFIDA1A2A3A4MEMWB o o oIFIDEXEMEMWB o o oIFIDEXEMEMWB L.DIFIDEXEMEMWB Structural Hazard

4 Example 6 - WAW MUL.D F3,F1,F2IFIDID M1M1 M2M2 M3M3 M4M4 M5M5 M6M6 M7M7 MEMMEM WBWB ADD.D F1,F5,F4IFIDID A1A1 A2A2 A3A3 A4A4 MEMMEM WBWB MUL.D F3,F9,F12IFIDID IDID IDID IDID IDID IDID IDID IDID M1M1 M2M2 Reg Busy bit in Register File

5 Example 7 L.D F4, 0(R2) MUL.DF0,F4,F6 ADD.DF2,F0,F8 S.DF2,0(R2)

6 Example 8 - EXCEPTIONS DIV.D F0,F1,F2 ADD.DF10,F10,F8 SUB.DF12,F12,F14

7 Data Hazards RAW Hazard ADD.D F3, F1, F2 SUB.D F5, F6, F3 WAW Hazard DIV.D F3, F1, F2 SUB.D F3, F6, F5 WAR Hazard DIV.D F3, F1, F2 SUB.D F5, F6, F3 ADD.D F3, F6, F7

8 TOO MANY ID STAGE STALLS – SOLUTION?

9 THE SCOREBOARD

10

11 I C a c h e S1 S2 OP S1 S2 OPD S1 S2 OP S1 S2 OP S1 S2 OP S1 S2 OP S1 S2 OP Fj Fk ADDER Fi Op WRITE RWRITE R Fj Fk MULT1 Fi Op WRITE RWRITE R Fj Fk MULT2 Fi Op WRITE RWRITE R Fj Fk DIV Fi Op WRITE RWRITE R Instruction Queue Fj, Fk, Source Register Number (5-bit) Fi, Destination, 5-bit (32-registers) Rj, Rk, Flags Qi,Qj, 4 or 5-bit, FU Number

12 ISSUE Read Operands Check for WAW, FU Check for RAW, Read Values from Register File when free Read Operands EXMem WB EX A1A1 A2A2 A3A3 A4A4 M1M1 M2M2. M7M7 Divide Read Operands Check for WAR Register File

13 Scoreboard Operation Instruction Status Wait UntilBookkeeping by the Scoreboard Issue Stage (ID/1) Function Unit is not Busy Not Busy [FU] No other Instruction has the same destination register (WAW Hazard). This can be checked by looking in the bookkeeper’s Result Registers. not Result[D] Make the function unit busy Busy[FU] ← YES Read Opcode in the Function Unit Op[FU] ← IR.op Store the number of the destination register in Function Unit Fi[FU] ← D Store the Number of the source registers in the function unit. Fj[FU] ← S1, Fk[FU] ← S2 If the source registers are waiting for a result from another function unit, get the function unit name in the Q fields. Q Fields only active for this case. Else make Q fields as 0. THE RAW hazard. Qj ← Result[Si] ; Qj will be ‘0’ after result is available Qj ← Result[Si] Make Source ready flags not available (0) if Q fields are busy (1) and vice versa….. Simple inversion. Rj ← NO if Qj≠0, R K ← NO if Q K ≠0 Update the bookkeepers result register Result[D] ← Fu

14 Operation Contd… Instruction Status Wait UntilBookkeeping by the Scoreboard Read Operand Stage (ID/2) Wait until Rj and Rk become 1, (sources are available) Operands have been read. So make R flags NO, meaning read (This is important as shown below in the Write Result (WR) stage. Rj ← No, Rk ← No (set to default) Set Q fields to 0. Qj ← 0, Qk ← 0 (set to default) (EX)Wait until FU completes execution NONE Write Result (MEM) Before writing result check that a 2 nd function unit is not waiting to read result from a 3 rd function unit This can be done by checking all function units that have same source register as this unit’s Destination register and they are waiting for operands from another FU.  ((Fj[  ]  Fi[FU] or Rj[  ] = No and  ((Fk[  ]  Fi[FU] or Rk[  ] = No To prevent WAR hazard. For example see the following program DIV.D F0, F2, F4 ADD.D F10, F0, F8 SUB.D F8, F8, F14 Here the SUB.D cannot Write until 2 nd Function Unit ADD.D has not read the result of the 3 rd Function Unit DIV. One cleared the WAR hazard do the following: This will make other instructions waiting in Read Operand Stage (see above) go through.  (if (Qj[  ] =[FU] then Rj[  ]← yes)  (if (Qk[  ] =[FU] then Rk[  ]← yes) Clear bookkeepers Result register Result [Fi[FU]] ← 0 Make this function unit free Busy[FU] ← No

15 Scoreboard (The Shift In-charge) Functions Instructions are issued in order but executed and committed out of order and Committed(OOOE+OOOC) Reduces many ID Stage stalls by out-of-order execution of independent instruction (Instruction Level Independence hence possibility of parallel execution also called Instruction Level Parallelism (ILP)) Keeps records of instruction and in which stage they are currently in. No Forwarding, Read Operands happens after Write Result (Not in same clock cycle as result could only be read from register after write). Keeps a big record of each function unit BUSY status Op code assigned Destination Register (Fi) Source Register (Fj, Fk) Function units that will produce the result to be used by this function unit (Qj, Qk) Operand available Status (Rj, RK indicate when Fj and Fk are ready and not yet read. Set to NO when they are read and FU goes into execution stage. Register Result Status: For every register, it indicates what function unit has a pending result for this register.

16 Scoreboard Limitations Long WAW delays. Ideally need to separate waiting for values (resolving RAW hazards) from issue. Basic Scoreboard system stalls on both WAR and WAW hazards which could be resolved by register renaming (discussed in chapter 3 and 4). No way to deal with memory based RAW hazards (or WAR or WAW) e.g. any memory load must wait for all outstanding stores to complete, in case they are to same address. (unless compiler can detect?) No memory based operations can occur in parallel/out of order – again limits instruction level parallelism. Deferred READ: Another problem not mentioned in the book but often associated with scoreboards.

17 E X A M P L E CDC6600 No Full Pipelining No Forwarding FPADD = 2 CC, MUL = 10, DIV = 60 Total Scoreboard Hardware = 1 FU (simple) Slides Prepared by Jahangir Ikram, Oct 2006

18 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F SUB.D F8, F6, F DIV.D F10, F0, F ADD.D F6, F8, F Name of FU FU BUSY Op Code Source Operand Register ID Fi Dest Results Coming From FU Operand Available FjFkQjQkRjRk Int YESLoadR2-F600YesYES Mult Add Div Result Status Register F0F1F2F3F4F6F8F10F12 FU Integer Jahangir Ikram, Oct 2006

19 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F SUB.D F8, F6, F DIV.D F10, F0, F ADD.D F6, F8, F Name of FU FU BUSY Op Code Source Operand Register ID Fi Dest Results Coming From FU Operand Available FjFkQjQkRjRk Int YESLoadR2-F600YesYES Mult Add Div Result Status Register F0F1F2F3F4F6F8F10F12 FU Integer Jahangir Ikram, Oct 2006

20 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) Address Calculation + Memory Access in L.D F2, 45(R3) 5678 MUL.D F0, F2, F SUB.D F8, F6, F DIV.D F10, F0, F ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Fi Dest Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) YESLoad[2-F600NO Mult (2) Add (3) Div (4) Result Status Register F0F1F2F3F4F6F8F10F12 FU Integer Jahangir Ikram, Oct 2006

21 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) FU Free 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F SUB.D F8, F6, F DIV.D F10, F0, F ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Fi Dest Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) Add (3) Div (4) Result Status Register F0F1F2F3F4F6F8F10F12 FU Jahangir Ikram, Oct 2006

22 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3)Can be issued now 5678 MUL.D F0, F2, F SUB.D F8, F6, F DIV.D F10, F0, F ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Fi Dest Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) YESLOADR3-F200Yes Mult (2) Add (3) Div (4) Result Status Register F0F1F2F3F4F6F8F10F12 FU Int(1) Jahangir Ikram, Oct 2006

23 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) Read Operand Values in Fj and Fk 5678 MUL.D F0, F2, F4 Issued But RAW F2 Busy SUB.D F8, F6, F DIV.D F10, F0, F ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Fi Dest Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) YESLOADR3-F200Yes Mult (2) YESMULF2F4F0Int(1)0NoYES Add (3) Div (4) Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Int(1) Jahangir Ikram, Oct 2006

24 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 Stalled in RO Stage 67-8, SUB.D F8, F6, F2 Issued But RAW F2 Busy DIV.D F10, F0, F ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) YESLOADR3-F200NO Mult (2) YESMULF2F4F0Int(1)0NoYES Add (3) YESSUBF6F2F80Int(1)YESNO Div (4) Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Int(1)ADD(3) Jahangir Ikram, Oct 2006

25 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 Stalled in RO Stage 67-8, SUB.D F8, F6, F2 Stalled in RO Stage 78, DIV.D F10, F0, F6 Issued but RAW on F ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F000 No→ Yes YES Add (3) YESSUBF6F2F800YES No→ Yes Div (4) YESDIVF0F6F10Mul(2)0NoYes Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)ADD(3)DIV(4) Jahangir Ikram, Oct 2006

26 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 Both read operands simultaneously 67-8, SUB.D F8, F6, F2 78,98, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Cannot Issue Adder Busy Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F000YesYES Add (3) YESSUBF6F2F800YES Yes Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)ADD(3)DIV(4) Jahangir Ikram, Oct 2006

27 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in EXE 67-8, SUB.D F8, F6, F2 2 CC in EXE 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Cannot Issue Adder Busy Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F000No Add (3) YESSUBF6F2F800No Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)ADD(3)DIV(4) Jahangir Ikram, Oct 2006

28 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 cc in EXE 67-8,910,1120 SUB.D F8, F6, F2 2 CC in EXE 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Cannot Issue FU Busy Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESSUBF6F2F8 Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)ADD(3)DIV(4) Jahangir Ikram, Oct 2006

29 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8,9 10,11, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Cannot Issue FU Busy Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) Mult (2) YESMULF2F4F0 Add (3) NO Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)0DIV(4) Jahangir Ikram, Oct 2006

30 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8,9 10,11,12,13 20 SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 FU Free so Issue Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F600YES Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

31 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8,9 10,11,12,13, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Reads Operands Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F600YES Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

32 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F600NO Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

33 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 2 CC in EXE Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F6 Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

34 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Wait in WB as WAW ,22 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F6 Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

35 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Wait in WB as WAW ,18,2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F6 Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

36 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 10 CC in Exe 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage ADD.D F6, F8, F2 Wait in WB as WAW ,2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) YESMULF2F4F0 Add (3) YESADDF8F2F6 Div (4) YESDIVF0F6F10Mul0NoYES Result Status Register F0F1F2F3F4F6F8F10F12 FU MUL (2)Add(3)DIV(4) Jahangir Ikram, Oct 2006

37 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 Finally MUL Finished 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Stalled at RO stage 89—20, ADD.D F6, F8, F2 Wait in WB as WAW ,2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) NO Add (3) YESADDF8F2F6 Div (4) YESDIVF0F6F1000YES Result Status Register F0F1F2F3F4F6F8F10F12 FU 0Add(3)DIV(4) Jahangir Ikram, Oct 2006

38 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6Reads Operans 89—20, ADD.D F6, F8, F2 Wait in WB as WAW ,2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) NO Add (3) YESADDF8F2F6 Div (4) YESDIVF0F6F1000YES Result Status Register F0F1F2F3F4F6F8F10F12 FU Add(3)DIV(4) Jahangir Ikram, Oct 2006

39 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F640 CC in EXE 89—20, 2122, 6162 ADD.D F6, F8, F ,, 2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NO Mult (2) NO Add (3) No Div (4) YESDIVF0F6F1000NO Result Status Register F0F1F2F3F4F6F8F10F12 FU DIV(4) Jahangir Ikram, Oct 2006

40 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F640 CC in EXE 89—20, 2122, 6162 ADD.D F6, F8, F ,, 2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NOXXXX00 Mult (2) NOXXXX00 Add (3) NoXXXX00NO Div (4) YESDIVF0F6F1000NO Result Status Register F0F1F2F3F4F6F8F10F12 FU DIV(4) Jahangir Ikram, Oct 2006

41 Instruction Status (Stage Completed) InstructionCommentsIssueRead OperandsExecution Complete Write Result L.D F6, 34(R2) 1234 L.D F2, 45(R3) 5678 MUL.D F0, F2, F4 67-8, SUB.D F8, F6, F2 78, DIV.D F10, F0, F6 89—20, 2122, 6162 ADD.D F6, F8, F2 Finally Writes ,, 2 2 Name of FU And ID FU BUSY Op Code Source Operand Register ID Dest Fi Results Coming From FU Operand Available FjFkQjQkRjRk Int(1) NOXXXX00 Mult (2) NOXXXX00 Add (3) NoXXXX00NO Div (4) NoXXXX00NO Result Status Register F0F1F2F3F4F6F8F10F12 FU Jahangir Ikram, Oct 2006


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