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DAY 1 Morning Session Overview of semiconductor/VLSI market and product development approach - Ajay Afternoon Session VLSI Design CMOS design concepts.

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Presentation on theme: "DAY 1 Morning Session Overview of semiconductor/VLSI market and product development approach - Ajay Afternoon Session VLSI Design CMOS design concepts."— Presentation transcript:


2 DAY 1 Morning Session Overview of semiconductor/VLSI market and product development approach - Ajay Afternoon Session VLSI Design CMOS design concepts (2:00 – 3:30) – Rajeev Synthesis (3:30 – 4:00) - Ajay Floor plan & Power plan (4:00 – 4:30) - Parag Placement (4:30 – 5:00) - Parag Clock Tree Synthesis (5:00 - 5:30) – Parag Can we make two teams and play a cricket match today? DAY 2 Morning Session Routing – (10:00 – 10:30) - Rajeev STA – (10:30 – 11:00) - Rajeev Signal Integrity - (11:00 – 11:30) -Rajeev Verification (11:30 – 12:00) - Rajeev Equivalence Checking (12:00 - 12:30) – Ajay Afternoon Session Career prospects in Semiconductor Industry. Workshop Agenda

3 Workshop on VLSI Technology. 7 th and 8 th October 2009 BKBIET Pilani IETE Students Forum

4 Kindly bear with my poor teaching skill!

5 My Hobby! About myself Ajay Sainis Current Designation: Sr. ASIC Program Manager Company Name: Open-Silicon Research Professional Accomplishments -14 years of experience in the semiconductor industry. - Worked with companies like Philips Semiconductors, LSI logic. - Currently Managing complete SOC product development Educational Background - Graduated in Electronics Engineering - From Maharashtra, Nanded - In year1995

6 Outline 1.IC design since 1950 2. What is Silicon? 3. What is ASIC? 4. ASIC end products 5. ASIC market segments 6. Cost of ASIC 7. ASIC implementation styles 8. FPGA short introduction 9. ASIC design in 9 Steps 10. High level SOC design introduction! 11.Future challenges

7 1. IC design since 1950

8 IC design in 1950

9 IC Design in 1980

10 Amount of logic increase on a single chip

11 IC Design Today? Can we manually draw a transistor schematic of iPod which has ~30 million transistors?

12 Solution today? iPod needs ASIC design approach! We will talk more about the ASIC design details in this workshop!

13 CMOS Technology advantages: size reduction! System on a board System on a Chip What is 65 nanometer technology?

14 Silicon technology roadmap low power SoC high performance MPU/SoC 200120042010200120042010 gate length (nm)1309045905325 supply voltage1. transistor count (M)3.38.3402765532212 chip size (mm 2 )100120144310 clock frequency (GHz) wiring levels6797810 max power (W)0.1 130160218

15 2. What is Silicon?

16 Pizza and Silicon

17 13 Inch Pizza Vs 300mm Silicon

18 200mm Wafer Vs 300mm Wafer!

19 Creating a silicon die from Wafer

20 Fitting a die in packaged part

21 3.What is ASIC?

22 ASIC is an embedded hardware component designed for a specific end product.

23 ASIC architecture (VOIP block diagram) An example of typical gateway VOIP (Voice over Internet Protocol) diagram. What ASIC stands for?

24 ASIC Physical view An example of how physically implemented ASIC would look on a computer screen before it is sent for silicon manufacturing… DDRs Processor Core PCIe SerDes XAUI SerDes Physical routing inside!

25 4. ASIC end products

26 Example of ASIC end products Systems on chip are everywhere Technology advances enable increasingly more complex designs

27  -pro- cessor DSP ASIC Sensor A/D Actuator D/A MEMS Do you know what is inside a Mobile phone?

28 Electronic systems


30 More than 30% of the cost of a car is now in Electronics 90% of all innovations will be based on electronic systems Slide courtesy of Alberto Sangiovanni-Vincentelli  Electronics and Car!

31 5. ASIC Market segments

32 ASICs for various Market Segments - 1 What are the design challenges for each of these segments?

33 Signal processing systems –Radar, sonar, real-time video, set-top boxes, DVD players, medical equipment, residential gateways Mission critical systems –Avionics, space-craft control, nuclear plant control Distributed control –Network routers & switches, mass transit systems, elevators in large buildings “Small” systems –Cellular phones, pagers, home appliances, toys, smart cards, MP3 players, PDAs, digital cameras and camcorders, sensors, smart badges Slide courtesy of Mani Srivastava  ASICs for various Market Segments - 2 What are the design challenges for each of these segments?

34 Slide courtesy of Mani Srivastava  Product application based design approach! Example shows two different product application and required design approach!

35 6. Cost of ASIC

36 Cost of ASIC CPU DSP Ip- Sec mem X USB hub mem CPU DSP USB hub Ip- Sec X Proc Co- Proc IP cores Typical : $10 Up to now : collection of chips Now : collection of cores on single chip Typical : $70 Product cost is ~$10. Development cost is ~$2 million! What is breakeven point in ASIC business?

37 How do you calculate the cost of ASIC? ASIC cost is of two types: 1.Development cost This one time cost also called as NRE (non-recurring expenditure) This is mostly spent on the EDA tools, Human resources, Silicon masks and any other infra structure or equipment related cost. This cost is typically $1.5 million. Biggest component is mask cost. 1.Part price This is the cost of each IC/ASIC that has been developed. This cost is starts from $1 to $100 depending on the ASIC and its complexity. Following factors influence this cost. Die size cost  This includes cost of raw silicon as well as processing charges. cost of the die is directly proportional to its size. Package cost  This includes cost package material as well as assembly charges for each ASIC. Cost of package is directly proportional to complexity of the selected package. Testing cost  This includes the cost towards testing of each ASIC. The cost is directly proportional to test time of each ASIC. What is a typical time required to test an ASIC?

38 5 steps to reduce the ASIC cost! Development cost is not a major concern for most product companies as it is seen as investment for product development. However, part price matters a lot to stay in the market ahead of competition. If we understand the factors influencing the part price, it is very easy to understand the required steps to reduce the ASIC cost. 1.Design a floor-plan with minimum possible area. Save the die cost. 2.Try and use minimum routing layers from the technology. This will reduce the wafer processing cost (this also means less number of masks and less NRE) 3.Reduce number of input-output pins. This will help in selecting the package with lower pin count. Save the package cost. 4.Use different design techniques to reduce the ASIC power consumption. This will allow you to select package with lower power rating as well as there would be no need to use the heat sinks on packages. Save the package cost. 5.Try to reduce the test pattern size which is used to test the ASIC. Ensure that quality is not comprised. This will save the testing cost. What are the routing layers?

39 7. ASIC implementation styles

40 Various styles of ASIC product implementation! Full custom FPGA Standard cell

41 8. FPGA short introduction








49 FPGA Summary

50 9. ASIC design steps

51 X=(ABCD+A+D+A(B+C)) Y=(A(B+C)+AC+D+A(BC+D)) Packaging Fabrication SynthesisPhysical Design RTLFunctional DesignSystem Specification ASIC design in 9 steps Testing 1 2 3 4 5 6 7 8 Product engineering Start Selling! 9

52 STEP1: Specification

53 Specification Define complete system through a document. Identify and describe the hardware components which needs development

54 STEP2: Functional Design

55 Example: Functional Design - 1

56 Example: Functional Design - 2

57 Functional Design - 3 The implemented design needs to be verified against the spec. This process in called functional verification. Functional verification is initially done through process of simulation!

58 STEP3: RTL coding

59 What is RTL code? RTL design is a coding style which will allow EDA tool to generate a schematic using logic gates. What RTL stands for?

60 Example: RTL code (in Verilog)

61 Example: RTL code (in VHDL)

62 STEP4: Synthesis

63 What is Synthesis? Synthesis is a process of generating a gate level functionally equivalent schematic from RTL description. Output of synthesis process is Netlist! In which language netlist is written?

64 residue = 16’h0000; if (high_bits == 2’b10) residue = state_table[index]; else state_table[index] = 16’h0000; Synthesis Process RTL code Generic Boolean (GTECH) Target Technology Synthesis = Translation + Logic Optimization + Mapping Timing and Area constraints

65 Example: Netlist

66 Netlist Quality! The netlist coming out of synthesis process needs to meet following goals - meet area target - meet timing/performance target - meet power consumption target - The structural quality is equally important.

67 Structural quality of the netlist is verified through the process of netlist screening. Here is an example. Fanout > 2 Open port Feedback loop Input pad shorted Escape char \n2 ctrl clk clk1 clk2 clk3 1 ’ b0 BUS Mix of tristate / non-tristate No Bus-keeper Don ’ t use cell Tieoff cell Buf Size assign statements

68 STEP5: Physical Design

69 Example: Physical Design -1 Floor-plan (Implementation) Managing ESD and Latch-up across digital and analog IOs Decoupling Analog and digital power appropriately Providing the right IO selection Guidelines for routing analog signal wires Providing adequate physical guard rings Suggesting process layer and design guidelines to handle Substrate Noise What is die size? Why is it so important?

70 Example: Physical Design -2 Power plan (Implementation) Power and ground mesh Secondary domains mesh Power and ground rings Connections to power and ground i/os IP power and ground connections

71 Example: Physical Design -3 Placement (Implementation) Standard cells after placement

72 Example: Physical Design -4 Clock Tree (Implementation) PLL Clock Trees

73 Example: Physical Design -5 Signal routing (Implementation)

74 Example: Physical Design - 6 RC extraction (to estimate net delays)

75 Static Timing Analysis (Verification) Example: Physical Design - 7

76 Foundry Design Rule Checks (Verification) Minimum Track Width Minimum Track Spacing Blue Book Rules are different for each process Rules are described in the Blue Book Example: Physical Design - 8 DRC

77 Layout Vs Schematic checks (Verification) ZA ZA Gnd Vcc Z A Gnd Vcc Z A Example: Physical Design - 9 LVS

78 Compare RTL and Final netlist (Verification) EC RTL design Final netlist Transformation e.g. Synthesis, CTS,P&R Is A=B ? Verification Succeeded or Failed Example: Physical Design - 10 Formal Verification

79 Check the power integrity of the chip! (Verification) VDD Drop Analysis Map VSS Rise Analysis Map Example: Physical Design - 11

80 Send the design to FAB in GDS format! We are now ready for Manufacturing

81 STEP6: Manufacturing

82 Example: Fabrication STEP1: Separate each layers from GDS (Data Fracture) STEP2: Prepare mask for each layer (mask making) STEP3: Take a raw wafer (remember pizza before it is cooked) and process wafer to completion using FAB process and prepared masks (Wafer processing) STEP4: Release the processed wafer to assembly house for packaging.

83 STEP7: Packaging

84 What is packaging?

85 Leadframe Based Example: Packaging -1

86 Substrate Based Example: Packaging -2 Detailed package presentation

87 STEP8: Testing

88 Example: Testing Pass/Fail Testing What is a difference between manufacturing test Vs Functional test?

89 Testing: What is physical Defect? Physical Defect: A on-chip flaw introduced during fabrication or packaging of an individual ASIC that makes the device malfunction. Common Physical Defects Short Circuit Transistor Always ON Open Circuit Oxide Pinholes What is DFT?

90 Testing: Physical Defect in CMOS Physical view of CMOS inverter with defects!

91 Testing Vs Verification! What is yield in silicon? Detailed ASIC TEST presentation

92 STEP9: Product engineering

93 Example: Product engineering

94 STEP10: Start selling the ASIC!

95 10. High level SOC design!

96 High level SOC flow

97 How to Design an SOC





102 Future challenges?

103 Example of SOC complexity matrix

104 SOC future challenges! We can’t Design it right! -Silmulation is not enough! -On an average 3 product design iteration is required. We can’t make it right! -Manufacturing variability increasingly difficult to control below ~60nm due to atomic effects We can’t Test it right! - Increasing number of gates and logic make it difficult to have good TEST coverage! We can’t keep it right! - Susceptibility to particles and wear-out increasing - Silicon product life time in reducing

105 Outline 1.IC design since 1950 2. What is Silicon? 3. What is ASIC? 4. ASIC end products 5. ASIC market segments 6. Cost of ASIC 7. ASIC implementation styles 8. FPGA short introduction 9. ASIC design in 9 Steps 10. High level SOC design introduction! 11.Future challenges

106 Thank you for your patience! Questions?

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