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VITURBO: A Reconfigurable Architecture for Future Ubiquitous Wireless Networks Mani Vaya August 7, 2002 Rice University

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Overview Motivation Communication Systems and Standards Channel Encoding and Decoding Techniques VITURBO Design Tools Results Conclusions & Future Work

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Ubiquitous Networks Anytime, Anywhere Networks Ubiquitous = Outdoor Cellular Networks + High Speed Indoor Wireless LANs Seamless transfer between different environments One receiver for all environments

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Ubiquitous Networks Cellular Systems High Speed Local Area Networks

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Motivation Motivation: Instead of multiple architectures for multiple standards one single receiver architecture for multiple standards Means: Exploitation of commonalities between channel decoding algorithms for multiple standards, and their architectural realizations End Result : Reduced area, reduced cost reconfigurable architectures

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Related Work Lucent: Unified Turbo/Viterbi Decoder –Uses log-MAP for Turbo decoding –4 ACS units in total –Limited to 3G (2 Mbps Turbo, 384 Kbps Viterbi) Rice: Reconfigurable Viterbi Decoder –Uses hard metrics (practical systems use soft metrics) –Data Rates up to 26 Mbps –Unable to turn down units not in use –Only does Viterbi decoding

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Our Contribution Design and Implementation of reconfigurable channel decoder for a and 3G systems – Achieves data rates for both systems – SOVA based Turbo decoding, and HDVA based Viterbi decoding –Extremely flexible and is capable of decoding constraint length 3-9 convolutional codes+ Turbo codes –Power saving mechanisms employed in the system

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Next Ubiquitous Wireless Networks Communication Systems and Standards Channel Encoding and Decoding Techniques VITURBO Design Tools Results Conclusions & Future Work

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CDMA System Channe l

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OFDM System Channe l

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Next Motivation Communication Systems and Standards Channel Encoding and Decoding Techniques VITURBO Design Tools Results Conclusions & Future Work

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Channel Encoding in Different Standards StandardMaximum Data Rate Code TypeCode Rate Constraint length WLAN54 MbpsConvolutional1/27 CDMA20002 MbpsConvolutional1/2,1/39 CDMA20002 MbpsTurbo1/34 3GPP2 MbpsConvolutional1/2,1/39 3GPP2 MbpsTurbo1/34

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Simple Convolutional Coder (SCC) : XOR : Shift Register U : Input Data Y 0 0,Y 0 1 : Output Data Rate: Number of Inputs/Number of Outputs = 1/2 Constraint Length: Number of Shift Registers +1= 3 Generator Polynomials: g0=[1 1 1], g1= [1 0 1]

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Viterbi Algorithm Decoding complexity increases exponentially with constraint length Finds the most likely sequence of state transitions through a finite state trellis

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Viterbi Decoder BMU: Branch Metric Unit ACS: Add Compare Select SMU: Survivor Management Unit

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Turbo Encoder U: Input data RSC: Constituent Encoders I : Interleaver X 1p, X 2p : Output Data(Parity) X s : Output Data(Systematic)

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Recursive Systematic Convolutional(RSC) Encoder Recursive: Intermediate Data is fed back to the encoder Systematic: Output X s is same as input U

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Turbo Decoding Reliability of decisions is computed and iterated between two decoders, in order to get a reliable estimate of the data Two competing algorithms: Soft Output Viterbi Algorithm(SOVA) & Maximum a posteriori Probability Algorithm(MAP) MAP has superior performance compared to SOVA, but SOVA is very similar to VA, and hence the choice for VITURBO

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SOVA based Turbo Decoder Y1p,Y2p: Received Parity data Ys: Received Systematic Data Le(12/21): Soft Information

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Next Motivation Communication Systems and Standards Channel Encoding and Decoding Techniques VITURBO Design Tools Results Future Work

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VITURBO: Features Completely parallel architecture for constraint length 9 (2 K-2 ACS units ), for high speed decoding Smaller constraint length decoding uses parts of larger circuit Flexible for a wide range of constraint lengths, generator polynomials and rates Power saving mechanisms help in shutting down units not in use for a particular decoding type

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VITURBO: Complete Architecture

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Reconfigurable BMU

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BMU & Codeword Look-Up Table Possible Codewords for rate k/n code : 2 n Corresponding codeword for each butterfly: Defined by generator polynomial Contemporary Solutions: Use of inbuilt encoders for each code configuration Our Solution: Programmable Codeword Look-Up Table for enhanced flexibility and low power. Programmable for any codeword for K=3-9

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Reconfigurable BMU

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Reconfigurable ACS Unit & ACS Routing

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Reconfigurable Add Compare Select Sub Unit PM0’,PM1’: Input Path Metrics BM0’, BM1’: Input Branch Metrics PM0, PM1: Competing Path Metrics Decoder Type(Viterbi/Turbo)

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State Transitions and Butterflies K=3, SCCK=4, RSC J th butterfly for Constraint length K J th butterfly’s computations are done in J th ACS unit

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ACS Path Metric Routing Problem ACS(0) To ACS(0) To ACS(1) ACS(0) From ACS(0) From ACS(1) From ACS(0) From ACS(1) To ACS(0) To ACS(2) K=3 K=4K=…..,9

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ACS Path Metric Routing Solution Solution for All Ks: ACS(0) ACS(127) Multiplexer Bank (256 Muxes) ACS(1) Decoder Type Constraint length

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PM0’,PM1’: Input Path Metrics BM0’, BM1’: Input Branch Metrics PM0, PM1: Competing Path Metrics J th ACS Unit and Mux Bank

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BMU, ACS and MUX banks

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Reconfigurable SMU

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Flexible Hard Decision Traceback Flexible Traceback DecisionLUT C Decbit P K Xt Xt/Xv

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Flexible Traceback for Viterbi and Turbo Decoding C: Current State, P: Previous State decbit :decision bit Xv and Xt: decoded data for Viterbi and Turbo decoding respectively Decision-LUT is a Look-Up table for various possible decisions for Turbo Decoding If C >= 2 K-2 then P= 2*C+ decbit - 2 K-1 xv=1 else P = 2*C + decbit xv=0 end if xt = DecisionLUT(2*C+ decbit)

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SOVA Traceback Architecture ML Path Competing Paths (All colors except black) I k-U : Decoded data at time k-U L k-U : Soft Information at time k-U U: Reliability depth(3*K)

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Power Saving Architecture is completely parallel for constraint length 9 (128 ACS units) Smaller constraint length decoders use parts of the complete circuit In order to save power, units not being used are shut down Quiescent Power is constant for all the different configurations

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Power Saving Mechanism for ACS units

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Next Motivation Communication Systems and Standards Channel Encoding and Decoding Techniques VITURBO Design Tools Results Conclusions & Future Work

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Design Tools Xilinx’s Virtex-II 2000K gate FPGA used to implement the design Xilinx’s ISE development environment used for design, synthesis, and implementation –Design described in VHDL –Modelsim used for simulations –Synplicity used for synthesis –XPower used for power estimation

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Next Motivation Communication Systems and Standards Channel Encoding and Decoding Techniques Viterbi and Turbo Decoding Architectures VITURBO Design Tools Results Conclusions & Future Work

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Gate Requirements for Different Realizations V(K1-K2) : Viterbi(Constraint length) T : Turbo

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Area Savings Conventional architecture: –Separate architectures for K=7,9, and Turbo –Total Logic Area requirements= 267,147 Reconfigurable VITURBO –Same architecture for K=7,9, and Turbo –Total Logic area requirements = 190,288 Area Savings = 28.7 %

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Maximum Clocking Frequency V(K1-K2) : Viterbi(Constraint length) T : Turbo

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Power Analysis DecoderClock Frequency Data Rate Power Consumption (sans Quiescent power) Energy/Bit (Joules/bit) Quiescent Power K=7 (WLAN) 54 Mhz54 Mbps501.3 mW9.28 nJ225 mW K=9 (3GPP) 2 Mhz2 Mbps59.54 mW29.77 nJ225 mW K=4 Turbo (3GPP) 34.3 Mhz2 Mbps mW52.38 nJ225 mW

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Next Motivation Communication Systems and Standards Channel Encoding and Decoding Techniques VITURBO Design Tools Results Conclusions & Future Work

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Conclusions VITURBO achieves data rates stipulated by a and 3G systems Reconfigurable architectures are a feasible proposition for future communication systems, as they –Provide flexibility –Save Area

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Possible Future Work Use of log-MAP for Turbo Decoding Use of Termination Algorithms for Turbo Decoding for lower power consumption Use of remaining ACS units for high data rate Turbo decoders Architecture designs with smaller number of ACS units Exploitation of similarities in other baseband processing units for CDMA and OFDM systems

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Backups

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Area-Time-Decoder Tradeoffs

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SOVA Algorithm- Branch Metric :Branch Metric for state transition from s’ to s :Extrinsic Information from previous decoder :Channel Value= :Output of RSC1 at time k, for input u k

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SOVA Traceback

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SOVA Traceback Blocks

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Two Step SOVA -SM D: Decoding Depth U: reliability Depth k: Index of decoded bit

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