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3. ASIC and SOC Design Methods: Structured VLSI Design Spring 2009 Rajesh K. Gupta.

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Presentation on theme: "3. ASIC and SOC Design Methods: Structured VLSI Design Spring 2009 Rajesh K. Gupta."— Presentation transcript:

1 3. ASIC and SOC Design Methods: Structured VLSI Design Spring 2009 Rajesh K. Gupta

2 Outline  Circuit Styles  The evolving ASIC Design Methodology  References:  Basic Logic Families, Kerry Bernstein, Ch. 7, of A. Chandrakasan et. al. book  Chapter 11 of Rabaey book

3 Basic Logic Families  Circuit Styles  Different possible circuit topologies for a given logic function (from the same set of basic transistor devices)  even within CMOS: compatible CMOS styles  Choice determined by design criteria: performance, power consumption, testability, ease of design (analysis)  Available styles  Nonclocked logic (clocked logic discussed after clocking)  example: static combinatorial CMOS, differential cascode voltage-switch logic, pass-transistor logic  generally: low power, ease of automated synthesis, easy timing analysis, reliability and noise immunity, defect tolerance, migration across process.  Reliability because nodes maintain values (never left to float), direct control of nodal values (noise immunity), switch points can be varied.

4 Nonclocked: Static Combinatorial CMOS  Operate under “push-pull” action  Transfer function  similar to the inverter transfer function  unity gain point (UGP)  point on the transfer function where slope is -1  a circuit will attenuate inputs less than the lower UGP and amplify inputs higher than the lower UGP  switch point (SWP)  where Vin = Vout  can be skewed by the effective device sizing by hastening transition in a given direction  noise margin  is the difference between the least positive up level of the preceding stage and the upper UGP of the given stage  or the most positive down level of the previous stage and the lower UGP of the given stage.

5 Static CMOS  Delay variations  by the input pattern, by switching history  by the active fanout load  depending upon the channel state, gate-substrate capacitance changes (towards inversion gate-substrate capacitance drops)  signal coupling in interconnect changes fanout load  false switching (consumes about 15% of the total power)  Design rules  Alpha ratio:  ratio of the total output capacitance on a given stage divided by its total input capacitance; (2.7 produces minimum PDP)  Beta ratio:  ratio of a given stage’s PFET W/L to its NFET W/L  NAND n-stack design:  body effect on the top device decreases its drive  device tapering and signal positioning.

6 Domino CMOS  Domino logic is evaluated through single-sided transitions  no need for complimentary logic implementations  generally N-FET evaluation trees (smaller area)  To ensure single transitions, all outputs are inverted so that the inputs only make a transition from low to high  several issues related to capacitive coupling, noise immunity and false discharges

7 Pass-Gate Logic  Logic evaluation by signal coupling  rather than by signal evaluation and redriving  Generally lower capacitive loads  However, many liabilities  limited fan-in capability  current discharge to ground through a pass-gate must be limited to achieve acceptable low levels at the receiver  excessive fan-out  the driver to pass gates (for example, output inverter driving subsequent pass gates) must be sized for all the paths its serves  noise vulnerability  interconnect coupling can be propagated through a pass- gate  Body bias effects reduce available drive  Path protection need for decoders: when used as mux, gate inputs are needed to ensure paths are maintained.  Improved by complementary pass-gate logic (CPL)

8 Structured VLSI Design

9 Four Phases in Creating a Chip

10 The Design Problem Source: sematech97 A growing gap between design complexity and design productivity [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

11 VLSI-design Tools & Methodologies  Goal is to reduce complexity, increase productivity, and increase chances of a working chip  Key is the use of Constraints and Abstractions  Constraints  help automate the procedure by simplifying the problem  Abstractions  collapse detail and arrive at a simpler problem to deal with  Different design methodologies  different types of constraints and trade-offs  choice driven by economics!

12 Design Domains  Behavioral  what a system does  Structural  how entities are connected together to perform the behavior  Physical (geometrical)  how to build a structure that has the required connectivity to implement the prescribed behavior

13 Levels of Design Abstractions for Each Design Domain  Architectural  Algorithmic  Module or functional block  Logical  Switch  Circuit  Device  etc.

14 Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."

15 Design Methodology  Design process traverses iteratively between behavior, structure, and geometry abstractions  CAD tools providing more and more automation Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

16 A Simplified Flow Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

17 Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

18 Transition to Automation and Regular Structures Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8286 Intel 8486 Courtesy Intel Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

19 Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

20 Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

21 Automatic Cell Generation Courtesy Acadabra Initial transistor geometries Placed transistors Routed cell Compacted cell Finished cell Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

22 MacroModules 256  32 (or 8192 bit) SRAM Generated by hard-macro module generator Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

23 “Soft” MacroModules Synopsys DesignCompiler Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

24 “Intellectual Property” A Protocol Processor for Wireless Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

25 Semicustom Design Flow HDL Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation Structural Physical Behavioral Design Capture Design Iteration Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

26 The “Design Closure” Problem Courtesy Synopsys Iterative Removal of Timing Violations (white lines) Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

27 Integrating Synthesis with Physical Design Physical Synthesis RTL(Timing) Constraints Place-and-Route Optimization Artwork Netlist with Place-and-Route Info Macromodules Fixed netlists Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

28 Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Late-Binding Implementation Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

29 Gate Array — Sea-of-gates Uncommited Cell Committed Cell (4-input NOR) Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

30 Sea-of-gate Primitive Cells Using oxide-isolationUsing gate-isolation Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

31 Prewired Arrays Classification of prewired arrays (or field-programmable devices):  Based on Programming Technique  Fuse-based (program-once)  Non-volatile EPROM based  RAM based  Programmable Logic Style  Array-Based  Look-up Table  Programmable Interconnect Style  Channel-routing  Mesh networks Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

32 Antifuse  Normally high resistance (> 100 M  )  on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200- 500  )

33 Array-Based Programmable Logic PLAPROMPAL O 1 O 2 O 3 Programmable AND array Programmable OR array O 1 O 2 O 3 Programmable AND array Fixed OR array Indicates programmable connection Indicates fixed connection Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

34 Programming a PROM f 0 1X 2 X 1 X 0 f 1 NA : programmed node Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

35 2-input mux as programmable logic block F A0 B S 1 Configuration ABSF= 0000 0X1X 0Y1Y 0YXXY X0Y Y0X Y1XX 1 Y 10X 10Y 1111 X Y Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

36 Logic Cell of Actel Fuse-Based FPGA Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

37 Look-up Table Based Logic Cell Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

38 LUT-Based Logic Cell Courtesy Xilinx D 4 C 1....C 4 x xxxxx D 3 D 2 D 1 F 4 F 3 F 2 F 1 Logic function of xxx Logic function of xxx Logic function of xxx xx 4 x xx xxxx H P Bits control Bits control Multiplexer Controlled by Configuration Program x x x x xx x xxxx x xx xxxx xx x x Xilinx 4000 Series Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

39 Array-Based Programmable Wiring Input/output pinProgrammed interconnection Interconnect Point Horizontal tracks Vertical tracks Cell Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

40 Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point Courtesy Dehon and Wawrzyniek Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

41 Transistor Implementation of Mesh Courtesy Dehon and Wawrzyniek Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

42 Hierarchical Mesh Network Use overlayed mesh to support longer connections Reduced fanout and reduced resistance Courtesy Dehon and Wawrzyniek Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

43 EPLD Block Diagram Macrocell Primary inputs Courtesy Altera Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

44 Altera MAX From Smith97 Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

45 Altera MAX Interconnect Architecture row channelcolumn channel LAB Courtesy Altera Array-based (MAX 3000-7000) Mesh-based (MAX 9000) Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

46 Field-Programmable Gate Arrays Fuse-based Standard-cell like floorplan Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

47 Xilinx 4000 Interconnect Architecture 2 12 8 4 3 2 3 CLB 8484 Quad Single Double Long Direct Connect Direct Connect QuadLongGlobal Clock LongDoubleSingleGlobal Clock Carry Chain Long 1244 Courtesy Xilinx Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

48 RAM-based FPGA Xilinx XC4000ex Courtesy Xilinx Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

49 Architecture ReUse  Silicon System Platform  Flexible architecture for hardware and software  Specific (programmable) components  Network architecture  Software modules  Rules and guidelines for design of HW and SW  Has been successful in PC’s  Dominance of a few players who specify and control architecture  Application-domain specific (difference in constraints)  Speed (compute power)  Dissipation  Costs  Real / non-real time data Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

50 Source:R.Newton Platform-Based Design  A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer  New platforms will be defined at the architecture- micro-architecture boundary  They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations  Key to such approaches is the representation of communication in the platform model Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

51 Heterogeneous Programmable Platforms Xilinx Vertex-II Pro Courtesy Xilinx High-speed I/O Embedded PowerPc Embedded memories Hardwired multipliers FPGA Fabric Adapted from Digital Integrated Circuits (2 nd Edition). Copyright 2002 J. Rabaey et al."

52 Principles of Structured Design Techniques  Hierarchy  Regularity  Modularity  Locality Source: Mani Srivastava, UCLA

53 Hierarchy  Divide and conquer  compose system from simpler widgets  Analogy with software  break large programs into threads and subroutines  Hierarchy can be there in all domains  behavior, structural, physical  The hierarchy in different domains may not correspond  e.g. a structural hierarchy may not map well to physical Source: Mani Srivastava, UCLA

54 Example of Structural Hierarchy Source: Mani Srivastava, UCLA

55 Example of Physical Hierarchy Source: Mani Srivastava, UCLA

56 Example of Structural Hierarchy Source: Mani Srivastava, UCLA

57 Example of Physical Hierarchy Source: Mani Srivastava, UCLA

58 Repartitioning Structural Hierarchy to Fit Physical Hierarchy Source: Mani Srivastava, UCLA

59 Regularity  Hierarchy breaks a system into submodules  but this may not solve the complexity problem  there may not be any regularity in the subdivision  we just end up with a large # of different submodules  Regularity as a guide  subdivide into a set of similar building blocks  e.g. RAM composed of identical cells  Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible Source: Mani Srivastava, UCLA

60 Regularity (contd.)  Regularity can be at all levels  circuit: use identically sized transistors  gate: similar gate structures  higher level: architectures with identical processors  Regularity helps in many ways  correct by construction  reuse of design  simplify verification of correctness Source: Mani Srivastava, UCLA

61 Circuit-level Regularity Example n A 2-1 Mux n D-type edge triggered flipflop n One-bit full add All designed using inverter and tristate buffer Source: Mani Srivastava, UCLA

62 Modularity  Condition that submodules have “well-defined” functions and interfaces  in addition to regularity and hierarchy  ‘Well-formed” modules allow their interaction with others to be “well-characterized”  Depends on the situation  e.g. in s/w a subroutine has a well-defined interface  argument list with typed variables  e.g. in IC a well-defined physical, structural, and behavioral interface  pin position, layer, size, signal type, electrical characteristics, logic function Source: Mani Srivastava, UCLA

63 Why Modularity?  Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined  Allows team design by a number of designers  Examples:  bad use: use of transmission gates as inputs  internal signals now depend on source impedance  bad use: use dynamic CMOS logic but fail to latch or register the inputs  timing of each module will have to be checked Source: Mani Srivastava, UCLA

64 Locality  Modularity provided “well-characterized” interfaces  internals of modules unimportant to exterior interface  internal details remain at the local level  a form of “information hiding”  reduces apparent complexity of the module  Locality ensures that connections are between neighboring modules, avoiding long-distance connections  Example: timing locality so that time critical operations are local  clock generation and distribution network  entire clock cycle for global signals to traverse chip  placement so that global wiring is minimized  Analogy with software  global variables are to be avoided Source: Mani Srivastava, UCLA

65 Parallels between H/W & S/W Design  Strong parallels in the way VLSIs are designed and the way complex software is  HDLs used to describe hardware systems in essence merge these two disciplines  software methods used to define hardware  Hardware-software Co-design  But, can’t ignore hardware aspects entirely  important since a physical chip is the end product Source: Mani Srivastava, UCLA


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