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Mani Srivastava UCLA - EE Department VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4.

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Presentation on theme: "Mani Srivastava UCLA - EE Department VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4."— Presentation transcript:

1 Mani Srivastava UCLA - EE Department VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4

2 Copyright 2001  Mani Srivastava 2 Reading for this Lecture n Chapter 11 of Rabaey’s book

3 Copyright 2001  Mani Srivastava 3 Four Phases in Creating a Chip This Lecture Previous Lecture Future Lecture

4 Copyright 2001  Mani Srivastava 4 The Design Problem Source: sematech97 A growing gap between design complexity and design productivity [Adapted from Copyright 1996 UCB]

5 Copyright 2001  Mani Srivastava 5 Profound Impact on the way VLSI is Designed n The old way: manual transistor twiddling F expert “layout designers” F entire chip hand-crafted F okay for small chips… but cannot design billion transistor chips in this fashion n The new way: using CAD tools at high level F tools do the grunge work… F high levels of abstractions –synthesis from a description of the behavior F libraries of reusable cores, modules, and cells Chip design increasingly like object-oriented software design! [Adapted from Copyright 1996 UCB]

6 Copyright 2001  Mani Srivastava 6 Designing a VLSI n Economic viability affected by design time n Design time affected by the efficiency of concept  requirements  architecture  logic/memory  circuit  layout n Continuous trade-off between F performance (speed, area, power) F size of die (hence cost of die and packaging) F time of design (hence cost of engineering & schedule) F ease of test generation and testability

7 Copyright 2001  Mani Srivastava 7 VLSI-design Tools & Methodologies n Goal is to reduce complexity, increase productivity, and increase chances of a working chip n Key is the use of Constraints and Abstractions F Constraints –help automate the procedure by simplifying the problem F Abstractions –collapse detail and arrive at a simpler problem to deal with n Different design methodologies F different types of constraints and trade-offs F choice driven by economics!

8 Copyright 2001  Mani Srivastava 8 Design Domains n Behavioral F what a system does n Structural F how entities are connected together to perform the behavior n Physical (geometrical) F how to build a structure that has the required connectivity to implement the prescribed behavior

9 Copyright 2001  Mani Srivastava 9 Levels of Design Abstractions for Each Design Domain n Architectural n Algorithmic n Module or functional block n Logical n Switch n Circuit n Device etc.

10 Copyright 2001  Mani Srivastava 10 Design Abstraction Levels [Adapted from Copyright 1996 UCB]

11 Copyright 2001  Mani Srivastava 11 Design Methodology n Design process traverses iteratively between behavior, structure, and geometry abstractions n CAD tools providing more and more automation

12 Copyright 2001  Mani Srivastava 12 A More Simplified Flow

13 Copyright 2001  Mani Srivastava 13 Principles of Structured Design Techniques n Hierarchy n Regularity n Modularity n Locality

14 Copyright 2001  Mani Srivastava 14 Hierarchy n Divide and conquer F compose system from simpler widgets n Analogy with software F break large programs into threads and subroutines n Hierarchy can be there in all domains F behavior, structural, physical n The hierarchy in different domains may not correspond F e.g. a structural hierarchy may not map well to physical

15 Copyright 2001  Mani Srivastava 15 Example of Structural Hierarchy

16 Copyright 2001  Mani Srivastava 16 Example of Physical Hierarchy

17 Copyright 2001  Mani Srivastava 17 Example of Structural Hierarchy

18 Copyright 2001  Mani Srivastava 18 Example of Physical Hierarchy

19 Copyright 2001  Mani Srivastava 19 Repartitioning Structural Hierarchy to Fit Physical Hierarchy

20 Copyright 2001  Mani Srivastava 20 Regularity n Hierarchy breaks a system into submodules F but this may not solve the complexity problem F there may not be any regularity in the subdivision –we just end up with a large # of different submodules n Regularity as a guide F subdivide into a set of similar building blocks –e.g. RAM composed of identical cells n Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible

21 Copyright 2001  Mani Srivastava 21 Regularity (contd.) n Regularity can be at all levels F circuit: use identically sized transistors F gate: similar gate structures F higher level: architectures with identical processors n Regularity helps in many ways F correct by construction F reuse of design F simplify verification of correctness

22 Copyright 2001  Mani Srivastava 22 Circuit-level Regularity Example n A 2-1 Mux n D-type edge triggered flipflop n One-bit full add All designed using inverter and tristate buffer

23 Copyright 2001  Mani Srivastava 23 Modularity n Condition that submodules have “well-defined” functions and interfaces F in addition to regularity and hierarchy n ‘Well-formed” modules allow their interaction with others to be “well-characterized” n Depends on the situation F e.g. in s/w a subroutine has a well-defined interface –argument list with typed variables F e.g. in IC a well-defined physical, structural, and behavioral interface –pin position, layer, size, signal type, electrical characteristics, logic function

24 Copyright 2001  Mani Srivastava 24 Why Modularity? n Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined n Allows team design by a number of designers n Examples: F bad use: use of transmission gates as inputs –internal signals now depend on source impedance F bad use: use dynamic CMOS logic but fail to latch or register the inputs –timing of each module will have to be checked

25 Copyright 2001  Mani Srivastava 25 Example of Poor Modularity

26 Copyright 2001  Mani Srivastava 26 Locality n Modularity provided “well-characterized” interfaces F internals of modules unimportant to exterior interface internal details remain at the local level F a form of “information hiding” reduces apparent complexity of the module n Locality ensures that connections are between neighboring modules, avoiding long-distance connections F Example: timing locality so that time critical operations are local clock generation and distribution network entire clock cycle for global signals to traverse chip placement so that global wiring is minimized F Analogy with software global variables are to be avoided

27 Copyright 2001  Mani Srivastava 27 Parallels between H/W & S/W Design n Strong parallels in the way VLSIs are designed and the way complex software is n HDLs used to describe hardware systems in essence merge these two disciplines F software methods used to define hardware n Hardware-software Co-design n But, can’t ignore hardware aspects entirely F important since a physical chip is the end product

28 Copyright 2001  Mani Srivastava 28 Typical VLSI Design Flow

29 Copyright 2001  Mani Srivastava 29 Types of Tools n Analysis and verification n Implementation and synthesis n Testability techniques

30 Copyright 2001  Mani Srivastava 30 Design Analysis and Verification n Accounts for largest fraction of design time n More efficient when done at higher levels of abstraction F select of correct analysis level can reduce verification time by orders of magnitude n Two approaches: F simulation: depends on choice of excitation F verification: extracts desired results directly from circuit description [Adapted from Copyright 1996 UCB]

31 Copyright 2001  Mani Srivastava 31 Simulation Approaches n Key distinction is how are data & time represented? F Circuit-level simulation (e.g. Spice) F Switch-level simulation (e.g. IRSIM) –transistors as switches with resistance F Gate-level (logic) simulation –now obsolete due to logic synthesis F Functional simulation (e.g. VHDL, Verilog) –primitives of arbitrary complexity F Behavioral simulation (e.g. VHDL) –only mimic I/O functionality –hardware delay loses its meaning

32 Copyright 2001  Mani Srivastava 32 Digital Data as Analog Signals Circuit Simulation Both Time and Data treated as Analog Quantities Also complicated by presence of non-linear elements (relaxed in timing simulation). Impractical for large circuits [Adapted from Copyright 1996 UCB]

33 Copyright 2001  Mani Srivastava 33 Representing Data as Discrete Entity Discretizing the data using switching threshold {0,1,X} representation of data The linear switch model of the inverter [Adapted from Copyright 1996 UCB]

34 Copyright 2001  Mani Srivastava 34 Discretizing Time n Evaluate circuits only at “interesting” times n Event-driven simulation F evaluate gates only at a future time of interest –current time + gate delay –for more accuracy gate delay = function of load F still, events can happen at any time n Further simplification: unit-delay model F events only at multiples of a unit time n Even further simplification: zero-delay model F events at clock F a.k.a. clock or cycle based simulation

35 Copyright 2001  Mani Srivastava 35 Circuit vs. Switch Level Simulation Circuit Switch [Adapted from Copyright 1996 UCB]

36 Copyright 2001  Mani Srivastava 36 Structural Description of Accumulator Design defined as composition of register and full-adder cells (“netlist”) Data represented as {0,1,Z} Time discretized and progresses with unit steps Description language: VHDL Other options: schematics, Verilog [Adapted from Copyright 1996 UCB]

37 Copyright 2001  Mani Srivastava 37 Behavioral Description of Accumulator Design described as set of input-output relations, regardless of chosen implementation Data described at higher abstraction level (“integer”) [Adapted from Copyright 1996 UCB]

38 Copyright 2001  Mani Srivastava 38 Behavioral Simulation of Accumulator Integer data Discrete time (Synopsys Waves display tool) [Adapted from Copyright 1996 UCB]

39 Copyright 2001  Mani Srivastava 39 Timing Verification (Synopsys-Epic Pathmill) Critical path Enumerates and rank orders critical timing paths No simulation needed! [Adapted from Copyright 1996 UCB]

40 Copyright 2001  Mani Srivastava 40 Issues in Timing Verification False Timing Paths [Adapted from Copyright 1996 UCB]

41 Copyright 2001  Mani Srivastava 41 Design Verification n Simulation only tells how circuit reacted to input excitation that was specified n Verification tools analyze design and find problems n Example: F electrical verification –transistor sizing for rise/fall time constraints F timing verification –find critical path F functional (formal) verification –compare circuit behavior against designer’s specification –proof that the two are “equivalent”, i.e. proof that the circuit will work –e.g. prove that two state machines are equivalent

42 Copyright 2001  Mani Srivastava 42 Implementation Methodologies [Adapted from Copyright 1996 UCB]

43 Copyright 2001  Mani Srivastava 43 Economics of Implementation n Decision depends on F Non-recurring engineering cost –engineering design cost (personnel, support etc.) –prototype manufacturing cost F Production cost (Recurring cost) –wafer cost, processing cost –die per wafer –die yield per wafer, packaging yield, final test yield F Fixed costs –data sheets, cost of sales n Important to estimate design time and design cost F guide to select the design method

44 Copyright 2001  Mani Srivastava 44 Choosing a Design Style

45 Copyright 2001  Mani Srivastava 45 Custom Circuit Design n When performance & design density important n High cost and long time-to-market F justified only if –high volumes –design will be reused (e.g. library cell) –cost no concern F due to CAD tools, custom design is minimal

46 Copyright 2001  Mani Srivastava 46 Tools for Custom Design n Layout editor (e.g. Virtuoso) n Symbolic layout F relative positioning followed by compactor n Design rule checking F technology file, hierarchical DRC n Circuit extraction F schematic from layout F transistors, caps, resistances, inductances n Netlist comparison and netlist isomorphism n Back annotation from layout to schematic

47 Copyright 2001  Mani Srivastava 47 Custom Design - Layout Editor Magic Layout Editor (UC Berkeley) [Adapted from Copyright 1996 UCB]

48 Copyright 2001  Mani Srivastava 48 Symbolic Layout Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program [Adapted from Copyright 1996 UCB]

49 Copyright 2001  Mani Srivastava 49 Cell-based Design Methodology n Why? Shorter design time! F but, larger penalty n Array-based design (later) cuts process steps and reduces time even further… n Standard cell F library of logic gate (nand, and, or etc.) F design as a schematic or netlist of cells from library F layout is generated automatically in rows F design and composition of library is the main issue –what fanout to design for? –Alternative versions of cells with different drive

50 Copyright 2001  Mani Srivastava 50 Standard Cell Libraries n Typically contain a few hundred cells F inverters, NAND gates, NOR gates, complex AOI, OAI gates, D- latches, and flip-flops n Each gate type can have multiple implementations to provide adequate driving capability for different fanouts F e.g the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors F the chip designer can choose the proper size to achieve high circuit speed and layout density n Cells characterized for various metrics, such as F delay time vs. load capacitance F Circuit, timing, and fault simulation models F cell data for place-and-route F mask data n Cells designed such that they can be abutted to form rows

51 Copyright 2001  Mani Srivastava 51 Standard Cell Based Design Routing channel requirements are reduced by presence of more interconnect layers [Adapted from Copyright 1996 UCB]

52 Copyright 2001  Mani Srivastava 52 Standard Cell - Example [Brodersen92] [Adapted from Copyright 1996 UCB]

53 Copyright 2001  Mani Srivastava 53 Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies [Adapted from Copyright 1996 UCB]

54 Copyright 2001  Mani Srivastava 54 Automatic Cell Generation (Compiled Cells) Random-logic layout generated by CLEO cell compiler (Digital) [Adapted from Copyright 1996 UCB]

55 Copyright 2001  Mani Srivastava 55 Module Generators n Logic gate okay for random logic n But, inefficient for regular structures F e.g. carry chain capacitance in N-bit adder n Standard cells do not exploit regularity n Structured custom design F macrocell generators, e.g. memories, multipliers –interconnects by abutment in both dimensions F datapath compilers –abutment in one dimension, routing in the other F usually “parameterizable”

56 Copyright 2001  Mani Srivastava 56 Datapath Compilers: Linear Placement [Adapted from Copyright 1996 UCB]

57 Copyright 2001  Mani Srivastava 57 Datapath Layout

58 Copyright 2001  Mani Srivastava 58 Macrocell Design Methodology Macrocell Interconnect Bus Routing Channel Floorplan: Defines overall topology of design, relative placement of modules, and global routes of busses, supplies, and clocks [Adapted from Copyright 1996 UCB]

59 Copyright 2001  Mani Srivastava 59 Channel Routing

60 Copyright 2001  Mani Srivastava 60 Macrocell-based Design Example Video-encoder chip [Brodersen92] SRAM Routing Channel Data paths Standard cells [Adapted from Copyright 1996 UCB]

61 Copyright 2001  Mani Srivastava 61 Array-based Design n Cuts process steps and reduces time even further… n Several types: F Mask programmable arrays –pre-diffused so that several masks are eliminated –typically, only top metalization needs to be done –standard packages to keep packaging cost low –e.g. gate array, sea of gates F Pre-wired arrays –avoid detailed manufacturing totally –analogy with memory

62 Copyright 2001  Mani Srivastava 62 Processing Steps in Gate Array Implementations

63 Copyright 2001  Mani Srivastava 63 Gate Array - Sea-of-gates Uncommited Cell Committed Cell (4-input NOR) [Adapted from Copyright 1996 UCB]

64 Copyright 2001  Mani Srivastava 64 Sea-of-gate Primitive Cells Using oxide-isolationUsing gate-isolation [Adapted from Copyright 1996 UCB]

65 Copyright 2001  Mani Srivastava 65 Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6  m CMOS) [Adapted from Copyright 1996 UCB]

66 Copyright 2001  Mani Srivastava 66 Pre-wired Arrays n Categories of pre-wired arrays (or, field programmable gate arrays) F fuse based (program once) F non-volatile EPROM or EEROM based F RAM based [Adapted from Copyright 1996 UCB]

67 Copyright 2001  Mani Srivastava 67 Programmable Logic Devices PLAPROM PAL [Adapted from Copyright 1996 UCB]

68 Copyright 2001  Mani Srivastava 68 EPLD Block Diagram Macrocell Courtesy Altera Corp. Primary inputs [Adapted from Copyright 1996 UCB]

69 Copyright 2001  Mani Srivastava 69 Antifuse n Normally high resistance (> 100 M  ) F on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (  )

70 Copyright 2001  Mani Srivastava 70 Antifuse-based Actel FPGAs Standard-cell like floorplan [Adapted from Copyright 1996 UCB]

71 Copyright 2001  Mani Srivastava 71 Detailed Interconnect Programming interconnect using anti-fuses [Adapted from Copyright 1996 UCB]

72 Copyright 2001  Mani Srivastava 72 Basic Block in Actel FPGA

73 Copyright 2001  Mani Srivastava 73 RAM-based FPGAs [Adapted from Copyright 1996 UCB]

74 Copyright 2001  Mani Srivastava 74 Basic Block (CLB) in RAM-based FPGAs Courtesy of Xilinx [Adapted from Copyright 1996 UCB]

75 Copyright 2001  Mani Srivastava 75 RAM-based FPGA Xilinx XC4025 [Adapted from Copyright 1996 UCB]

76 Copyright 2001  Mani Srivastava 76 General Architecture of Xilinx FPGAs

77 Copyright 2001  Mani Srivastava 77 Switch Matrices & Interconnection between CLBs

78 Copyright 2001  Mani Srivastava 78 XC2000 CLB of the Xilinx FPGA

79 Copyright 2001  Mani Srivastava 79 Overview of VLSI Design Styles

80 Copyright 2001  Mani Srivastava 80 Design synthesis Behavior  Structure

81 Copyright 2001  Mani Srivastava 81 Taxonomy of Synthesis Tasks [Adapted from Copyright 1996 UCB]

82 Copyright 2001  Mani Srivastava 82 Circuit Synthesis n Logic equations  transistor schematics F selection of circuit style –complementary static, pass-transistor, dynamic etc. F construction of logic network –e.g. Euler path techniques n Transistor sizing F to meet performance constraints –major impact on area, power, timing F subtle process… sensitive to parasitics –usually circuit modeled by equivalent RC circuit –detailed knowledge of subsequent layout process needed for estimation of parasitic capacitances

83 Copyright 2001  Mani Srivastava 83 RTL or Logic Synthesis n Generate structural view of a logic level network n Many ways of specifying: F FSMs, schematics, boolean equations, HDL etc. n Two step process: F technology independent phase –logic optimized using boolean & algebraic manipulation F technology mapping phase

84 Copyright 2001  Mani Srivastava 84 Evolution of RTL Synthesis n 2-Level logic minimization F Espresso from Berkeley F Suited for PLAs & PALs which were used a lot in 80s n Sequential and state-machine synthesis F state minimization, state encoding n Multilevel logic synthesis F Mis-II from Berkeley F standard-cell and FPGA n Full blown RTL synthesis from HDL F e.g. Synopsys’s VHDL compiler, Berkeley’s SIS

85 Copyright 2001  Mani Srivastava 85 Example: Multi-level Logic Synthesis n Adder: S = (A  B)  C i C o = A.B + A.C i + B.C i

86 Copyright 2001  Mani Srivastava 86 Architecture Synthesis n Also called behavior or high-level synthesis n Generate architecture from task description F under constraints on area, speed, power etc. n Three phases F allocation: figures out busses, execution units etc. F assignment: binds behavior operations to hardware resources F scheduling: order of operations n Also, transformations that manipulate input behavior to obtain superior solution F pipelining, parallelization etc.

87 Copyright 2001  Mani Srivastava 87 Example of Architecture Synthesis ;

88 Copyright 2001  Mani Srivastava 88 Alternative Solution

89 Copyright 2001  Mani Srivastava 89 Design-Evaluation Space

90 Copyright 2001  Mani Srivastava 90 Design-Evaluation Space for a Logic Function

91 Copyright 2001  Mani Srivastava 91 Area, Latency, Cycle-time Design Evaluation Space

92 Copyright 2001  Mani Srivastava 92 Another Example of Architecture Synthesis

93 Copyright 2001  Mani Srivastava 93 Alternative Implementations

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