Presentation is loading. Please wait.

Presentation is loading. Please wait.

Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Tel: 310-267-2098 WWW: Copyright 2003.

Similar presentations


Presentation on theme: "Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Tel: 310-267-2098 WWW: Copyright 2003."— Presentation transcript:

1 Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Tel: WWW: Copyright 2003  Mani Srivastava High-level Synthesis of Embedded Hardware EE202A (Fall 2003): Lecture #9 Note: Several slides in this Lecture are from Prof. Miodrag Potkonjak, UCLA CS

2 Copyright 2003  Mani Srivastava 2 Overview n High Level Synthesis n Allocation, Assignment and Scheduling n Estimations n Transformations

3 Copyright 2003  Mani Srivastava 3 Synthesis Process

4 Copyright 2003  Mani Srivastava 4 High Level Synthesis: Mission Statement n Provide ASIC solutions n ASIC: high speed, low cost, low power, complex control

5 Copyright 2003  Mani Srivastava 5 History - High Level Synthesis n Audio Datapaths - early 1980's n Video Datapaths - late 1980's n Communication Datapaths - forever

6 Copyright 2003  Mani Srivastava 6 Typical High-Level Synthesis System

7 Copyright 2003  Mani Srivastava 7 High Level Synthesis n Resource Allocation - How Much? n Scheduling - When? n Assignment - Where? n Module Selection n Template Matching & Operation Chaining n Clock Selection n Partitioning n Transformations

8 Copyright 2003  Mani Srivastava 8 Allocation, Assignment, and Scheduling Techniques Well Understood and Mature

9 Copyright 2003  Mani Srivastava 9 Scheduling and Assignment Control Step Control Step

10 Copyright 2003  Mani Srivastava 10 High Level Synthesis

11 Copyright 2003  Mani Srivastava 11 Algorithm Description

12 Copyright 2003  Mani Srivastava 12 Control Data Flow Graph (CDFG)

13 Copyright 2003  Mani Srivastava 13 Precedence Graph

14 Copyright 2003  Mani Srivastava 14 Sequence Graph: Start and End Nodes

15 Copyright 2003  Mani Srivastava 15 Hierarchy in Sequence Graphs

16 Copyright 2003  Mani Srivastava 16 Hierarchy in Sequence Graphs (contd.)

17 Copyright 2003  Mani Srivastava 17 Hierarchy in Sequence Graphs (contd.)

18 Copyright 2003  Mani Srivastava 18 Implementation

19 Copyright 2003  Mani Srivastava 19 Timing Constraints n Time measured in “cycles” or “control steps” u problem? n Max & min timing constraints

20 Copyright 2003  Mani Srivastava 20 Constraint Graphs

21 Copyright 2003  Mani Srivastava 21 Operations with Unknown Delays n Unknown but bounded u e.g.  Conditionals  loops n Unknown and unbounded u e.g.  I/O operations  synchronization u Completion signal u Called “anchor nodes”  Need to schedule relative to these anchors

22 Copyright 2003  Mani Srivastava 22 Scheduling Under Timing Constraints n Feasible constraint graph u Timing constraints satisfied when execution delays of all the anchors is zero u Necessary for existence of schedule n Well-posed constraint graph u Timing constraints satisfied for all values of execution delays u Implies feasibility n Feasible constraint graph is well-posed or can be made well-posed iff no cycles with unbounded weight exist

23 Copyright 2003  Mani Srivastava 23 Ill-posed (a, b) vs. Well-posed (c) Timing Constraints

24 Copyright 2003  Mani Srivastava 24 Conclusions n High Level Synthesis n Connects Behavioral Description and Structural Description n Scheduling, Estimations, Transformations n High Level of Abstraction, High Impact on the Final Design


Download ppt "Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Tel: 310-267-2098 WWW: Copyright 2003."

Similar presentations


Ads by Google