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1 Alberto Romano Schiesari – www.profars.comwww.profars.com Prev.Page Machine Instructions MACHINE INSTRUCTIONS.

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1 1 Alberto Romano Schiesari – Prev.Page Machine Instructions MACHINE INSTRUCTIONS

2 2 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips Hints and Tips

3 3 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips STORE = FROM register TO storage 2 - LOAD = FROM storage TO register 3 - xxxxR = RR instruction, operands are both registers Example: AR,SR, LR, MR, DR, LTR 4 - xxxxI = SI instruction, 1 operand is an immediate operand; it is the 2nd byte of the instruction, and is specified via an self-defining term (1 byte length) Example: MVI, SI, NI, OI, XI, etc 5 - xxxxP = SS instruction, decimal packed operands, 2 lengths specification Example: AP, SP, MP, DP, ZAP 6 - xxxxH = RX instruction, operands are 1 register and 1 halfword storage field Example: LH, SH, AH

4 4 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips Nxxxx = boolean instruction AND Example: NI, NC, N, NR 8 - Oxxxx = boolean instruction OR Example: OI, OC, O, OR 9 - Xxxxx = boolean instruction Exclusive OR Example: XI, XC, X, XR 10 - Most instructions (except CVD and the STORE ones STC, ST, STH, STCM, STM ): symbol instruction receiver_operand,emitter_operand 11 - STORE and CVD instructions: symbol instruction emitter_operand,receiver_operand

5 5 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips SS-L instructions (only one length) are: MVN, MVC, MVZ, NC, CLC, OC, XC, TR, TRT, ED, EDMK, MVCIN Maximum length of each operand is 256 bytes SS-L1/L2 instructions (2 lengths) are: MVO, PACK, UNPK, ZAP, CP, AP, SP, MP, DP Maximum length for each operand is 16 bytes. 14 – SRP instruction is an exception in the SS group: it has a reference to a length (1st half of the 2nd byte), and a round (in the other half of the 2nd byte)

6 6 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips 4 15 – Use of Boolean instructions: OR = To force bits to 1 (turn ON bits) This can be used to (for instance) : (a) Set program flags to ON (b) Transform lowercase leters into uppercase letters (mask : note in an EBCDIC table that the difference between lowercase and uppercase letters is always x’40’ (b’ ’); turning the 2nd bit ON one can transform a lowercase letter into an uppercase letter. (c) Transform a binary number into the nearest high odd number (turning rightmost bit ON) Example: is decimal 254. Turning rightmost bit ON: it becomes decimal 255

7 7 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips 4 15 – Use of Boolean instructions: AND = Force bits to 0 (turn bits OFF) This can be used to (for instance) : (a) Set program flags to OFF (b) Transform uppercase leters into lowercase letters (mask : note in an EBCDIC table that the difference between uppercase and lowercase letters is always x’40’ (b’ ’); turning the 2nd bit OFF one can transform an uppercase letter into a lowercase letter. (c) Transform a binary number into the nearest low even number (turning rightmost bit OFF) Example: is decimal 255. Turning rightmost bit OFF: it becomes decimal 254

8 8 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips 4 15 – Use of Boolean instructions: XOR (ou exclusivo) = To invert bit setting (turns OFF if it is on, turns ON if it is OFF) This can be used to (for instance) : (a) Inverte program flags (toggle flags) (b) Transform lowercase into uppercase letter and vice-versa (mask ) : letter x1xx xxxx becomes x0xx xxxx letter x0xx xxxx becomes x1xx xxxx (c) Transform binary even numbers into odd numbers and vice- versa: (mask ) : rightmost bit is inverted (d) Exchange the contents of 2 area without a 3rd auxiliary area : XOR A,B + XOR B,A + XOR A,B (e) “Clear” (move binary zeros) an area : XOR A,A

9 9 Alberto Romano Schiesari – Prev.Page Machine Instructions – Hints and Tips 4 16 – Arithmetic and bit shift operations (algebraic / logic operations): Unless othewise stated, these operations are done algebraically. This is always true for decimal packed fields. For binary fixed point numbers (in storage and/or registers) some operations that work algebraically and other operations work logically. Algebraic operations uses: 15-bit binary numbers + 1 bit sign for 2 byte numbers 31-bit binary numbers + 1 bit sign for 4 byte numbers 63-bit binary numbers + 1 bit sign for 8 byte numbers Logical operations assume numbers are always positive and uses: 16-bit binary numbers for 2 byte numbers 32-bit binary numbers for 4 byte numbers 64-bit binary numbers for 8 byte numbers

10 10 Alberto Romano Schiesari – Prev.Page Machine Instructions Machine instructions (alphabetically) A AH AL ALR AP AR BAL BALR BAS BASR BASSM BC BCR BCT BCTR BSM BXH BXLE C CDS CH CL CLC CLCL CLI CLM CLR CP CR CS CVB CVD D DP DR ED EDMK EX IC ICM IPM L LA LCR LH LM LNR LPR LR LTR M MC MH MP MR MVC MVCIN MVCL MVI MVN MVO MVZ N NC NI NR O OC OI OR PACK S SH SL SLA SLDA SLDL SLL SLR SP SPM SR SRA SRDA SRDL SRL SRP ST STC STCK STCM STH STM SVC TM TR TRT TS UNPK X XC XI XR ZAP

11 11 Alberto Romano Schiesari – Prev.Page Machine Instructions (Some) Machine instructions (by group) - Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCIN - Register to Storage move : ST, STH, STM, STC, STCM, CVD - Storage to Register move : L, LH, LM, IC, ICM, CVB - Register to Register move : LR, LPR, LNR, LCR, LTR - Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP - Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR - Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL - Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR - Branch : BC, BCR - Loop Control : BCT, BCTR, BXH, BXLE - Edition : ED, EDMK - Byte Translation and test: TR, TRT - Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA - Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC - Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM - Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS

12 12 Alberto Romano Schiesari – Prev.Page Machine Instructions Hints: what instruction do I have to use to move data from a place to another? OriginDestinationInstruction Storage MVC Register LR Storage (zoned)Storage (packed)PACK Storage (packed)Storage (zoned)UNPK (maybe, additionally, MVZ / OI) RegisterStorageST Storage (binary)RegisterL Storage (packed)Register (binary)CVB Register (binary)Storage (packed)CVD (address)RegisterLA [ or L reg,=A(address) ] (address)Storage (contents=address) LA + ST [ or L + ST ]

13 13 Alberto Romano Schiesari – Prev.Page Machine Instructions - A A (ADD) Instruction A adds algebraically the binary number in the 1st operand and the bynary number in a storage field (2nd operand – a full-word). Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after A 5,=F'259' BF.D C0.D A 7,FULL D A 7,4(2,8) 07.FF.FF.FE FF.FF.FF A 7,4(2) 07.FF.FF.FF FF.FF.FF.FF 07.FF.FF.FE FF.FF.FF.FF A 7,4(,8) FF.FF.FF.FF FF.FF.FF.FF FF.FF.FF.FF Machine Instruction Code5A (RX Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0005,0008 Mach.Inst.Summary

14 14 Alberto Romano Schiesari – Prev.Page Machine Instructions - AH AH (Add Halfword) Machine Instruction Code4A (RX Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0005,0008 This instruction adds algebraically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage half-word specified as 2nd operand. Before the operation is executed, the half-word is internally expanded to 32 bits by repeating (to the left) the leftmost bit (sign bit). Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AH 5,=H'259' B.C C.C AH 5,HALF D 01.0D A 01.0D AH 5,4(2,8) (decimal ) (decimal –30584) (decimal ) AH 5,4(2) (decimal ) (decimal ) (decimal ) Mach.Inst.Summary

15 15 Alberto Romano Schiesari – Prev.Page Machine Instructions - AL AL (Add Logical) Machine Instruction Code5E (RX Instruction) Condition code00 Result = 0, sign not lost 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions0005 This instruction adds logically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage full-word specified as 2nd operand. Both numbers are considered as positive 32-bit numbers. Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AL 5,=F'259' AL 5,FULL 00.B0.C4.E B0.C4.E AL 5,4(2,8) 7F.FF.FF.FF AL 5,4(2) FF.FF.FF.FF AL 5,4(,8) Mach.Inst.Summary

16 16 Alberto Romano Schiesari – Prev.Page Machine Instructions - ALR ALR (Add Logical Register) Machine Instruction Code1E (RR Instruction) Condition code00 Result = 0, sign not lost 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible InterruptionsNo interruptions occur This instruction adds logically the contents of two binary numbers, both located in registers. Both numbers are considered as positive 32-bit numbers. Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after ALR 7,12 00.B0.C4.E B0.C4.E ALR 8,8 7F.FF.FF.FF ALR 10,10 FF.FF.FF.FF ALR 10, Mach.Inst.Summary

17 17 Alberto Romano Schiesari – Prev.Page Machine Instructions - AP AP (Add Packed) Machine Instruction CodeFA (SS Instruction – L1 e L2) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A This instruction adds the contents of two packed numbers, both located in storage fields. Both numbers must be in the decimal packed format. Result is stored into 1st operand field. Examples: AP FLDA,FLDB before after FLDB 12.3C 12.3C FLDA C C AP FLDA,FLDA before after FLDA 45.2C 90.4C See more examples following: Mach.Inst.Summary

18 18 Alberto Romano Schiesari – Prev.Page Machine Instructions - AP AP (Add Packed) Machine Instruction CodeFA (SS Instruction – L1 e L2) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after AP HOWMANY,=P'1' F 1C C 1C AP ARL+2(5),ARL+7(2) C 98.7C C 98.7C AP TOTAL,2(3,7) C D C D AP 4(3,8),WALFA F 02.0C C 02.0C AP 7(07,8),14(2,3) C 00.5C C 00.5C AP GRANDTOT,SMALLTOT C C C Mach.Inst.Summary

19 19 Alberto Romano Schiesari – Prev.Page Machine Instructions - AR AR (Add Register) Machine Instruction Code1A (RR Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0008 This instruction adds the contents of two binary numbers, both located in registers. The value of the register 2nd operand is added to the value of the register 1st operand. Result is stored into register 1st operand. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AR 7, FF.FF AR 2, FF.FF FF.FF FF.FE FF.FE Mach.Inst.Summary

20 20 Alberto Romano Schiesari – Prev.Page Machine Instructions – BAL BAL (Branch And Link) Machine Instruction Code45 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BAL instruction is similar to the BALR instruction; the difference is that the address where the branch is to be made to (specified by the 2nd operand) is the instruction address in the base+displacement format (rather than the address in the register as in the BALR instruction). Note that to load the next instruction address (generally used as the return address when branching to execute a routine) BAL loads the last 4 bytes of PSW into 1st operand register. Examples: Mach.Inst.Summary BAL 9,ROUTINE BAL 14,WRTHDR BAL 7,2(5) BAL 7.2(,8) BAL 7,2(5,8)... BAL 9,ROUTINE RETINS EQU * continuation... ROUTINE ST 9,SAVEREG9.... L 9,SAVEREG9 BR 9 BAL loads the address of instruction labeled RETINS into register 9 Save register 9 (return address) into SAVEREG9 Restore return address Goback (to RETINS)

21 21 Alberto Romano Schiesari – Prev.Page Machine Instructions - BALR BALR (Branch And Link Register) Machine Instruction Code05 (RR Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BALR instruction is similar to the BAL instruction; the difference is that the address where branch is to be made to (specified by the 2nd operand) is the value of the register 2nd operand (rather than the address in the base+displacement format as in the BAL instruction). Important: if the second operand is register zero, branch won’t be executed. Note that to load the next instruction address (generally the return address) BALR loads the last 4 bytes of PSW. Examples: Mach.Inst.Summary BALR 3,0 BALR 14,15... LA 15,ROUTINE BALR 14,15 RETINS EQU * continuation... ROUTINE ST 14,SAVEREG.... L 14,SAVEREG BR 14 BALR loads the address of instruction labeled RETINS into register 14 Save register 14 (return address) into SAVEREG Restore return address Goback (to RETINS) LA loads the address of instruction labeled ROUTINE into register 15

22 22 Alberto Romano Schiesari – Prev.Page Machine Instructions - BAS BAS (Branch And Save) Machine Instruction Code4D (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The address of the next instruction (following BAS) is loaded in the register 1st operand: - Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register - Leftmost byte of register 1st operand is set to zero (this is the difference between BAS and BAL) After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand. Example: BAS 14,ROUTINE Mach.Inst.Summary... BAS 9,ROUTINE RETINS EQU * continuation... ROUTINE ST 9,SAVEREG.... L 9,SAVEREG BR 9 BAS loads the address of instruction labeled RETINS into register 9 bytes 1,2,3 and sets byte 0 with zero Save register 9 (return address) into SAVEREG Restore return address Goback (to RETINS)

23 23 Alberto Romano Schiesari – Prev.Page Machine Instructions - BASR BASR (Branch And Save Register) Machine Instruction Code0D (RR Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The address of the next instruction (following BASR) is loaded in the register 1st operand: - Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register - Leftmost byte of register 1st operand is set to zero (this is the difference between BASR and BALR) After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand. Example: BASR 14,15 Mach.Inst.Summary... LA 15,ROUTINE BASR 14,15 RETINS EQU * continuation... ROUTINE ST 14,SAVEREG.... L 14,SAVEREG BR 14 BASR sets register 14 byte 0 with zero and loads the address of instruction labeled RETINS into bytes 1,2,3 of register 14 Save register 14 (return address) into SAVEREG Restore return address Goback (to RETINS) LA loads the address of instruction labeled ROUTINE into register 15

24 24 Alberto Romano Schiesari – Prev.Page Machine Instructions - BASSM BASSM (Branch And Save and Set Mode) Machine Instruction Code0C (RR Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The address of the next instruction (following BASSM) is loaded in the register 1st operand: - Bytes 4, 5, 6 and 7 (last 4 bytes of PSW) are loaded into bytes 0, 1, 2, 3 of the register 1st operand - The value of register 2nd operand is loaded into bytes 4-7 of PSW; it includes leftmost bit (addressing mode) and (next) instruction address. Due to this, the addressing mode is (re)set and a branch is provided. Example: BASSM 14,15 Mach.Inst.Summary LA 15,ROUTINE ICM 15,8,AMODE BASSM 14,15 RETINS EQU * continuation... ROUTINE ST 14,SAVEREG.... L 14,SAVEREG BR 14 BASSM : - Sets register 14 with the address of instruction labeled RETINS into register 14 (taken from PSW) - Loads contents of register 15 into PSW bytes 4-7 (Addressing mode is set [from reg. 15 into PSW] ) and (Branch to ROUTINE is executed) Save register 14 (return address) into SAVEREG Restore return address Goback (to RETINS) LA loads the address of instruction labeled ROUTINE into register 15 ICM sets addressability mode into register 15 bits

25 25 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) There are 2 branch instructions: BC (RX Instruction) and BCR (RR Instruction). But they have many auxiliary mnemonic codes, named extended mnemonic codes. The branch instruction execution is based upon the status of Condition Code (remember? Those 2 bits of PSW) and the mask provided in the instruction (in the left half of its 2nd byte). The 4 different status Condition Code can be are: 00, 01, 10 and 11. For each one of them there is a corresponding code: STATUSCODE The MASK occupies half byte and indicates the condition in which branch MUST be done. It can vary from X'0' to X'F' (decimal 0 up to 15). MASK 8, CC B'00‘ = Branch executed MASK 4, CC B'01‘ = Branch executed MASK 2, CC B'10“ = Branch executed MASK 1, CC B’11’ = Branch executed Mach.Inst.Summary

26 26 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) One can do a combination of the masks, by adding their value. For instance, if mask is X'C', it means that branch must occur if Condition Code is in the 8 or 4 status (8 + 4 = 12). If mask is zero, no branch will be done (NOP/NOPR = no operation). If mask is 15 (X'F') branch will be done no matter waht is the Condition Code setting, because 15 = all codes added ( ); it is an unconditional branch. Branch instructions with masks from 1 to 14 are conditional branches: the branch will only be done if Condition Code is apropriately set. See in the following slide the list of mnemonic codes, the valid masks and the extended mnemonic codes. Mach.Inst.Summary

27 27 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) USE MNEMONIC MEANING BC/BCR EQUIVALENCE General B or BR Allways branches BC 15 or BCR 15 NOP or NOPR Never branches BC 0 or BCR After BH or BHR Branch if A > B BC 2 or BCR 2 Compare BL or BLR Branch if A < B BC 4 or BCR 4 BE or BER Branch if A = B BC 8 or BCR 8 BNH or BNHR Branch if A < or = B BC 13 or BCR 13 BNL or BNLR Branch if A > or = B BC 11 or BCR 11 BNE or BNER Branch if A not = B BC 7 or BCR After BO or BOR Branch if overflow BC 1 or BCR 1 Arithmetic BP or BPR Branch if R > 0 BC 2 or BCR 2 Instructions BM or BMR Branch if R < 0 BC 4 or BCR 4 BZ or BZR Branch if R = 0 BC 8 or BCR 8 BNP or BNPR Branch if R < or = 0 BC 13 or BCR 13 BNM or BNMR Branch if R > or = 0 BC 11 or BCR 11 BNZ or BNZR Branch if R not = 0 BC 7 or BCR After TM BO or BOR Branch if all bits 1 BC 1 or BCR 1 BM or BMR Branch if mixed BC 4 or BCR 4 BZ or BZR Branch if all bits 0 BC 8 or BCR 8 BNO or BNOR Branch if some are 1 BC 14 or BCR Notes: A = 1st operand ; B = 2nd operand ; R = 1st operand after compute Mach.Inst.Summary

28 28 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) The extended menmonic codes are: B = Branch NOP = No Operation BH = Branch High BL = Branch Low BE = Branch Equal BNH = Branch Not High BNL = Branch Not Low BNE = Branch Not Equal BO = Branch If Overflow BP = Branch If Plus BM = Branch If Minus BZ = Branch If Zero BNP = Branch If Not Plus BNM = Branch If Not Minus BNZ = Branch If Not Zero BO = Branch If Ones BM = Branch If Mixed BZ = Branch If Zeros BNO = Branch If Not Ones Mach.Inst.Summary

29 29 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) Machine Instruction Code47 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur This instruction branches (or not) to another instruction. The format is: 1st byte = operation code = 47 2nd byte – 1st half = mask 2nd byte – 2nd half = index register for 2nd operand (branch instruction address) 3rd and 4th byte = 2 bytes with base+displacement of 2nd operand (branch instruction address) 1st operand is the mask; it indicates the condition branch must be done (or not). 2nd operand address is the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BC). If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand. Mach.Inst.Summary

30 30 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) Machine Instruction Code47 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur If one uses the mnemonic code, only one “operand” must be specified: the address to branch to; in this case the mask is implicit in the mnemonic. Example: BC 8,AGAIN is the same as BE AGAIN BE is the same as BC 8. In this case, the branch will be done when condition code is 00. Other examples: B READ same as BC 15,READ BH AGAIN same as BC 2,AGAIN BL COMPARE same as BC 4,COMPARE BE 0(2) same as BC 8,0(2) BE 0(,4) same as BC 8,0(,4) BE 0(2,4) same as BC 8,0(2,4) NOP TOGGLE1 same as BC 0,TOGGLE1 Mach.Inst.Summary

31 31 Alberto Romano Schiesari – Prev.Page Machine Instructions - BC BC (Branch on Condition) Machine Instruction Code47 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur Other examples: B READ same as BC 15,READ BNH LOOP1 same as BC 13,AGAIN BNL LOOP2 same as BC 11,COMPARE BNE 0(2) same as BC 7,0(2) BZ 0(,4) same as BC 8,0(,4) BNZ 0(2,4) same as BC 7,0(2,4) BM BTAB(15) same as BC 4,BTAB(15) Mach.Inst.Summary

32 32 Alberto Romano Schiesari – Prev.Page Machine Instructions - BCR BCR (Branch on Condition Register) Machine Instruction Code07 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BCR instruction is similar to BC instruction. SEE BC INSTRUCTION. The format is: 1st byte = operation code = x’07’ 2nd byte – 1st half = mask (1st operand) 2nd byte – 2nd half = register 2nd operand containing the branch instruction address 1st operand is the mask; it indicates the condition branch must be done (or not). 2nd operand register must contain the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BCR). If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand. If one uses the mnemonic code, only the register 2nd operand must be specified. See examples following: Mach.Inst.Summary

33 33 Alberto Romano Schiesari – Prev.Page Machine Instructions - BCR BCR (Branch on Condition Register) Machine Instruction Code07 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BCR 8,15 is the same as BER 15 BER is the same as BCR 8. In this case, the branch will be done when condition code is 00. Other examples: BCR 2,10 same as BHR 10 BR 7 same as BCR 15,R7 BNER 10 same as BCR 7,R10 BLR 15 same as BCR 4,R15 Mach.Inst.Summary

34 34 Alberto Romano Schiesari – Prev.Page Machine Instructions - BCT BCT (Branch on CounT) Machine Instruction Code46 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur This instruction has 2 operands: the first one is a register, and the second is an instruction address. BCT subtracts 1 from the register 1st operand and after it compares the resulting number with zero.  If result not equal to zero, it will provide a branch to the instruction referred in the 2nd operand  If result is zero the branch won’t be done, processing will resume at the next instruction after BCT. Examples: Mach.Inst.Summary BCT 5,AGAIN BCT 2,0(4,7) BCT 2,0(4) BCT 2,0(,7)... L 11,=F’200’ AGAIN CLC 0(3,5),CODE BE FOUND... BCT 11,AGAIN NOTFND EQU *.... FOUND EQU *... L loads into register 11 number of times loop must be repeated At the end of the set of loop instructions, BCT subtracts 1 from register 11. If zero not reached, branchs to AGAIN. If zero, resumes execution at NOTFND

35 35 Alberto Romano Schiesari – Prev.Page Machine Instructions - BCTR BCTR (Branch on CounT Register) Machine Instruction Code06 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BCTR instruction has 2 operands, both in registers. BCTR subtracts 1 from the register 1st operand and after it compares the resulting number with zero.  If result not = zero, a branch is provided to the instruction whose address is in the register 2nd operand  If result is zero the branch won’t be done, processing will resume at the next instruction after BCTR. IMPORTANT: If 2nd operand is register zero, branch won’t be done; this is often used just to subtract 1 from a register, rather than, for instance, the S or SH instructions. Examples: Mach.Inst.Summary BCTR 2,7 BCTR 4,0 LA 15,AGAIN L 11,=F’200’ AGAIN CLC 0(3,5),CODE BE FOUND... BCTR 11,15 NOTFND EQU *.... FOUND EQU *... L loads into register 11 number of times loop must be repeated At the end of the set of loop instructions, BCTR subtracts 1 from register 11. If zero not reached, branchs to AGAIN. If zero, resumes execution at NOTFND LA loads into register 15 the address of AGAIN instruction

36 36 Alberto Romano Schiesari – Prev.Page Machine Instructions - BSM BSM (Branch and Set Mode) Machine Instruction Code0B (RR Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur (a)The PSW’s addressing mode (bit 32) is loaded into bit 0 of the register 1st operand; bits 1-31 remain unchanged, and after that (b)PSW’s Bytes 4-7 is loaded with contents of register 2nd operand (including addressing mode bit and next instruction address) Thus a addressing mode setting is done followed by a branch. If 2nd operand is register zero, branch is not executed. Example: BSM 14,15 Mach.Inst.Summary

37 37 Alberto Romano Schiesari – Prev.Page Machine Instructions - BXH BXH (Branch on indeX High) Machine Instruction Code86 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur 1st and 2nd operands are registers. 3rd operand is an instruction address. (a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with:  Contents of register 2nd operand (if it is an odd register) or  Contents of register following register 2nd operand (if it is an even register) If the compare result is  Greater than it will be executed a branch to the instruction addressed by 3rd operand  Less than or equal to the branch will not be executed; processing resumes at the instruction following BXH Mach.Inst.Summary

38 38 Alberto Romano Schiesari – Prev.Page Machine Instructions - BXH BXH (Branch on indeX High) Machine Instruction Code86 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur Examples: BXH 7,8,AGAIN R7 = R8 + R7; If R7 > R9 Branch to AGAIN; * If R7 <= R9 next instruction BXH 7,9,AGAIN R7 = R9 + R7; If R7 > R9 Branch to AGAIN; * If R7 <= R9 next instruction BXH 7,9,8(4) R7 = R9 + R7; If R7 > R9 Branch to instruction * whose address is [ (contents R4) + x’008’ ] * If R7 <= R9 next instruction Mach.Inst.Summary

39 39 Alberto Romano Schiesari – Prev.Page Machine Instructions - BXH BXH (Branch on indeX High) Machine Instruction Code86 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BXH 7,8,NOTFOUND R7 = R8 + R7; * If R7 > R9 all table already read; end search * If R7 <= R9 table not exhausted; continue search Example: Use in a search loop: R7 = begins with table address; incremented by element table length via R8 R8 = Table element length R9 = Last element address NOTFOUND : all table read, desired item not found. L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH) NEXTITEM pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXH R7,R8,NOTFOUND B NEXTITEM TABLSEEN... Mach.Inst.Summary

40 40 Alberto Romano Schiesari – Prev.Page Machine Instructions - BXLE BXLE (Branch on indeX Less or Equal) Machine Instruction Code87 (RS Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BXLE is similar to BXH instruction; the difference is that the branch is done if the result of the compare is Less or Equal. 1st and 2nd operands are registers. 3rd operand is an instruction address. (a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with:  Contents of register 2nd operand (if it is an odd register) or  Contents of register following register 2nd operand (if it is an even register) If the compare result is  Less or Equal to : it will be executed a branch to the instruction addressed by 3rd operand  Greater than : the branch will not be executed; processing resumes at the instruction following BXLE Mach.Inst.Summary

41 41 Alberto Romano Schiesari – Prev.Page Machine Instructions - BXLE BXLE (Branch on indeX Less or Equal) Machine Instruction Code87 (RS Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur Examples: BXLE 7,8,AGAIN R7 = R8 + R7; If R7 <= R9 Branch to AGAIN; * If R7 > R9 next instruction BXLE 7,9,AGAIN R7 = R9 + R7; If R7 <= R9 Branch to AGAIN; * If R7 > R9 next instruction BXLE 7,9,8(4) R7 = R9 + R7; If R7 <= R9 Branch to instruction * Whose address is [ (contents R4) + x’008’ ] * If R7 > R9 next instruction Mach.Inst.Summary

42 42 Alberto Romano Schiesari – Prev.Page Machine Instructions - BXLE BXLE (Branch on indeX Less or Equal) Machine Instruction Code87 (RS Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur BXLE 7,8,NOTFOUND R7 = R8 + R7; * If R7 <= R9 table not exhausted; continue search * If R7 > R9 all table already read; end search Example: Use in a search loop: R7 = begins with table address; incremented by element table length via R8 R8 = Table element length R9 = Last element address NOTFOUND : all table read, desired item not found L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH) NEXTITEM compare pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXLE R7,R8,NEXTITEM NOTFOUND... TABLSEEN... Mach.Inst.Summary

43 43 Alberto Romano Schiesari – Prev.Page Machine Instructions - C C (Compare) Machine Instruction Code59 (RX Instruction) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after C Possible Interruptions0005 C performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a full-word, the 2nd operand). Example: C 9,CPO C 8,=F'0' C 13,=A(TABLE+430) C 1,2(4) C 1,2(,4) C 1,2(7,4) Mach.Inst.Summary

44 44 Alberto Romano Schiesari – Prev.Page Machine Instructions - CDS CDS (Compare Double and Swap) Machine Instruction CodeBB (RS Instruction) Condition code00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS Possible Interruptions0004,0005,0006 1st and 3rd operands are even registers. They are considered an indication of: 1st operand: double-word composed by R1 and R1+1 3rd operand: double-word composed by R3 and R3+1 2nd operand is an storage field (double-word). Contents of 1st operand (R1 and R1+1) is compared with the contents of the double-word 2nd operand. If they are equal, the contents of the 3rd operand (R3 and R3+1) is stored into the 2nd operand double-word. If they are not equal, the contents of the double-word 2nd operand is loaded into the 1st operand (R1 and R1+1). See the following examples: Mach.Inst.Summary

45 45 Alberto Romano Schiesari – Prev.Page Machine Instructions - CDS CDS (Compare Double and Swap) Machine Instruction CodeBB (RS Instruction) Condition code00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS Possible Interruptions0004,0005,0006 CDS 4,8,DW Before: R4/R5 00.BF.C CC.A0.00 R8/R9 7D.48.C DW 00.BF.C CC.A0.00 After: R4/R5 00.BF.C CC.A0.00 R8/R9 7D.48.C DW 7D.48.C CDS 4,8,DW Before: R4/R5 00.CC.DD.EE.FF.FF.FF.FF R8/R9 7D.48.C DW 00.BF.C CC.A0.00 After: R4/R5 00.BF.C CC.A0.00 R8/R9 7D.48.C DW 00.BF.C CC.A0.00 Mach.Inst.Summary

46 46 Alberto Romano Schiesari – Prev.Page Machine Instructions - CH CH (Compare Halfword) Machine Instruction Code49 (RX Instruction) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CH Possible Interruptions0005 CH performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a half-word, the 2nd operand). To do that, the 2nd operand is expanded (internally in the CPU) to 4 bytes, by repeating (to the left) 16 times the leftmost bit of the half-word. Example: CH 9,FLD 1st operand = R9; 2nd operand = FLD field CH 8,=H'0' 1st operand = R8; 2nd operand = half-word with zeros CH 13,=Y(TAB+430) 1st operand = R13; 2nd operand = half-word with address of TAB+430 CH 1,2(4) 1st operand = R1; 2nd operand = storage half-word which * address = value of index register R4 +0[base register omitted] + x’2’ CH 1,2(,4) 1st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +0[index register omitted] + x’2’ CH 1,2(7,4) 1st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +R7[index register] + x’2’ Mach.Inst.Summary

47 47 Alberto Romano Schiesari – Prev.Page Machine Instructions - CL CL (Compare Logical) Machine Instruction Code55 (RX Instruction) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CL Possible Interruptions0005 The CL instruction compares logically the contents of register 1st operand and the contents of a storage full-word (2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits finish the operation.. Examples: CL 9,CPO 32 bits of register 9 compared with 32 bits of 4-byte CPO CL 8,=F'0' 32 bits of register 8 compared with 32-bit of 4-byte full-word with zero CL 1,2(4) 32 bits of register 1 compared with 4-byte storage field * ( 2nd operand address = contents of index reg. 4 + displacement X’2’ [base reg. omitted = zero = not considered] ) CL 1,2(,4) 32 bits of register 1 compared with 4-byte storage field * ( 2nd operand address = [ index reg. Omitted = zero = not considered] + displacement X’2’ + base reg.4 ) CL 1,2(7,4) 32 bits of register 1 compared with 4-byte field * ( 2nd operand address = contents of index reg. 7 + displacement X’2’ + contents of base reg. 4 ) Mach.Inst.Summary

48 48 Alberto Romano Schiesari – Prev.Page Machine Instructions - CLC CLC (Compare Logical Character) Machine Instruction CodeD5 (SS Instruction – L) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLC Possible Interruptions0005 This instruction compares logically (left to right, one bit at a time) two storage fields. The first not equal couple of bits finish the compare. Examples: CLC CPOA,CPOB Only one length used = length of CPOA (e.g. 100 bytes) CLC AE+78(2),=C'*1' 2-byte (AE+78 and AE+79) storage field is compared with * 2-byte storage field referenced via literal (contents = X’5CF1’) CLC 4(2,7),2(9) 2 bytes field (address = base register 7 + displacement X’4’) * is compared with storage field ( address = base register 9 + displacement X’2’ ) CLC ID,2(7) n-byte storage field ID is compared with n-byte storage field * (address = base register 7 + displacement X’2’ ) CLC 194(5,11),AE+3 5-byte storage field (address = base register 11 + displacement X’C2’) * is compared with 5-byte storage field ( address = AE+3 ) Mach.Inst.Summary

49 49 Alberto Romano Schiesari – Prev.Page Machine Instructions- CLCL CLCL (Compare Logical Character Long) Machine Instruction Code0F (RR Instruction) Condition code00 1st operand = 2nd operand or both operands have zero length. 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Possible Interruptions0005,0006 This instruction compares two storage fields, in a similar way the CLC does. Both 1st and 2nd operands must be even registers. They indicate (each one of them) a pair of even-odd registers. We’ll call them: 1st pair = R1st and R1st+1; 2nd pair = R2nd and R2nd+1 The 1st operand (receiver field) address must be in the last 3 bytes (righmost) of R1st. The 2nd operand (sender field) address must be in the last 3 bytes (righmost) of R2nd. The 1st operand length must be in the last 3 bytes (rightmost) of R1st+1. The 2nd operand length must be in the last 3 bytes (rightmost) of R2nd+1. The leftmost byte of R2nd+1 must have the padding character. The leftmost byte of R1st, the leftmost byte of R2nd and the leftmost byte of R1st+1 are not considered in the operation. Example: CLCL 2,8 R2=1st operand register (dubbed as R1st above); note that R1st+1 = register 3 R8=2nd operand register (dubbed as R2nd above); note that R2nd+1 = register 9 Mach.Inst.Summary

50 50 Alberto Romano Schiesari – Prev.Page Machine Instructions- CLCL CLCL (Compare Logical Character Long) Machine Instruction Code0F (RR Instruction) Condition code00 1st operand = 2nd operand or both operands are zero length. 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Possible Interruptions0005,0006 Compare is done one bit at a time, from left to right. When not 2 bits unequal are found OR when length of greater operand is exhausted compare is finished. If the operands have no equal kengths, the smaller one is extended with the padding character (internally, without any change in the field). If compare is finished due to 2 bits unequal encountered: - From the value in the rightmost 3 bytes of R1st+1 and R2nd+1 is subtracted the amount of equal bytes; if the difference was found with the padding character the rightmost 3 bytes of R1st OR R2nd+1 are zeroed (the ones who have the smallest length). - To the value of the rightmost 3 bytes of R1st and R2nd is added the amount of equal bytes. If both operands are equal (including the padding character, if needed): - The 3 rightmost bytes of R1st+1 AND R2nd+1 are zeroed. - To the 3 rightmost bytes of R1st AND R2nd is added the amount of equal bytes. In both cases : the leftmost byte of R1 and the leftmost byte of R2 are zeroed, and the leftmost byte of R1st+1 and R2nd+1 remain unchanged. Mach.Inst.Summary

51 51 Alberto Romano Schiesari – Prev.Page Machine Instructions- CLCL CLCL (Compare Logical Character Long) Machine Instruction Code0F (RR Instruction) Condition code00 1st operand = 2nd operand or both operands are zero length. 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Possible Interruptions0005,0006 Mach.Inst.Summary Example: LA 2,BUFEROUT LA 3,12000 LA 8,BUFERIN LA 9,20000 ICM 9,B'1000',C' ' AGAIN CLCL 8,9 BE EQUALS DIFFS EQU *... EQUALS EQU *... LA loads into register 2 the BUFEROUT address CLCL executes the compare between a byte field (BUFEROUT) and a byte field (BUFERIN) LA loads into register 3 the BUFEROUT length LA loads into register 8 the BUFERIN address LA loads into register 9 the BUFERIN length ICM inserts padding character into leftmost byte of register 9

52 52 Alberto Romano Schiesari – Prev.Page Machine Instructions - CLI CLI (Compare Logical Immediate) Machine Instruction Code95 (SI Instruction) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLI Possible Interruptions0005 This instruction compares logically (left to right, one bit at a time) two storage fields. The first operand is a “normal” storage field with its address expressed with a base+displacement address. The second operand is also a storage field, but it is located IN the instruction: it is the instruction’s 2nd byte. It’s not necessary to specify its address, only its contents. Examples (note that b1d1d1d1 is the address of the 1st operand, in the base+displacement format): CLI AE+79,C'*' Machine code = 95.5C. b1d1. d1d1 Compare with asterisk CLI 2(5),X'00' Machine code = Compare with binary zeros CLI BYTE,B' ' Machine code = 95.F0. b1d1. d1d1 Compare with character zero CLI NOP+1,240 Machine code = 95.F0. b1d1. d1d1 Compare with character zero Mach.Inst.Summary

53 53 Alberto Romano Schiesari – Prev.Page Machine Instructions - CLM CLM (Compare Logical under Mask) Machine Instruction CodeBD (RS Instruction) Condition code00 Selected bytes are equal, or mask is zero 01 Selected field of the 1st operand is less than 2nd operand 10 Selected field of the 1st operand is greater than 2nd operand 11 Condition code is not set as 11 after CLM Possible Interruptions0005 The contents of register 1st operand is logically compared (left to right, one bit at a time) with the contents of the 2nd operand, based on the control of the mask 3rd operand. The result is reflected in the setting of the condition code. It’s a RS instruction, with the following format: Byte 1= x’BD’ (operation code); Byte 2 = left half = R1 = register 1st operand; right half = M3 =(mask) Bytes 3 and 4 = 2nd operand address (base+displacement) The 4-bit mask, left to right, are related to the 4 bytes of the register 1st operand. The register bytes whose bits in the mask are ON are considered as a contiguous field, and compared with the storage field specified in the 2nd operand (the 2nd operand must have a length equal to the number of bits ON in the mask. The register bytes whose bits in the mask are OFF are not considered in the operation. Example: CLM 5,B'1011',ARCOMP The “field” composed by 1st, 3rd and 4th bytes of register 5 is compared with the 3-byte field named ARCOMP. Mach.Inst.Summary

54 54 Alberto Romano Schiesari – Prev.Page Machine Instructions - CLR CLR (Compare Logical Register) Machine Instruction Code15 (RR Instruction) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLR Possible InterruptionsNo interruptions occur The CLR instruction compares logically the contents of the 2 registers (1st operand and 2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits found finish the operation. Examples: CLR 4,5 32-bit “string” of register 4 compared with 32 bit “string” of register 5 CLR 8,13 32-bit “string” of register 8 compared with 32-bit “string” of rregister 13 Mach.Inst.Summary

55 55 Alberto Romano Schiesari – Prev.Page Machine Instructions - CP CP (Compare Packed) Machine Instruction CodeF9 (SS Instruction – L1 e L2) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CP Possible Interruptions0005,0007 The CP instruction compares the contents of 2 storage fields ( 1st and 2nd operands). Both must be in the decimal packed format, and remain unchanged. The lengths can be different: the values are compared, not the sizes. Examples: CP FLDA,FLDB If FLDA = X’ C’ and FLDB = X’10000C’ * Result is : 1st operand less than 2nd operand CP COUNTLIN,=P'1' If COUNTLIN = X’999999D’ compared with X’1C’ * Result is : 1st operand less than 2nd operand CP 0(5,9),=P'0' Compares contents of 5-byte field at address * (base register 9 + X’0’) with zero CP TOTAL,2(7,9) Compares contents of TOTAL with 7-byte field address (base register 9 + displacement X’2’) Mach.Inst.Summary

56 56 Alberto Romano Schiesari – Prev.Page Machine Instructions - CR CR (Compare Register) Machine Instruction Code19 (RR Instruction) Condition code00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CR Possible InterruptionsNo interruptions occur The CR instruction compares 2 binary numbers within 2 registers (1st and 2nd operands). Both remain unchanged. Examples: CR 4,5 31-bit binary number in register 4 compared with 31-bit binary number in register 5 CR 8,13 31-bit binary number in register 8 compared with 31-bit binary number in register 13 Mach.Inst.Summary

57 57 Alberto Romano Schiesari – Prev.Page Machine Instructions - CS CS (Compare and Swap) Machine Instruction CodeBA (RS Instruction) Condition code00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 10 after CS 11 Condition code is not set as 11 after CS Possible Interruptions0004,0005,0006 1st and 3rd operands are registers. 2nd operand is a storage field (full-word). The contents of the register 1st operand is compared with the 2nd operand full-word. If they are equal, the contents of register 3rd operand is stored in the 2nd operand full-word. If they are unequal the contents of the 2nd operand full-word is loaded into register 1st operand. Examples: CS 5,8,FW Before: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 00.BF.C4.20 After: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 7D.48.C0.00 CS 5,8,FW Before: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 00.FF.EE.DD After: R5 00.FF.EE.DD R8 7D.48.C0.00 FW 00.FF.EE.DD Mach.Inst.Summary

58 58 Alberto Romano Schiesari – Prev.Page Machine Instructions - CVB CVB (ConVert to Binary) Machine Instruction Code4F (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005, 0007, 0009 The decimal packed number within the 8-byte field 2nd operand (normally a double-word – it remains unchanged), is converted to binary and loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVB 8,DOUBLE 12.BC.4F.CA D FF.FF.FC D * 2nd operand = DOUBLE CVB 8,0(5,9) FF.FF.FF.FF C C * 2nd operand address = index register 5 + base register 9 + X’0’ CVB 8,0(,9) FF.FF.FF.FF F FF F * 2nd operand address = index register 0 + base register 9 + X’0’ CVB 8,0(5) FF.FF.FF.FF C FF C * 2nd operand address = index register 5 + base register 0 + X’0’ Mach.Inst.Summary

59 59 Alberto Romano Schiesari – Prev.Page Machine Instructions - CVD CVD (ConVert to Decimal [packed]) Machine Instruction Code4E (RX Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 The binary number within the register 1st operand is converted to decimal packed format and stored into the 8-byte field 2nd operand (normally a double-word). For positive numbers or zero, sign is ‘C’. For negative numbers sign is ‘D’. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVD 8,DOUBLE C * 2nd operand = DOUBLE CVD 8,0(5,9) FF.FF.FF.FF FB.EC.44.CC.F0.F1 FF.FF.FF.FF D * 2nd operand address = index register 5 + base register 9 + X’0’ CVD 8,0(,9) BA.76.FE.54.DC.32.B C * 2nd operand address = index register 0 + base register 9 + X’0’ CVD 8,0(5) AA.AA C AA.AA C * 2nd operand address = index register 5 + base register 0 + X’0’ Mach.Inst.Summary

60 60 Alberto Romano Schiesari – Prev.Page Machine Instructions - D D (Divide) Machine Instruction Code5D (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005,0006,0008 This instruction executes a division between 2 binary numbers. 1st operand indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits. The number within this couple of registers is the dividend. The divisor is the number within the 2nd operand storage field (full-word). After division: -The remainder is stored into the even register from the even-odd couple. - The quotient is stored in the odd register from the even-odd couple. Examples: L 6,=F'0' Dividend: Registers 6-7 together; L 7,=F'257' They have the number 257 D 6,=F'4' Divisor: (literal) with number 4; Quotient: Register 7 = 64; Remainder: Register 6 = 1 * L 10,=F'0' Dividend: Registers together; L 11,=F'17' They have the number 17 D 10,=F'3' Divisor: (literal) with number 3; Quotient: Register 11 = 5; Remainder: Register 10 = 2 * Mach.Inst.Summary

61 61 Alberto Romano Schiesari – Prev.Page Machine Instructions - DP DP (Divide Packed) Machine Instruction CodeFD (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005,0006,0007,000B The DP instruction executes a division between 2 storage fields, both in packed decimal format. 1st operand is the dividend, and 2nd operand is the divisor. After division the quotient and the remainder are stored in the 1st operand storage field. 2nd operand remains unchanged. About the 2nd operand divisor (a) it remains unchanged after division (b) it cannot exceed 8 bytes (c) its length cannot be greater than or equal to the 1st operand length (d) if condition b or c occurs, program will interrupt with code The remainder is stored in the rightmost bytes of the 1st operand, with divisor’s length. Code 000B interruption occurs when:  Quotient’s length is greater than the length available to it in the 1st operand  Dividend has not at least 1 leftmost zero algarism.  Divisor is zero. See the following examples: Mach.Inst.Summary

62 62 Alberto Romano Schiesari – Prev.Page Machine Instructions - DP DP (Divide Packed) Machine Instruction CodeFD (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005,0006,0007,000B Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after DP FLDA,FLDB C 00.2C C.00.0C 00.2C DP FLDA,FLDB C 00.2C C.00.1C 00.2C DP VALUE,=P'5' C 5C C.2C 5C

63 63 Alberto Romano Schiesari – Prev.Page Machine Instructions - DR DR (Divide Register) Machine Instruction Code1D (RR Instruction) Condition codeRemains unchanged Possible Interruptions0006,0009 This instruction executes a division between 2 binary numbers, both in registers. 1st operand must indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits. The number within this couple of registers is the dividend. 2nd operand is the divisor. After division: - The quotient is stored into the odd register - The remainder is stored into the even register - If the remainder and/or quotient are = 0, their sign will be 0; remainder’s sign is the same as dividend’s sign Examples: L 12,=F'2' Divisor: Register 12 with number 2 L 4,=F'0' Dividend: Registers 4-5 together; L 5,=F'257' They have the number 257 DR 4,12 Quotient: Register 5 = 128; Remainder: Register 4 = 1 * L 9,=F'12' Divisor: Register 9 with number 12 L 6,=F'0' Dividend: Registers 6-7 together; L 7,=F'148' They have the number 148 DR 6,9 Quotient: Register 7 = 12; Remainder: Register 6 = 4 Mach.Inst.Summary

64 64 Alberto Romano Schiesari – Prev.Page Machine Instructions - ED ED (Edit) Machine Instruction CodeDE (SS Instruction – L) Condition code00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions0004,0005,0007 Syntax: [symbol] ED receiving_field,sending_field The 1st operand must have been prepared, prior to the edition, with the edition mask (e.g. move the edition mask to the 1st operand of edit instruction). The sending field (2nd operand) is converted from packed decimal to zoned decimal, and stored into the receiving field (1st operand), ovelaying therefore the mask in the 1st operand. Edition means the control and inclusion, if needed, of sign, visual characters (e.g. decimal point, 3- digit separators), and supression of non-significant zeros. One may edit many packed fields in just one execution of ED instruction. The (only) length specified is applied just to the 1st operand. The 2nd operand must be in the decimal packed format. If any byte of the 2nd operand have in his left half the configurations A, B, C, D, E or F, it will occur a program interruption (code 0007). Edit is done left to right. Mach.Inst.Summary

65 65 Alberto Romano Schiesari – Prev.Page Machine Instructions - ED ED (Edit) Machine Instruction CodeDE (SS Instruction – L) Condition code00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions0004,0005,0007 The bytes of mask may have: X'20‘ = digit selector; X’21’ = significance trigger, X’22’ ) = field separator, or any other contents (in this last case, it’s just a character to be inserted for visual pirposes) During edition, each character of the receiving field (mask – 1st operand) may have go into one of the 3 ways:  Remain unchanged  Substituted by an algarism of the sending field (converted to zoned format)  Substituted by the leftmost character of the 1st operand mask (FILLING character). To make the opetion from the 3 alternatives, CPU must analyse the mask, and consider the algarism being edited (is it zero or not?). The process is as follows: Mach.Inst.Summary

66 66 Alberto Romano Schiesari – Prev.Page Machine Instructions - ED ED (Edit) Machine Instruction CodeDE (SS Instruction – L) Condition code00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions0004,0005,0007  The mask’s leftmost byte is analysed; if it is X’20’ or X’21’ it’s assigned as padding character and the edition starts with it.  Each one of the following bytes can have one of the following configurations:  Digit selector (X'20') or S-Trigger (X'21') or Field separator (X'22') or Any other  In the edition, when is detected a X’20’ or X’21’ in the 1st operand, instruction v erifies:  The S-Trigger : significance indicator; it is a CPU flag; it can be ON or OFF.  The digit carresponding at the 2nd operand.  As a result of the verification, the configuration in the mask in the 1st operand will be substituted by the corresponding digit in the 2nd operand converted to zoned (if digit in the 1st operand is X’20’ or X’21’), or by the padding character (if not X’20’ nor X’21’). Mach.Inst.Summary

67 67 Alberto Romano Schiesari – Prev.Page Machine Instructions - ED ED (Edit) Machine Instruction CodeDE (SS Instruction – L) Condition code00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions0004,0005,0007 About the S-trigger:  It is turned OFF (a) at the beginning of the ED execution or (b) after a X’22’ is found in the mask or (c) when a X’A’ or X’C’ or ‘E’ or ‘F’ is found in the right phalf of any byte of the 2nd operand (the packed field being edited)  It is turned ON (a) after a X’21’ is detected in the mask or (b) when a ‘X20’ is detected in the mask WITH its corresponding digit in the sending field being NOT zero. For these 2 cases the right half of the byte in the sending field doesn’t have X’A’ or X’C’ or ‘E’ or ‘F’. About Field separator (X'22') : it identifies fields in a multi-field edition. It is always substituted by the padding character Examples: Mach.Inst.Summary

68 68 Alberto Romano Schiesari – Prev.Page Machine Instructions - ED ED (Edit) Machine Instruction CodeDE (SS Instruction – L) Condition code00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions0004,0005,0007 Note that lowercase b means a (blank) space. MVC WPAREA+5(10),MASK ED WPAREA+5(10),TOTAL. MASK DC X' B202126B2020' Before: TOTAL C WPAREA+5(10) B B b b b b 1 2 3, 4 5 After: TOTAL C WPAREA+5(10) F1.F2.F3.6B.F4.F5 b b b b 1 2 3, 4 5 Other examples: ED 0(5,7),CPO ED ARIMP+17(8),ISDRT ED 4(12,9),2(10) Mach.Inst.Summary

69 69 Alberto Romano Schiesari – Prev.Page Machine Instructions - EDMK EDMK (Edit and Mark) Machine Instruction CodeDF (SS Instruction – L) Condition code00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after EDMK Possible Interruptions0004,0005,0007 This instruction is analog to the ED instruction. It loads into register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the byte in the 1st operand who received the 1st non-zero digit. Note that the address is not loaded when significance is forced (using X'21'). Example: EDMK ARIMP+5(10),TOTAL Mach.Inst.Summary

70 70 Alberto Romano Schiesari – Prev.Page Machine Instructions - EX EX (Execute) Machine Instruction Code44 (RX Instruction) Condition codeThe setting (or not) depends on the executed instruction Possible Interruptions0003,0005,0006 The 2nd operand specifies an instruction address. The instruction it refers to is temporarily (internally in theCPU) modified according to the value of the register specified as 1st operand. With this tomporary change, it is executed. The temporary changing is made applying a boolean OR (mask = rightmost byte of 1st operand register; object = 2nd byte of instruction addressed by 2nd operand). Note that both EX operands remain unchanged. If 1st operand is register 0, OR won’t be done, the instruction will be executed as it is in storage, with no change in the 2nd byte. Example: L 5,=F'22' EX 5,MVC. MVC MVC 0,(0,12),=CL256' ' Move will be executed with length 23 Mach.Inst.Summary

71 71 Alberto Romano Schiesari – Prev.Page Machine Instructions - IC IC (Insert Character) Machine Instruction Code43 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005 The contents of the byte specified in the 2nd operand is inserted into the rightmost byte of the register 1st operand; leftmost 3 bytes remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after IC 4,BYTE C 6B B 6B IC 8,=C'K' C D D2 D2 IC 11,=HL1'125' C 7D C.2C 7D Mach.Inst.Summary

72 72 Alberto Romano Schiesari – Prev.Page Machine Instructions - ICM ICM (Insert Character under Mask) Machine Instruction CodeBF (RS Instruction) Condition code00 All inserted bits are 0, or mask is zero. 01 1st bit of inserted field is st bit of inserted field is 0, and not all inserted bits are zero. 11 Condition code is not set as 11 after ICM. Possible Interruptions0005 The format of this instruction is: 1st byte: X’BF’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register. The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The storage bytes are inserted left to right into the bytes of 1st operand byteswhose bits in the mask are ON. The remaining bytes of the register remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after ICM 5,B'1010',TWOBYTES A.BC 9A.00.BC.67 9A.BC 1st byte from TWOBYTES is inserted into 1st byte of register 5 and 2nd byte from TWOBYTES is inserted into the 3rd byte of register 5. Mach.Inst.Summary

73 73 Alberto Romano Schiesari – Prev.Page Machine Instructions - IPM IPM (Insert Program Mask) Machine Instruction CodeB222 (RR InstructionE) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur Bits (3rd byte) and (4th byte right) of the instruction are ignored. Condition code and program mask (from PSW) are copied into bits 2-3 (condition code) and bits 4-7 (program mask) into the corresponding bits of 1st operand register. Bits 0-1 of the register are zeroed, and bits 8-31 remain unchanged. Example: Suppose PSW with condition code ’01’ and program mask ‘1100’ register 8 before register 8 after IPM 8 C A 1C A Mach.Inst.Summary

74 74 Alberto Romano Schiesari – Prev.Page Machine Instructions - L L (Load) Machine Instruction Code58 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005 The contents of the field specified as 2nd operand (remains unchanged and) is loaded into the register 1st operand. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after L 7,FULL FE.DC.BA L 14,SALVA FF.FF.FF.FD FF.FF.FF.FD FF.FF.FF.FD L 11,=F'125' D D D Other examples: L 8,0(10) L 8,0(,11) L 8,0(10,11) L 5,=F'200' Mach.Inst.Summary

75 75 Alberto Romano Schiesari – Prev.Page Machine Instructions - LA LA (Load Address) Machine Instruction Code41 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example: Suppose the registers with the values shown bellow (for symbol references register 3 is supposed to be the base register for the referenced fileds, and the displacements are just for example purposes; ) register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5,TABLE A.C2 00.0B not used 00.0B B not used LA 5,FLD F A not used 00.A0.0F A not used LA 5,FLD+17(9) F A A0.0F A LA 5,2(9,3) A A A LA 5, C8 not used not used C8 not used not used Mach.Inst.Summary

76 76 Alberto Romano Schiesari – Prev.Page Machine Instructions - LA LA (Load Address) Machine Instruction Code41 (RX Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example: Suppose the registers with the values shown bellow register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5, F.FF not used not used F.FF not used not used LA 5,4095(3) F.FF 00.0A not used 00.0A.8F.FF 00.0A not used LA 5,4095(3,9) F.FF 00.0A A A Mach.Inst.Summary

77 77 Alberto Romano Schiesari – Prev.Page Machine Instructions - LCR LCR (Load Complement Register) Machine Instruction Code13 (RR Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0008 The binary number in the register 2nd operand is complemented and stored into the register 1st operand. If the number is positive, it becomes negative; if it is negative it becomes positive. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LCR 4, FF.FF.FF.FC FF.FF.FF.FC LCR 4, FF.FF.FF.FE Mach.Inst.Summary

78 78 Alberto Romano Schiesari – Prev.Page Machine Instructions - LH LH (Load Halfword) Machine Instruction Code48 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005 The 2-byte field specified as 2nd operand (remains unchanged and) is loaded into the rightmost 2 bytes of the register 1st operand. The leftmost bit of the storage field is used to fill the leftmost 2 bytes of the register 1st operand: it is expanded / copied to all bits of the first 2 bytes of the register. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after LH 5,FLD A.B4 FF.FF.8A.B4 8A.B4 LH 8,HWORD FF.FF.FF.FF 7A.B A.B4 7A.B4 More examples: LH 7,HALF LH 8,0(10) LH 8,0(,11) LH 8,0(10,11) LH 8,=H'200' Mach.Inst.Summary

79 79 Alberto Romano Schiesari – Prev.Page Machine Instructions - LM LM (Load Multiple) This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field. It loads the contents of the storage field 2nd perand into the registers specified as a range by the 1st and 3rd operands. The length of the field depends on how many registers must be loaded. To load 2 registers, the area must have 8 bytes; to load 3 registers, the area must have 12 bytes, and so on. Example: LM 14,1,SAVEAREA Reg. 14 Reg.15 Reg.0 Reg.1 | SAVEAREA | SAVEAREA = 16 bytes (bytes 0-3 = contents loaded into register 14; bytes 4-7 = contents loaded into register 15; bytes 8-11 = contents loaded into register 0; bytes = contents loaded into register 1) Another example: LM 1,7,2(10) Machine Instruction Code98 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005 Mach.Inst.Summary

80 80 Alberto Romano Schiesari – Prev.Page Machine Instructions - LNR LNR (Load Negative Register) Machine Instruction Code11 (RR Instruction) Condition code00 Result = 0 01 Result < 0 10 Condition code is not set as 10 after LNR 11 Condition code is not set as 11 after LNR Possible InterruptionsNo interruptions occur The binary number of the 2nd operand is converted to negative and loaded into the register 1st operand. Negative numbers and zero remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LNR 4, FF.FF.FF.FC FF.FF.FF.FE FF.FF.FF.FC LNR 4, FF.FF.FF.FE LNR 4, Mach.Inst.Summary

81 81 Alberto Romano Schiesari – Prev.Page Machine Instructions - LPR LPR (Load Positive Register) Machine Instruction Code10 (RR Instruction) Condition code00 Result = 0 01 Condition code is not set as 1 after LPR. 10 Result > 0 11 Overflow Possible Interruptions0008 The binary number of the 2nd operand converted to positive and loaded into the register 1st operand. Positive numbers and zero remain unchanged. The overflow occurs when the maximum negative value is converted to positive; in this case, the number remains unchanged. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LPR 4, FF.FF.FF.FC FF.FF.FF.FC LPR 4, LPR 4, FF Mach.Inst.Summary

82 82 Alberto Romano Schiesari – Prev.Page Machine Instructions - LR LR (Load Register) Machine Instruction Code18 (RR Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The contents of the register 2nd operand is loaded into the register 1st operand. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LR 4, FF.FF.FF.FC FF.FF.FF.FC FF.FF.FF.FC LR 4, LR 4, Mach.Inst.Summary

83 83 Alberto Romano Schiesari – Prev.Page Machine Instructions - LTR LTR (Load and Test Register) Machine Instruction Code12 (RR Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after LTR Possible InterruptionsNo interruptions occur The contents of register 2nd operand is loaded into the register 1st operand; the condition code is set according to the number loaded. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LTR 4, FF.FF.FF.FC FF.FF.FF.FC FF.FF.FF.FC LTR 4, LTR 4, Mach.Inst.Summary

84 84 Alberto Romano Schiesari – Prev.Page Machine Instructions - M M (Multiply) Machine Instruction Code5C (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005,0006 This instruction multiplies two binary numbers. Register 1st operand must be an even register. The odd register following it must contain the multiplicand. The 2nd operand storage field must contain the multiplier. The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Examples: Register 6 before Register 7 before 2nd operand before Register 6 after Register 7 after 2nd operand after M 6,FLDA [ Multiplicand: Register 7; Multiplier: FLDA; Result: Registers 6 and 7 together ] A M 6,=F'256' Multiplicand: Register 7; Multiplier: 256; Result: Registers 6 and 7 together FF FC FF M 6,4(2,8) Multiplicand: Register 7; Multiplier address: Index reg 2 + Base reg 8 + X’4’; Result: Registers 6 and 7 together A A Mach.Inst.Summary

85 85 Alberto Romano Schiesari – Prev.Page More examples: Register 6 before Register 7 before 2nd operand before Register 6 after Register 7 after 2nd operand after M 6,4(2) Multiplicand: Register 7; Multiplier address: Reg index 2 [ + Reg base 0 ] + X’4’; Result: Registers 6 and 7 together C M 6,FLD+4(1) Multiplicand: Reg 7; Multiplier address: Reg index 1 + Base register of FLD+4 + Displacement of FLD+4 + X’4’; Result: Registers 6 and 7 together AA.AA B 6C DE Machine Instructions - M M (Multiply) Machine Instruction Code5C (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005,0006 Mach.Inst.Summary

86 86 Alberto Romano Schiesari – Prev.Page Machine Instructions - MC MC (Monitor Call) Machine Instruction CodeAF (SI Instruction) Condition codeRemains unchanged Possible Interruptions0006,0040 This instruction causes a program interruption if the bit that controls this event is ON in the control register. The control register mask bits are the bits 16-31, end they correspond to the classes 0-15 respectively. The leftmost 4 bits of 2nd operand (immediate) must be zero. The rightmost 4 bits of 2nd operand specify abinary number indicating the desired interruption class. If the corresponding bit in the control register 8is ON, interruption will occur. The 2nd operand address is not a storage address; it is a code to be stored at the storage address X'000156'. If the mask referred to the desired interruption is OFF in the control register 8, instruction processes as a NOP (no operation). Example: MC MONITCOD,7 Mach.Inst.Summary

87 87 Alberto Romano Schiesari – Prev.Page Machine Instructions - MH MH (Multiply Halfword) Machine Instruction Code4C (RX Instruction) Condition codeRemains unchanged Possible Interruptions0005 This instruction multiplies two binary numbers. Register 1st operand must have the multiplicand. The 2nd operand 2-byte storage field must contain the multiplier. The result is a 32-bit fixed-point binary number stored into the register 1st operand. Example: Note that if an overflow occurs (this event is NOT indicated in the condition code) the result sign may not be correct. If result = zero, sign is same as positive number. Examples: Register 1st operand before 2nd operand before Register 1st operand after 2nd operand after MH 5,=H'4' [ Multiplicand: Register 5; Multiplier: literal 4; Result: Register 5 ] A MH 5,=F'2' Multiplicand: Register 5; Multiplier: 0 [ left half of the fullword is taken as the halfword 2nd operand] ; Result: Register [TAKE CARE! right half with not taken! ] Mach.Inst.Summary

88 88 Alberto Romano Schiesari – Prev.Page Machine Instructions - MP MP (Multiply Packed) Machine Instruction CodeFC (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0001,0004,0005,0006,0007 This instruction multiplies two decimal packed numbers, both in storage fields. The result is stored in the 1st operand. 2nd operand can be up to 8 bytes. 2nd operand length must be less than the length of the 1st operand. If 2nd operand length is greater than or equal to the length of the 1st operand, an interruption will occur (code 0006). 1st operand must have as many zero leftmost digits as many digits the 2nd operand has. If it doesn’t happen, interruption 0007 will occur. Example: MP FLDA,FLDB 1st operand before 2nd operand before 1st operand after 2nd operand after C 99.9C C 99.9C C 99.9C (Error! FLDA must have at least 3 leftmost digits with zero) Mach.Inst.Summary

89 89 Alberto Romano Schiesari – Prev.Page Machine Instructions - MR MR (Multiply Register) Machine Instruction Code1C (RR Instruction) Condition codeRemains unchanged Possible Interruptions0006 This instruction multiplies two binary numbers, both in registers. Register 1st operand must be an even register (its contents is not considered in the operation, unless it is [also] the multiplier). The odd register following it must contain the multiplicand. The 2nd operand register must contain the multiplier. The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Example: Register 6 before Register 7 before Register 9 before Register 6 after Register 7 after Register 9 after MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] A MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] AA.BB.CC 00.FF.FF.FF AA.BB FF.FF.FF Mach.Inst.Summary

90 90 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVC MVC (MoVe Character) Machine Instruction CodeD2 (SS Instruction - L) Condition codeRemains unchanged Possible Interruptions0004,0005 This instruction moves (copies) the contents of stotage field to another storage field. The move is done left to right, each byte at a time. Example: MVC FLDA,FLDB before after FLDB C1.C2.C3 C1.C2.C3 FLDA C4.C5.C6 C1.C2.C3 The sending field is the 2nd operand and remains unchanged (unless part of it is at the same time the receiving field = overlapping). The receiving field is the 1st operand. The quantity of bytes moved is determined by the 1st operand length, and both operands are treated with this same length. Examples: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVC WA+5(3),WR E5.C1.D3 E5.C1.D3 E5.C1.D3 MVC WOUT,WIN C C C MVC NICKNAM,=C'SMAIL' C3.D9.E E2.D4.C1.C9.D3 E2.D4.C1.C9.D3 E2.D4.C1.C9.D3 Mach.Inst.Summary

91 91 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVC MVC (MoVe Character) Machine Instruction CodeD2 (SS Instruction - L) Condition codeRemains unchanged Possible Interruptions0004,0005 Mach.Inst.Summary More examples: Move spaces using an auxiliary 5-byte field (a 5-byte literal) : Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVC WA(5),=CL5' ' 5C.5C.5C.5C.5C Alternatively, one may propagate spaces using na auxiliary 1-byte area (the literal) ! - The first MVC moves space to the leftmost byte of WA. - The second one moves 4 bytes; remember that MVC operates one byte at a time. - Follow the 4-byte move, one at a time:  The 1st byte is moved to the 2nd; The 2nd to the 3rd; The 3rd byte to the 4th; The 4th byte to the 5th. Initial MVC for the leftmost byte: MVC WA(1),=C' ' 5C.??.??.??.?? 40 before 40.??.??.??.?? 40 after

92 92 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVC MVC (MoVe Character) Machine Instruction CodeD2 (SS Instruction - L) Condition codeRemains unchanged Possible Interruptions0004,0005 Mach.Inst.Summary Propagation from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th and from 4th to 5th MVC WA+1(4),WA Follow MVC one byte at a time : 1st byte move: 40.??.??.??.?? 40.??.??.??.?? ??.??.?? ??.??.?? 2nd byte move : ??.??.?? ??.??.?? ??.?? ??.?? 3rd byte move : ??.?? ??.?? ?? ?? 4th byte move : ?? ?? Or, better yet: 1st move: 40.??.??.??.?? Before ??.??.?? After 2nd move: ??.??.?? Before ??.?? After 3rd move: ??.?? Before ?? After 4th move: ?? Before After

93 93 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVCIN MVCIN (MoVe Character Inverted) Machine Instruction CodeE8 (SS Instruction – L) Condition codeRemains unchanged Possible Interruptions0001,0004,0005 This instruction moves (copies) the contents of the 2nd operand to the 1st operand (both are storage fields) in an inverted sequence. Note that the 1st operand address is its leftmost byte, and the 2nd operand address is its rightmost byte. Move is done each byte at a time. From the sending field’s view its from right to left. From the receiving field’s view its from left to right. If occurs any overlay (superposition), results are unpredictable. Example: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVCIN A(3),B+2 C4.C5.C6 C1.C2.C3 C3.C2.C1 C1.C2.C3 MVCIN A(5),BETA C4.C5.C6.C7.C8 C1.C2.C3.C4.C5 C5.C4.C3.C2.C1 C1.C2.C3.C4.C5 Mach.Inst.Summary

94 94 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVCL MVCL (MoVe Character Long) Machine Instruction Code0E (RR Instruction) Condition code00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Possible Interruptions0004,0005,0006 Both 1st and 2nd operands must be even registers. They indicate a couple of (even-odd) registers, herein dubbed R1st, R1st+1, R2nd and R2nd+1 This instruction move a storage field (sending field) to another storage field (receiving field), each byte at a time, left to right. Receiving field address must be in the 3 rightmost bytes of R1st. Sending field address must be in the 3 rightmost bytes of R2nd. Receiving field length must be in the 3 rightmost bytes of R1st+1. Sending field length must be in the 3 rightmost bytes of R2nd+1. The leftmost byte of R2nd+1 must contain the padding character. The leftmost byte of R1st is ignored. Same happens with leftmost byte of R1st+1 and leftmost byte of R2nd. Example: MVCL 2,8 See details on following slide. Mach.Inst.Summary

95 95 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVCL MVCL (MoVe Character Long) Machine Instruction Code0E (RR Instruction) Condition code00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Possible Interruptions0004,0005,0006 L 2,=A(RECEIVE) L 3,=A(L’RECEIVE) L 8,=A(SENDING) L 9,=A(L’SENDING) ICM 9,B'1000',=C'*' MVCL 2,8 If sending field wraps from byte to byte 0 (or not), move is executed this way: · The move is executed while the receiving field’s leftmost byte is the same or it’s at the left of the leftmost byte of the sending field OR the move is executed while the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field. · The move is executed while the receiving field’s leftmost byte is the same or is at the left of the leftmost byte of the sending field AND the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field. The (address of the) rightmost byte of the sending field is computed using the length of the receiving or sending field (the smaller). Mach.Inst.Summary

96 96 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVCL MVCL (MoVe Character Long) Machine Instruction Code0E (RR Instruction) Condition code00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Possible Interruptions0004,0005,0006 After move: - The 3 rightmost bytes of R1st+1 (previously with the receiving field length) are set to zero (in fact, at each byte moved, it’s decremented by 1;, it is the amount of remaining bytes to move; at the end of operation remaining bytes to move = zero). To the 3 rightmost bytes of R1st (previously with the receiving field address) is added the length originally specified in R1st+1 (in fact, at each byte moved, it’s incremented by 1 = next receiving byte address). From the 3 rightmost bytes of R2nd+1 (originally with the sending field length) is subtracted the amount of moved bytes (in fact at each byte move it is decremented by 1, it is the amount of remaining bytes to move; at the end remaining bytes to move = zero) - To the 3 rightmost bytes of R2nd (previously with sending field address) it is added the number of bytes moved from sending to receiving field (in fact, at each byte moved, it’s incremented by 1 = next sending byte address) Leftmost R1st byte and leftmost R2nd byte are set to zero, even if move is not done. - Leftmost R1st+1 byte and leftmost R2nd+1 byte remain unchanged. Mach.Inst.Summary

97 97 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVI MVI (MoVe Immediate) Machine Instruction Code92 (SI Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 This instruction moves (copies) a constant 1-byte storage field (2nd operand – immediate operand) to another storage 1-byte field. 2nd operand (mmediate operand) is the sending field and 1st operand is the receiving field. Examples: MVI FLDA,C'*' or MVI FLDA,X'5C' or MVI FLDA,B' ' or MVI FLDA,92 FLDA before Immediate operand before FLDA after Immediate operand after 12 5C 5C 5C Other examples: MVI WAREA+72,C'/' MVI 0(4),X'80' Mach.Inst.Summary

98 98 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVN MVN (MoVe Numerics) Machine Instruction CodeD1 (SS Instruction - L) Condition codeRemains unchanged Possible Interruptions0004,0005 This instruction is similar to MVC, but it moves onle the right half of the bytes. Example: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVN FLDA,FLB A.BC 18.3A.5C 78.9A.BC MVN TOT+4(1),=X'0C' F 0C C 0C Mach.Inst.Summary

99 99 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVO MVO (MoVe with Offset) Machine Instruction CodeF1 (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005 The MVO instruction moves the contents of the 2nd operand storage field to the 1st operand storage field, from righ to left, with displacement of half byte: the right half of the receveing field rightmost byte remains unchanged. The right half of the rightmost byte of sending field is sent to the left half of the rightmost byte of receiving field. And so on. If 1st operand isn’t large enough to receive all digits sent from the 1st operand, the leftmost half-bytes are truncated. If 1st operand is larger than enough to receive all digits sent from the 1st operand, the leftmost half-bytes are filled with X’0’. Examples: MVO RECFLD,SENFLD SENFLD Before SENFLD After RECFLD Before C RECFLD After C Mach.Inst.Summary

100 100 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVO MVO (MoVe with Offset) Machine Instruction CodeF1 (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005 MVO CPOA,CPOB Before After 1º Case CPOB CPOA 78.9A 45.6A 2º Case CPOB AB.72 AB.72 CPOA 4A.5C.B9.FC 00.0A.B7.2C Other examples: MVO ARCALC(5),ARCALC(4) MVO 0(4,7),ARCALC MVO AREA,2(5,8) MVO 2(7,13),19(5,15) Mach.Inst.Summary

101 101 Alberto Romano Schiesari – Prev.Page Machine Instructions - MVZ MVZ (MoVe Zones) Machine Instruction CodeD3 (SS Instruction – L) Condition codeRemains unchanged Possible Interruptions0004,0005 The MVZ instruction is similar to the MVC, but it moves onle the left half of the bytes. Examples: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVZ FLDA,FLB A.BC B6 78.9A.BC MVZ TOT,=4C'0' C5 F0.F0.F0.F0.F0 F1.F2.F3.F4.F5 F0.F0.F0.F0.F0 Mach.Inst.Summary

102 102 Alberto Romano Schiesari – Prev.Page Machine Instructions - N N ([boolean] aNd) Machine Instruction Code54 (RX Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after N 11 Condition code is not set as 11 after N Possible Interruptions0005 This instruction executes a boolean AND between a register (1st operand) and a 4-byte storage field (2nd operand). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: N 13,FIELDX Before After Register 13 B4.EF.2F.A A8 FIELDX FF FF Other examples: N 11,=F'15' N 3,0(4) N 3,0(,4) N 3,0(8,4) Mach.Inst.Summary

103 103 Alberto Romano Schiesari – Prev.Page Machine Instructions - NC NC ([boolean] aNd Character) Machine Instruction CodeD4 (SS Instruction – L) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NC 11 Condition code is not set as 11 after NC Possible Interruptions0004, 0005 This instruction executes a boolean AND between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NC FLDA,FLDB Before After FLDA EF.2F.A A8 FLDB FF FF Mach.Inst.Summary

104 104 Alberto Romano Schiesari – Prev.Page Machine Instructions - NI NI ([boolean] aNd [with] Immediate [operand]) Machine Instruction Code94 (SI Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NI 11 Condition code is not set as 11 after NI Possible Interruptions0004, 0005 This instruction executes a boolean AND between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NI BYTE,X'0F' Before After BYTE B4 04 Immediate Op. 0F 0F Mach.Inst.Summary

105 105 Alberto Romano Schiesari – Prev.Page Machine Instructions - NR NR ([boolean] aNd Register) Machine Instruction Code14 (RR Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NR 11 Condition code is not set as 11 after NR Possible InterruptionsNo interruptions occur This instruction executes a boolean AND between 2 registers. Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NR 5,8 Before After Register 5 B4.EF.2F.A A8 Register FF FF Mach.Inst.Summary

106 106 Alberto Romano Schiesari – Prev.Page Machine Instructions - O O ([boolean] Or) Machine Instruction Code56 (RX Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after O 11 Condition code is not set as 11 after O Possible Interruptions0005 This instruction executes a boolean OR between a register (1st operand) and a 4-byte storage field (2nd operand). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: O 13,FIELDF Before After Register 13 B4.EF.2F.A8 B4.EF.2F.FF FIELDF FF FF Mach.Inst.Summary

107 107 Alberto Romano Schiesari – Prev.Page Machine Instructions - OC OC ([boolean] Or Character) Machine Instruction CodeD6 (SS Instruction – L) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OC 11 Condition code is not set as 11 after OC Possible Interruptions0004, 0005 This instruction executes a boolean OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.FF FLDB FF FF Mach.Inst.Summary

108 108 Alberto Romano Schiesari – Prev.Page Machine Instructions - OI OI ([boolean] Or [with] Immediate [operand]) Machine Instruction Code96 (SI Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OI 11 Condition code is not set as 11 after OI Possible Interruptions0004, 0005 This instruction executes a boolean OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OI BYTE,X'0F' Before After BYTE B4 BF Immediate Operand 0F 0F Mach.Inst.Summary

109 109 Alberto Romano Schiesari – Prev.Page Machine Instructions - OR OR ([boolean] Or Register) Machine Instruction Code16 (RR Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OR 11 Condition code is not set as 11 after OR Possible InterruptionsNo interruptions occur This instruction executes a boolean OR between 2 registers. Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OR 5,8 Before After Reg. 5 B4.EF.2F.A8 B4.EF.2F.FF Reg FF FF Mach.Inst.Summary

110 110 Alberto Romano Schiesari – Prev.Page Machine Instructions - PACK PACK Machine Instruction CodeF2 (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005 The PACK instruction moves a storage zoned field to a storage packed field. The intended function is to convert a numeric field from zoned format to packed format. NO validation is done in the sending field; if its contents is not a valid decimal zoned number, the operation flows normally. 1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left. The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field. After that, each right half byte of the sending field is sent to a half of the receiving field. 2nd operand remains unchanged. If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated. If the receiving field is greater than needed to fit all digits from sending field, the remaining left digits are filled with X’0’. Example: PACK FLDA,FLDB Before After FLDB F1.F2.F3.F4 F1.F2.F3.F4 FLDA 00.B7.2A F Mach.Inst.Summary

111 111 Alberto Romano Schiesari – Prev.Page Machine Instructions - PACK PACK Machine Instruction CodeF2 (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005 PACK FLDA,FLDB 2ºcase FLDB F1.F2.F3.F4 F1.F2.F3.F4 FLDA C9.4A 23.4F 3ºcase FLDB 9A.48.F9.DB 9A.48.F9.DB FLDA 19.B7.DF 0A.89.BD Note the 3rd case. The sending field is not validated about being zoned. The receiving field may not become a valid decimal packed field. More examples: PACK VALUE,READAREA+5(9) PACK HOWMUCH+2(7),2(8,5) PACK 0(10,2),AREA PACK 2(5,7),2(3,8) PACK DOUBLE,DOUBLE PACK BYTE,BYTE Mach.Inst.Summary

112 112 Alberto Romano Schiesari – Prev.Page Machine Instructions - S S (Subtract) Machine Instruction Code5B (RX Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0005,0008 Instruction S subtracts algebraically the binary number in the 4-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after S 5,=F'259' BF.D BE.CF S 7,FULL D FF.FF.FF.0A S 7,4(2,8) 07.FF.FF.FE FF.FF.FD S 7,4(2) 07.FF.FF.FF FF.FF.FD S 7,4(,8) FF.FF.FF.FF FF.FF.FF.FF Mach.Inst.Summary

113 113 Alberto Romano Schiesari – Prev.Page Machine Instructions - SH SH (Subtract Halfword) Machine Instruction Code4B (RX Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0005,0008 Instruction SH subtracts algebraically the binary number in the 2-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SH 5,=H'259' B.C A.C SH 5,HALF D 01.0D FF.FF.FF D SH 5,4(2,8) (decimal ) (decimal –30584) (decimal ) SH 5,4(2) (decimal ) (decimal ) (decimal ) Mach.Inst.Summary

114 114 Alberto Romano Schiesari – Prev.Page Machine Instructions - SL SL (Subtract Logical) Machine Instruction Code5F (RX Instruction) Condition code00 Condition code is not set as 00 after SL 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions0005 Instruction S subtracts logically the binary number in the 4-byte storage field 2nd operand from the binary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SL 5,=F'259' BF.D BE.CF SL 7,FULL D A SL 7,4(2,8) 07.FF.FF.FE FF.FF.FD SL 7,4(2) 07.FF.FF.FF FF.FF.FD Mach.Inst.Summary

115 115 Alberto Romano Schiesari – Prev.Page Machine Instructions - SLA SLA (Shift Left Algebraic) Machine Instruction Code8B (RS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible InterruptionsNo interruptions occur This instruction shifts algebraically, to the left, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted. The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SLA 5,3 Register 5 before Shift FF.80.9A.00 Register 5 after Shift FC.04.D0.00 Mach.Inst.Summary

116 116 Alberto Romano Schiesari – Prev.Page Machine Instructions SLDA SLDA (Shift Left Double Algebraic) Machine Instruction Code8F (RS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0004, 0008 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number). This instruction shifts algebraically, to the left, the bits of the number inside the 2 registers (both treated as only onr number). The sign bit remains unchanged, and the other 63 bits are shifted. The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDA 8,3 Registers 8 and 9 before Shift FF.80.9A.00 Registers 8 and 9 after Shift FC.04.D0.00 Mach.Inst.Summary

117 117 Alberto Romano Schiesari – Prev.Page Machine Instructions - SLDL SLDL (Shift Left Double Logical) Machine Instruction Code8D (RS Instruction) Condition codeRemains unchanged Possible Interruptions0006 The register specified as 1st operand indicates a pair of registers (R1st and R1st+1), taken as a number with 64-bit. This instruction shifts logically, to the left, the bits of the number inside the 2 registers (both treated as only onr number). All 64 bits are shifted (including sign bit). The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDL 8,4 Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A Registers 8 and 9 after Shift 2F.E3.D4.C5 B6.A Mach.Inst.Summary

118 118 Alberto Romano Schiesari – Prev.Page Machine Instructions - SLL SLL (Shift Left Logical) Machine Instruction Code89 (RS Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur The register specified as 1st operand indicates a register, taken as a 32-bit number. This instruction shifts logically, to the left, the bits of the number inside the register. All 32 bits are shifted (including sign bit). The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SLL 5,2 Register 5 before Shift B9.4F.FF.FF Register 5 after Shift E5.3F.FF.FC Mach.Inst.Summary

119 119 Alberto Romano Schiesari – Prev.Page Machine Instructions - SLR SLR (Subtract Logical Register) Machine Instruction Code1F (RR Instruction) Condition code00 Condition code is not set as 00 after SLR 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible InterruptionsNo interruptions occur Instruction SLR subtracts logically the binary number in the register 2nd operand from the binary number in the register 1st operand. Result is stored into 1st operand register. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SLR 7,12 00.B0.C4.E B0.C4.E SLR 10, F.FF.FF.FF Mach.Inst.Summary

120 120 Alberto Romano Schiesari – Prev.Page Machine Instructions - SP SP (Subtract Packed) Machine Instruction CodeFB (SS Instruction – L1 e L2) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A This instruction subtracts the contents of the 2nd operand from the contents of the 1st operand. Both must be storage fields in the decimal packed format. Result is stored into 1st operand field. Examples: SP FLDA,FLDB Before After FLDB 98.7C 98.7C FLDA C C More examples: SP VALUE,VALUE SP TOTAL,=P'1' SP AE+5(8),AE+15(3) SP 0(2,7),4(1,8) Mach.Inst.Summary

121 121 Alberto Romano Schiesari – Prev.Page Machine Instructions - SPM SPM (Set Program Mask) Machine Instruction Code04 (RR Instruction) Condition codeIs set with the contents of bits 2 and 3 of register 1st operand Possible InterruptionsNo interruptions occur This is RR instruction. Its bits are not considered. The contents of 1st operand register is used to take the values of condition code and program mask to store them into PSW. The value of bits 2-3 are set to the condition code. The value of bits 4,5,6 and 7 are set to the PSW program mask. The bits 0-1 and 8-31 are ignored. Example: SPM 8 Mach.Inst.Summary

122 122 Alberto Romano Schiesari – Prev.Page Machine Instructions - SR SR (Subtract Register) Machine Instruction Code1B (RR Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0008 This instruction subtracts the contents of the register 2nd operand from the contents of the register 1st operand. Result is stored into register 1st operand. Then: Minuend : 1st operand ; Subtrahend : 2nd operand ; Result : 1st operand Examples: Suppose the operands with the length and values shown in the “before” line Register 1st operand before Register 2nd operand before Register 1st operand after Register 2nd operand after SR 7, FF.FF FF.FE SR 2, FF.FF FF.FF Mach.Inst.Summary

123 123 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRA SRA (Shift Right Algebraic) Machine Instruction Code8A (RS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after SRA Possible InterruptionsNo interruptions occur This instruction shifts algebraically, to the right, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted. The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SRA 5,3 Register 5 before Shift FF.80.0A.00 Register 5 after Shift 8F.F Mach.Inst.Summary

124 124 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRDA SRDA (Shift Right Double Algebraic) Machine Instruction Code8E (RS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after SRDA Possible Interruptions0006 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number). This instruction shifts algebraically, to the right, the bits of the number inside the 2 registers (both treated as only one number). The sign bit remains unchanged, and the other 63 bits are shifted. The “new” bits to the left are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDA 8,4 Registers 8 and 9 before Shift C FF Registers 8 and 9 after Shift C F Mach.Inst.Summary

125 125 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRDL SRDL (Shift Right Double Logical) Machine Instruction Code8C (RS Instruction) Condition codeRemains unchanged Possible Interruptions0006 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit. This instruction shifts logically, to the right, the bits of the number inside the 2 registers (both treated as only onr number). All 64 bits are shifted (including sign bit). The “new” bits to the left are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDL 8,4 Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A Registers 8 and 9 after Shift 01.2F.E3.D4 C5.B6.A Mach.Inst.Summary

126 126 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRL SRL (Shift Right Logical) The register specified as 1st operand indicates a register, taken as a 32-bit number. This instruction shifts logically, to the right, the bits of the number inside the register. All 32 bits are shifted (including sign bit). The “new” bits to the left are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SRL 5,2 Register 5 before Shift B9.4F.FF.FF Register 5 after Shift 2E.53.FF.FF Machine Instruction Code88 (RS Instruction) Condition codeRemains unchanged Possible InterruptionsNo interruptions occur Mach.Inst.Summary

127 127 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRP SRP (Shift and Round Packed) Machine Instruction CodeF0 (SS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A This is a SS instruction, and its format is the following: 1 byte = operation code 1/2 byte = L1 = 1st operand length - 1 1/2 byte = I3 = 3rd operand (immediate operand) 2 bytes = 1st operand base+displacement address 2 bytes = 2nd operand base+displacement address The 1st operand is a decimal packed storage field; it is shifted based upon the information provided by the 2nd operand: the sense of shift and the amount of digits to be shifted. If shift is to be done rightwards the number is rounded accordingly 3rd operand. Mach.Inst.Summary

128 128 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRP SRP (Shift and Round Packed) Machine Instruction CodeF0 (SS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A The 6 rightmost bits of the number computed as the “address” of 2nd operand are analysed this way:  Leftmost bit indicates the sense of the shift: OFF means shift leftwards; ON means rightwards.  The number composed by the remaining 5 bits indicates the amount of digits to be shifted (if shift rightwards, this number is negative). The round is done by adding the number specified in the 3rd operand to the last shifted digit and, if it is 1, it is added to the number-result after shift. See the following examples: Mach.Inst.Summary

129 129 Alberto Romano Schiesari – Prev.Page Machine Instructions - SRP SRP (Shift and Round Packed) Machine Instruction CodeF0 (SS Instruction) Condition code00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A SRP TOTAL,61,5 TOTAL Before C TOTAL After C (shifts 3 digits to the right) SRP TOTAL,3,0 TOTAL Before C TOTAL After C (shifts 3 digits to the left) These rules make it easier to specify shift sense and amount of digits: Shift leftwards = specify directly the amount of digits SRP TOTAL,3,5 Specify amount in the 2nd operand = shifts “amount” digits to the left (in the example = 3) Shift rightwards = specify (64 – amount of digits) SRP TOTAL,64-3,5 Specify [64-amount] in the 2nd operand = shifts “amount” digits to the right (In the example = 3) Mach.Inst.Summary

130 130 Alberto Romano Schiesari – Prev.Page Machine Instructions - ST ST (Store [from register to storage]) Machine Instruction Code50 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 The register 1st operand (remain unchanged and) is stored into the 2nd operand 4-byte storage field. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after ST 7,FULL FE.DC.BA FE.DC.BA.98 FE.DC.BA.98 ST 14,SAVE FF.FF.FF.FD Other examples: ST 14,FULL+4 ST 14,0(2) ST 14,0(,8) Mach.Inst.Summary

131 131 Alberto Romano Schiesari – Prev.Page Machine Instructions - STC STC (STore Character) Machine Instruction Code42 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 The rightmost byte of register 1st operand (remain unchanged and) is stored into the 2nd operand 1-byte storage field. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STC 7,BYTE FE.DC.BA FE.DC.BA STC 14,0(5) FF Mach.Inst.Summary

132 132 Alberto Romano Schiesari – Prev.Page Machine Instructions - STCK STCK (STore ClocK) Machine Instruction CodeB205 (Instrução S) Condition code00 Clock status allows set 01 Clock status does not allow set 10 Clock status is error 11 Condition code is not set as 11 after STCK Possible Interruptions0004 TOD clock contents is stored into the 8-byte storage field specified in the 2nd operand. Clock must be is set, stop or no-set state. The rightmost bytes are set to zero. If TOD clock is in error state, contents stored is unpredictable. If TOD clock is not operational, all bytes are set to zero. Example: STCK DW Mach.Inst.Summary

133 133 Alberto Romano Schiesari – Prev.Page Machine Instructions - STCM STCM (STore Character under Mask) Machine Instruction CodeBE (RS Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 The format of this instruction is: 1st byte: X’BE’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register. The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The register 1st operand bytes corresponding to the ON bits of the mask are stored into the 2nd operand storage bytes (taken as a contiguous field). 1st operand remains unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STCM 5,B’1010’,TWOBYTES A.BC st byte of register 5 is stored into byte TWOBYTES and 3rd byte of register 5 is stored into byte TWOBYTES+1 Mach.Inst.Summary

134 134 Alberto Romano Schiesari – Prev.Page Machine Instructions - STH STH (STore Halfword) Machine Instruction Code40 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 The rightmost 2 bytes of register 1st operand (remain unchanged and) are stored into the 2nd operand 2-byte storage field. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STH 5,FLD A 8A.B A 00.0A STH 8,HWORD FF.FF.FF.FF FF.FF FF.FF.FF.FF FF.FF Other examples: STH 14,SAVE+18 STH 14,0(2) STH 14,0(,8) STH 14,0(2,8) STH 0,FLD Mach.Inst.Summary

135 135 Alberto Romano Schiesari – Prev.Page Machine Instructions - STM STM (STore Multiple) Machine Instruction Code90 (RX Instruction) Condition codeRemains unchanged Possible Interruptions0004,0005 This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field. It stores the contents of the registers specified as a range by the 1st and 3rd operands into the storage field 2nd perand. The length of the field depends on how many registers must be stored. To store 2 registers, the area must have 8 bytes; to store 3 registers, the area must have 12 bytes, and so on. Example: STM 14,1,SAVE SAVE = 16 bytes (bytes 0-3 = contents of register 14; bytes 4-7 = contents of register ; bytes 8-11 = contents of register 0; bytes = contents of register 1) | SAVE | Reg. 14 Reg.15 Reg.0 Reg.1 Another example: STM 1,7,2(10) Mach.Inst.Summary

136 136 Alberto Romano Schiesari – Prev.Page Machine Instructions - SVC SVC (SuperVisor Call) Machine Instruction Code0A (RR Instruction) Condition code(Remains unchanged in the old PSW) Possible InterruptionsNo interruptions occur The format of this instruction is: 1st byte = operation code; 2nd byte = SVC number This instruction causes a program interruption; this interruption demands CPU to execute a call to the operating system (supervisor) to execute some function. The code (2nd byte – from 0 to 255 – X’00’ up to X’FF’) determines the function to be executed by supervisor. Examples: SVC 0 SVC 7 Some MVS-z/OS SVCs: X'00' (000) = EXCP/XDAP X'13' (019) = OPEN X'01' (001) = WAIT/WAITR/PRTOV X'14' (020) = CLOSE X'02' (002) = POST X'23' (035) = WTO/WTOR X'04' (004) = GETMAIN X'24' (036) = WTL X'05' (005) = FREEMAIN X'5D' (093) = TGET/TPUT X'0B' (011) = TIME X'63' (099) = DYNALLOC X'0D' (013) = ABEND X'6B' (107) = MODESET Mach.Inst.Summary

137 137 Alberto Romano Schiesari – Prev.Page Machine Instructions - TM TM (Test under Mask) Machine Instruction Code91 (SI Instruction) Condition code00 All bits tested are OFF, or mask is zero 01 Some bits tested are ON and others are OFF 10 Condition code is not set as 10 after TM 11 All bits tested are ON Possible Interruptions0005 This instruction tests the bits of the 1-byte storage field specified by the 1st operand, using the mask specified in the 2nd operand (self-defining term). The mask indicates whose bits must be tested. The ON bits in the mask indicate the bits of the stoprage byte to be tested. Test means: is the bit(s) ON or OFF? To reflect the result, condition code is set. Example: TM BYTE,X'9C' Bits 0, 3, 4 and 5 of BYTE are tested More examples: TM KEYAB,B' ' Bits 0, and 7 of KEYAB are tested TM 0(4),240 Bits 4,5,6 and 7 of [base register 4 + displacement X’0’] are tested TM 2(8),X'80' Bit 0 [base register 8 + displacement X’2’] is tested Mach.Inst.Summary

138 138 Alberto Romano Schiesari – Prev.Page Machine Instructions - TR TR (TRanslate) Machine Instruction CodeDC (SS Instruction – L) Condition codeRemains unchanged Possible Interruptions0004,0005 TR instruction moves the contents of 2nd operand to the 1st operand, according to the 1st operand contents. The move is done left to right, each byte at a time, this way:  The contents of each byte of the 1st operand is added (internally) to the 2nd operand address;  The byte at the resulting address is moved (copied) to the byte of the 1st operand.  2nd operand remains unchanged Example: TR ACSD,TABLE Before ACSD FF.05 TABLE C1.48.B9.D7.A1.C3.D9.5C.4B A 256 bytes After ACSD B9.C1.4B.1A.C3 TABLE Remains unchanged More examples : TR 0(5,7),0(10) TR WAREA+7(10),TABASTER TR 2(5,124),FIELD Mach.Inst.Summary

139 139 Alberto Romano Schiesari – Prev.Page Machine Instructions - TR TR (TRanslate) Machine Instruction CodeDC (SS Instruction – L) Condition codeRemains unchanged Possible Interruptions0004,0005 More examples : To translate uppercase EBCDIC letters into lowercase EBCDIC letters; invalid letters are converted to EBCDIC spaces CONVTB1 DC 256C ' ' 256 EBCDIC spaces ORG CONVTB1+C'A' “Return” to Uppercase A DC C'abcdefghi' Substitute original spaces by lowwercase ORG CONVTB1+C'J' “Return” to Uppercase J DC C'jklmnopqr' Substitute original spaces by lowwercase ORG CONVTB1+C'S' “Return” to Uppercase S DC C'stuvwxyz' Substitute original spaces by lowwercase ORG, Return to byte folowing CONVTB1 To translate uppercase EBCDIC letters into uppercase ASCII letters; invalid letters are converted to ASCII spaces CONVTB2 DC 256X'20' 256 ASCII spaces ORG CONVTB2+C'A' “Return” to Uppercase A DC X' ' Substitute EBCDIC value by ASCII value ORG CONVTB1+C'J' “Return” to Uppercase J DC X'4A4B4C4D4E4F505152' Substitute EBCDIC value by ASCII value ORG CONVTB1+C'S' “Return” to Uppercase S DC X' A' Substitute EBCDIC value by ASCII value ORG, Return to byte folowing CONVTB2 Mach.Inst.Summary

140 140 Alberto Romano Schiesari – Prev.Page Machine Instructions - TR TR (TRanslate) Machine Instruction CodeDC (SS Instruction – L) Condition codeRemains unchanged Possible Interruptions0004,0005 More examples : To translate uppercase ASCII letters into uppercase EBCDIC letters; invalid “letters” are converted to EBCDIC spaces CONVTB3 DC 256X ' 40 ' 256 EBCDIC spaces ORG CONVTB2+X ' 41 ' Volta para A maiusculo ASCII DC C ' ABCDEFGHIJKLMNOPQRSTUVWXYZ ' Substitui ASCII value by EBCDIC ORG, Return to byte CONVTB3+256 Mach.Inst.Summary

141 141 Alberto Romano Schiesari – Prev.Page Machine Instructions - TRT TRT (TRanslate and Test) Machine Instruction CodeDD (SS Instruction – L) Condition code00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested. 10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions0005 This instruction tests bytes of the 2nd operand, verifying their status (X’00’ or not). The 1st tested byte NOT in X’00’ ends the instruction execution. 1st operand indicates the 2nd operand bytes to be tested: TRT adds the contents of each byte of the 1st operand to the 2nd operand address (same as TR instruction); the byte at the resulting address is tested with X’00’. When a non-X’00’ byte is detected instruction stores in the register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the 1st operand byte that lead to the 2nd operand non-X’00’ byte; it also stores in register 2 (bits 24-31; bits 0-23 remain unchanged) the contents of the 2nd operand byte not in X’00’. This instruction is generally used to: Mach.Inst.Summary

142 142 Alberto Romano Schiesari – Prev.Page Machine Instructions - TRT TRT (TRanslate and Test) Machine Instruction CodeDD (SS Instruction – L) Condition code00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested. 10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions0005 a) Validate a decimal zoned field (1st operand – only valid digits): TRT CART+9(6),TABNUM BZ NUMÉRIC. TABNUM DC 240X'FF',10X'00',6X'FF' b) Validate an alphanumeric field (1st operand – only uppercase letters and spaces) TRT CART+9(6),TABALFAB BZ FABETIC. TABALFA DC CL256X'FF' ORG TABALFAB+C' ' DC X'00' ORG TABALFAB+C'A' DC 9X'00' ORG TABALFAB+C'J' DC 9X'00' ORG TABALFAB+C'S' DC 8X'00' ORG Mach.Inst.Summary

143 143 Alberto Romano Schiesari – Prev.Page Machine Instructions - TRT TRT (TRanslate and Test) Machine Instruction CodeDD (SS Instruction – L) Condition code00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested. 10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions0005 c) Find a character (* in the example) in a string of characters (e.g. for parsing). TRT 0(80,7),TABASTER BZ NOTASTER register 1 has the byte with *. TABASTER DC 256X'00' ORG TABASTER+C'*' DC X'FF' ORG Mach.Inst.Summary

144 144 Alberto Romano Schiesari – Prev.Page Machine Instructions - TS TS (Test ans Set) Machine Instruction Code93 (Instrução S) Condition code00 Leftmost bit OFF 01 Leftmost bit ON 10 Condition code is not set as 10 after TS 11 Condition code is not set as 11 after TS Possible Interruptions0004,0005 Second byte of instruction is ignored. The leftmost bit of the (only) operand is tested (ON or OFF). After the test all bits of the byte are set to 1 (ON). Condition code is set according to the result of the test. Example: TS BYTE Mach.Inst.Summary

145 145 Alberto Romano Schiesari – Prev.Page Machine Instructions - UNPK UNPK (UNPacK) Machine Instruction CodeF3 (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005 The UNPK instruction moves a storage packed field to a storage zoned field. The intended function is to convert a numeric field from packed format to zoned format. NO validation is done in the sending field; if its contents is not a valid decimal packed number, the operation flows normally. 1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left. The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field. After that, each half byte of the sending field is sent to a right half of a receiving field byte, and the left half is set to X’F’. 2nd operand remains unchanged. If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated. If the receiving field is greater than needed to fit all digits from sending field, the remaining left bytes are filled with X’F0’. Example: UNPK FLDA,FLDB Before After FLDB C C FLDA 92.B8.4C.D0 F2.F3.F4.C5 Mach.Inst.Summary

146 146 Alberto Romano Schiesari – Prev.Page Machine Instructions - UNPK UNPK (UNPacK) Machine Instruction CodeF3 (SS Instruction – L1 e L2) Condition codeRemains unchanged Possible Interruptions0004,0005 More examples: UNPK FLDA,FLDB Before After FLDB 12.3C 12.3C FLDA 92.B8.4C.D0 F0.F1.F2.C3 UNPK WRITAREA+5(12),TOTLIQ UNPK AX2,2(3,7) UNPK 17(10,8),T4B2F+3(5) UNPK 2(13,10),0(5,3) Mach.Inst.Summary

147 147 Alberto Romano Schiesari – Prev.Page Machine Instructions - X X ([boolean] eXclusive or Character) Machine Instruction Code57 (RX Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after X 11 Condition code is not set as 11 after X Possible Interruptions0005 This instruction executes a boolean Exclusive OR between a register (1st operand) and a 4-byte storage field (2nd operand). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: X 13,FIELDF Before After Register 13 B4.EF.2F.A8 B4.EF.2F.57 FIELDF FF FF Mach.Inst.Summary

148 148 Alberto Romano Schiesari – Prev.Page Machine Instructions - XC XC ([boolean] eXclusive or Character) Machine Instruction CodeD7 (SS Instruction – L) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after XC 11 Condition code is not set as 11 after XC Possible Interruptions0004, 0005 This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: XC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.57 FLDB FF Mach.Inst.Summary

149 149 Alberto Romano Schiesari – Prev.Page Machine Instructions - XI XI ([boolean] eXclusive or [with] Immediate [operand]) Machine Instruction Code97 (SI Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OI 11 Condition code is not set as 11 after OI Possible Interruptions0004, 0005 This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: NI BYE,X’0F’ before After BYTE B4 BB Immediate operand 0F 0F Mach.Inst.Summary

150 150 Alberto Romano Schiesari – Prev.Page Machine Instructions - XR XR ([boolean] eXclusive or Register) Machine Instruction Code17 (RR Instruction) Condition code00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after XR 11 Condition code is not set as 11 after XR Possible InterruptionsNo interruptions occur This instruction executes a boolean EXCLUSIVE OR between 2 registers. Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: XR 5,8 Before After Register 5 B4.EF.2F.A8 B4.EF.2F.57 Register FF FF Mach.Inst.Summary

151 151 Alberto Romano Schiesari – Prev.Page Machine Instructions - ZAP ZAP (Zero and Add Packed) Machine Instruction CodeF8 (SS Instruction – L1 e L2) Condition code00 Sender field = 0 01 Sender field < 0 10 Sender field > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A 2nd operand must be a packeddecimal storage field. This instruction zeroes (decimal packed zero) the 1st operand and add the value of the 2st operand to the 1st. 2nd operand remains unchanged. Note that this process is done internally (in the CPU). That’s the reason one can specify the same storage field as 1st and also as 2nd operand; this is often used to test the number (positive, negative or zero) because ZAP sets the condition code When we do ZAP FLD,FLD before zeroing FLD, its contents are internally saved. After being zeroed, when add is done the original contents is available; then it returns to the original value. Mach.Inst.Summary

152 152 Alberto Romano Schiesari – Prev.Page Machine Instructions - ZAP ZAP (Zero and Add Packed) Machine Instruction CodeF8 (SS Instruction – L1 e L2) Condition code00 Se o campo movido = 0 01 Se o campo movido < 0 10 Se o campo movido > 0 11 Overflow Possible Interruptions0001,0004,0005,0007,000A ZAP CPOA,CPOB Before After 1st Case CPOB C C CPOA B4.F8 34.5C 2nd Case CPOB 12.3C 12.3C CPOA 07.B C More examples: ZAP TOTAL,=P'0' ZAP CONTLIN,=P'2' Mach.Inst.Summary

153 153 Alberto Romano Schiesari – Prev.Page Macro Instructions MACRO INSTRUCTIONS

154 154 Alberto Romano Schiesari – Prev.Page Macro Instructions MACRO INSTRUCTIONS Sorry... It’s not in the scope of this course...

155 155 Alberto Romano Schiesari – Prev.Page Appendix - Links LINKS z/Architecture ESA Enterprise Systems Architecture / XC Extended Configuration (para z/VM) High Level Assembler

156 156 Alberto Romano Schiesari – Prev.Page Appendix – Instructions by operation code Some instructions (ordered by operation code) Mnemonic Code Type BALR 05 RR BCTR 06 RR BCR 07 RR SVC 0A RR BSM 0B RR BASSM 0C RR BASR 0D RR MVCL 0E RR CLCL 0F RR LPR 10 RR LNR 11 RR LTR 12 RR LCR 13 RR NR 14 RR CLR 15 RR OR 16 RR XR 17 RR LR 18 RR CR 19 RR AR 1A RR Mnemonic Code Type SR 1B RR MR 1C RR DR 1D RR ALR 1E RR SLR 1F RR STH 40 RX LA 41 RX STC 42 RX IC 43 RX EX 44 RX BAL 45 RX BCT 46 RX BC 47 RX LH 48 RX CH 49 RX AH 4A RX SH 4B RX MH 4C RX BAS 4D RX CVD 4E RX Mnemonic Code Type CVB 4F RX ST 50 RX LAE 51 RX N 54 RX CL 55 RX O 56 RX X 57 RX L 58 RX C 59 RX A 5A RX S 5B RX M 5C RX D 5D RX AL 5E RX SL 5F RX STD 60 RX MXD 67 RX LD 68 RX CD 69 RX AD 6A RX Continues...

157 157 Alberto Romano Schiesari – Prev.Page Appendix – Instructions by operation code Some instructions (ordered by operation code) Mnemonic Code Type SD 6B RX MD 6C RX DD 6D RX AW 6E RX SW 6F RX STE 70 RX LE 78 RX CE 79 RX BXH 86 RS BXLE 87 RS SRL 88 RS SLL 89 RS SRA 8A RS SLA 8B RS SRDL 8C RS SLDL 8D RS SRDA 8E RS SLDA 8F RS STM 90 RS TM 91 SI Mnemonic Code Type MVI 92 SI TS 93 S NI 94 SI CLI 95 SI OI 96 SI XI 97 SI LM 98 RS MC AF SI LRA B1 RX STCK B205 S CS BA RS CDS BB RS CLM BD RS STCM BE RS ICM BF RS MVN D1 SS/L MVC D2 SS/L MVZ D3 SS/L NC D4 SS/L CLC D5 SS/L Mnemonic Code Type OC D6 SS/L XC D7 SS/L TR DC SS/L TRT DD SS/L ED DE SS/L EDMK DF SS/L MVCIN E8 SS/L SRP F0 SS/L1I3 MVO F1 SS/L1L2 PACK F2 SS/L1L2 UNPK F3 SS/L1L2 ZAP F8 SS/L1L2 CP F9 SS/L1L2 AP FA SS/L1L2 SP FB SS/L1L2 MP FC SS/L1L2 DP FD SS/L1L2

158 158 Alberto Romano Schiesari – Prev.Page Appendix – Instructions by mnemonic Some instructions (ordered by mnemonic) Continues... Mnemonic Code Type A 5A RX AD 6A RX AH 4A RX AL 5E RX ALR 1E RR AP FA SS/L1L2 AR 1A RR AW 6E RX BAL 45 RX BALR 05 RR BAS 4D RX BASR 0D RR BASSM 0C RR BC 47 RX BCR 07 RR BCT 46 RX BCTR 06 RR BSM 0B RR BXH 86 RS BXLE 87 RS Mnemonic Code Type C 59 RX CD 69 RX CDS BB RS CE 79 RX CH 49 RX CL 55 RX CLC D5 SS/L CLCL 0F RR CLI 95 SI CLM BD RS CLR 15 RR CP F9 SS/L1L2 CR 19 RR CS BA RS CVB 4F RX CVD 4E RX D 5D RX DD 6D RX DP FD SS/L1L2 DR 1D RR Mnemonic Code Type ED DE SS/L EDMK DF SS/L EX 44 RX IC 43 RX ICM BF RS L 58 RX LA 41 RX LAE 51 RX LCR 13 RR LD 68 RX LE 78 RX LH 48 RX LM 98 RS LNR 11 RR LPR 10 RR LR 18 RR LRA B1 RX LTR 12 RR M 5C RX MC AF SI

159 159 Alberto Romano Schiesari – Prev.Page Appendix – Instructions by mnemonic Some instructions (ordered by mnemonic) Mnemonic Code Type MD 6C RX MH 4C RX MP FC SS/L1L2 MR 1C RR MVC D2 SS/L MVCIN E8 SS/L MVCL 0E RR MVI 92 SI MVN D1 SS/L MVO F1 SS/L1L2 MVZ D3 SS/L MXD 67 RX N 54 RX NC D4 SS/L NI 94 SI NR 14 RR O 56 RX OC D6 SS/L OI 96 SI OR 16 RR Mnemonic Code Type PACK F2 SS/L1L2 S 5B RX SD 6B RX SH 4B RX SL 5F RX SLA 8B RS SLDA 8F RS SLDL 8D RS SLL 89 RS SLR 1F RR SP FB SS/L1L2 SR 1B RR SRA 8A RS SRDA 8E RS SRDL 8C RS SRL 88 RS SRP F0 SS/L1I3 ST 50 RX STC 42 RX STCK B205 S Mnemonic Code Type STCM BE RS STD 60 RX STE 70 RX STH 40 RX STM 90 RS SVC 0A RR SW 6F RX TM 91 SI TR DC SS/L TRT DD SS/L TS 93 S UNPK F3 SS/L1L2 X 57 RX XC D7 SS/L XI 97 SI XR 17 RR ZAP F8 SS/L1L2

160 160 Alberto Romano Schiesari – Prev.Page Appendix – EBCDIC - Some characters Some EBCDIC configurations HEX CARATER 40 Space 60 - hiphen 81aA2sD0D0 } Right brace F00 4B. point 61 / slash 82bA3tD1D1 JF11 4C < less than 6B, comma 83cA4uD2D2 KF22 4D ( Left parenheses 6C % percent 84dA5vD3D3 LF33 4E + Plus sign 6D _ underscore 85eA6wD4D4 MF44 4F | Vertical bar 6E > Greater than 86fA7xD5D5 NF55 50 & Ampersand 6F ? Question mark 87gA8yD6D6 OF66 5A ! Exclamation mark 7A : colon 88hA9zD7D7 PF77 5B $ Dollar sign 7B # number sign 91iC0C0 { Left brace D8D8 QF88 5C * Asterisk at 92jC1C1 AD9D9 RF99 5D ) Right parentheses 7D ' apostrophe 93kC2C2 BE0 \ Backslash 5E ; Semicolon 7E = equals 94lC3C3 CE2S 5F  Not 7F " quotes 95mC4C4 DE3T 96nC5C5 EE4U 97oC6C6 FE5V 98pC7C7 GE6W 99qC8C8 HE7X 9ArC9C9 IE8Y E9Z

161 161 Alberto Romano Schiesari – Prev.Page Appendix – ASCII - Some characters Some ASCII configurations HEXCARATER 20 Space 30 0 zero at 50P60 ` grave accent 70p 21 ! exclamation mark 31 1 one 41A51Q61a71q 22 “ quotes 32 2 two 42B52R62b72r 23 # number 33 3 three 43C53S63c73s 24 $ dollar sign 34 4 four 44D54T64d74t 25 % percent sign 35 5 five 45E55U65e75u 26 & ampersand 36 6 six 46F56V66f76v 27 ‘ apostrophe 37 7 seven 47G57W67g77w 28 ( Left parentheses 38 8 eight 48H58X68h78x 29 ) Right parentheses 39 9 nine 49I59Y69i79y 2A * asterisk 3A : colon 4AJ5AZ6Aj7Az 2B + plus sign 3B ; semicolon 4BK5B [ Left bracket 6Bk7B { Left brace 2C, comma 3C < less than 4CL5C \ back slash 6Cl7C | Vertical Slash 2D - hyphen 3D = equals 4DM5D ] Right bracket 6Dm7D } Right brace 2E. point 3E > greater 4EN5E ^ circumflex 6En7E ~ tilde 2F / slash 3F ? question mark 4FO5F _ (underscore) 6Fo

162 162 Alberto Romano Schiesari – Prev.Page Questions

163 163 Alberto Romano Schiesari – Prev.Page (Q) Exercises 1-12 (Convert decimal to binary) Exercise 1 : (987654) 10 = (?) 2 Exercise 2 : (4095) 10 = (?) 2 Exercise 3 : (7) 10 = (?) 2 Exercise 4 : (1023) 10 = (?) 2 Exercise 5 : (4096) 10 = (?) 2 Exercise 6 : (255) 10 = (?) 2 Exercise 7 : (1024) 10 = (?) 2 Exercise 8 : ( ) 10 = (?) 2 Exercise 9 : (256) 10 = (?) 2 Exercise 10 : (1025) 10 = (?) 2 Exercise 11 : (999888) 10 = (?) 2 Exercise 12 : (65432) 10 = (?) 2

164 164 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Convert decimal to hexadecimal) Exercise 13 : (987654) 10 = (?) 16 Exercise 14 : (4095) 10 = (?) 16 Exercise 15 : (7) 10 = (?) 16 Exercise 16 : (1023) 10 = (?) 16 Exercise 17 : (4096) 10 = (?) 16 Exercise 18 : (255) 10 = (?) 16 Exercise 19 : (1024) 10 = (?) 16 Exercise 20 : ( ) 10 = (?) 16 Exercise 21 : (256) 10 = (?) 16 Exercise 22 : (1025) 10 = (?) 16 Exercise 23 : (999888) 10 = (?) 16 Exercise 24 : (65432) 10 = (?) 16

165 165 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Convert binary to hexadecimal) Exercise 25 : ( ) 2 = (?) 16 Exercise 26 : ( ) 2 = (?) 16 Exercise 27 : (1100) 2 = (?) 16 Exercise 28 : ( ) 2 = (?) 16 Exercise 29 : ( ) 2 = (?) 16 Exercise 30 : ( ) 2 = (?) 16 Exercise 31 : ( ) 2 = (?) 16 Exercise 32 : ( ) 2 = (?) 16 Exercise 33 : ( ) 2 = (?) 16 Exercise 34 : (1) 2 = (?) 16 Exercise 35 : ( ) 2 = (?) 16 Exercise 36 : ( ) 2 = (?) 16

166 166 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Convert hexadecimal to binary) Exercise 37 : (CAFE) 16 = (?) 2 Exercise 38 : (CDF) 16 = (?) 2 Exercise 39 : (1AB4D) 16 = (?) 2 Exercise 40 : (15) 16 = (?) 2 Exercise 41 : (F) 16 = (?) 2 Exercise 42 : (87B54) 16 = (?) 2 Exercise 43 : (1001) 16 = (?) 2 Exercise 44 : (234) 16 = (?) 2 Exercise 45 : (CAD) 16 = (?) 2 Exercise 46 : (7F7) 16 = (?) 2 Exercise 47 : (1990) 16 = (?) 2 Exercise 48 : (33) 16 = (?) 2

167 167 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Convert binary to decimal) Exercise 49 : (11) 2 = (?) 10 Exercise 50 : ( ) 2 = (?) 10 Exercise 51 : ( ) 2 = (?) 10 Exercise 52 : ( ) 2 = (?) 10 Exercise 53 : ( ) 2 = (?) 10 Exercise 54 : ( ) 2 = (?) 10 Exercise 55 : (11) 2 = (?) 10 Exercise 56 : ( ) 2 = (?) 10 Exercise 57 : ( ) 2 = (?) 10 Exercise 58 : ( ) 2 = (?) 10 Exercise 59 : ( ) 2 = (?) 10 Exercise 60 : ( ) 2 = (?) 10

168 168 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Convert hexadecimal to decimal) Exercise 61 : (11) 16 = (?) 10 Exercise 62 : (AAF45) 16 = (?) 10 Exercise 63 : (1B567) 16 = (?) 10 Exercise 64 : (100) 16 = (?) 10 Exercise 65 : (1000) 16 = (?) 10 Exercise 66 : (FF) 16 = (?) 10 Exercise 67 : (FFF) 16 = (?) 10 Exercise 68 : (CDF) 16 = (?) 10 Exercise 69 : (CAFE) 16 = (?) 10 Exercise 70 : (FACA) 16 = (?) 10 Exercise 71 : (DAD0) 16 = (?) 10 Exercise 72 : (F1E2D3C4) 16 = (?) 10

169 169 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Add numbers in binary) Exercise 73 : ( ) 2 + ( ) 2 = (?) 2 Exercise 74 : ( ) 2 + ( ) 2 = (?) 2 Exercise 75 : (1111) 2 + (1) 2 = (?) 2 Exercise 76 : (1111) 2 + (111) 2 = (?) 2 Exercise 77 : (100001) 2 + (11110) 2 = (?) 2 Exercise 78 : ( ) 2 + ( ) 2 = (?) 2 Exercise 79 : ( ) 2 + ( ) 2 = (?) 2 Exercise 80 : ( ) 2 + (101111) 2 = (?) 2 Exercise 81 : (111) 2 + (1111) 2 + (100) 2 = (?) 2 Exercise 82 : (11) 2 + (111) 2 + (1111) 2 + (11111) 2 = (?) 2 Exercise 83 : (1111) 2 + (1001) 2 + (111) 2 + (101) 2 + (11) 2 + (1) 2 = (?) 2 Exercise 84 : (111) 2 + (1000) 2 + (1) 2 + (1100) 2 = (?) 2

170 170 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Subtract numbers in binary) Exercise 85 : ( ) 2 - ( ) 2 = (?) 2 Exercise 86 : ( ) 2 - ( ) 2 = (?) 2 Exercise 87 : (1111) 2 - (1) 2 = (?) 2 Exercise 88 : (1111) 2 - (111) 2 = (?) 2 Exercise 89 : (100001) 2 - (11110) 2 = (?) 2 Exercise 90 : ( ) 2 - ( ) 2 = (?) 2 Exercise 91 : ( ) 2 - ( ) 2 = (?) 2 Exercise 92 : ( ) 2 - ( ) 2 = (?) 2 Exercise 93 : (111) 2 - (1111) 2 = (?) 2 Exercise 94 : (10001) 2 - (111111) 2 = (?) 2 Exercise 95 : (0) 2 - (1) 2 = (?) 2 Exercise 96 : (0) 2 - (10) 2 = (?) 2

171 171 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Add numbers in hexadecimal) Exercise 97 : (F12B) 16 + (321) 16 = (?) 16 Exercise 98 : (1100) 16 + (111) 2 = (?) 16 Exercise 99 : (1000F) 16 + (F0001) 16 = (?) 16 Exercise 100 : (A9B8C7) 16 + (D6E5F4) 16 = (?) 16 Exercise 101 : (CAFE) 16 + (CDF) 16 = (?) 16 Exercise 102 : (B001) 16 + (FD) 16 = (?) 16 Exercise 103 : (999) 16 + (111) 16 = (?) 16 Exercise 104 : (123456) 16 + (789ABC) 16 = (?) 16 Exercise 105 : (FFF) 16 + (EEE) 16 = (?) 16 Exercise 106 : (DDD) 16 + (333) 16 = (?) 16 Exercise 107 : (987AED) 16 + (CF01) 16 = (?) 16 Exercise 108 : (FACA) 16 + (CAFE) 16 = (?) 16

172 172 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Subtract numbers in hexadecimal) Exercise 109 : (F1C5) 16 - (101) 16 = (?) 16 Exercise 110 : (1AD87C) 16 - (FDE9) 2 = (?) 16 Exercise 111 : (112233) 16 - (44556) 16 = (?) 16 Exercise 112 : (AABBCC) 16 - (DDEEF) 16 = (?) 16 Exercise 113 : (F1E2D3) 16 - (C4B5A6) 16 = (?) 16 Exercise 114 : (FF00001) 16 - (10000F) 16 = (?) 16 Exercise 115 : (CAFE) 16 - (FACA) 16 = (?) 16 Exercise 116 : (CDF) 16 - (FDC) 16 = (?) 16 Exercise 117 : (10001) 16 - (20001) 16 = (?) 16 Exercise 118 : (10000) 16 - (FFFE) 16 = (?) 16 Exercise 119 : (0) 16 - (9) 16 = (?) 16 Exercise 120 : (0) 16 - (1A) 16 = (?) 16

173 173 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing binary numbers in bytes) Exercise 121 : (1) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 122 : (-1) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 123 : (10) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 124 : (-10) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 125 : (17) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 126 : (-17) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16

174 174 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing binary numbers in bytes) Exercise 127 : (254) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 128 : (-254) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 129 : (100000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 130 : ( ) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 131 : (32000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 132 : (-32000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16

175 175 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing binary numbers in bytes) Exercise 133 : (63000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 134 : (-63000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 135 : (1010) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 136 : (-1010) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 137 : (4095) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 138 : (-4095) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16

176 176 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing binary numbers in bytes) Exercise 139 : (4097) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 Exercise 140 : (-4097) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16

177 177 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing packed numbers in bytes) Exercise 141 : (1) 10 = (in decimal-packed format) Exercise 142 : (-1) 10 = (in decimal-packed format) Exercise 143 : (10) 10 = (in decimal-packed format) Exercise 144 : (-10) 10 = (in decimal-packed format) Exercise 145 : (17) 10 = (in decimal-packed format) Exercise 146 : (-17) 10 = (in decimal-packed format) Exercise 147 : (254) 10 = (in decimal-packed format) Exercise 148 : (-254) 10 = (in decimal-packed format) Exercise 149 : (100000) 10 = (in decimal-packed format) Exercise 150 : ( ) 10 = (in decimal-packed format) Exercise 151 : (32000) 10 = (in decimal-packed format) Exercise 152 : (-32000) 10 = (in decimal-packed format)

178 178 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing packed numbers in bytes) Exercise 153 : (63000) 10 = (in decimal-packed format) Exercise 154 : (-63000) 10 = (in decimal-packed format) Exercise 155 : (1010) 10 = (in decimal-packed format) Exercise 156 : (-1010) 10 = (in decimal-packed format) Exercise 157 : (4095) 10 = (in decimal-packed format) Exercise 158 : (-4095) 10 = (in decimal-packed format) Exercise 159 : (4097) 10 = (in decimal-packed format) Exercise 160 : (-4097) 10 = (in decimal-packed format)

179 179 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing zoned numbers in bytes) Exercise 161 : (1) 10 = (in decimal-zoned format) Exercise 162 : (-1) 10 = (in decimal-zoned format) Exercise 163 : (10) 10 = (in decimal-zoned format) Exercise 164 : (-10) 10 = (in decimal-zoned format) Exercise 165 : (17) 10 = (in decimal-zoned format) Exercise 166 : (-17) 10 = (in decimal-zoned format) Exercise 167 : (254) 10 = (in decimal-zoned format) Exercise 168 : (-254) 10 = (in decimal-zoned format) Exercise 169 : (100000) 10 = (in decimal-zoned format) Exercise 170 : ( ) 10 = (in decimal-zoned format) Exercise 171 : (32000) 10 = (in decimal-zoned format) Exercise 172 : (-32000) 10 = (in decimal-zoned format)

180 180 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing zoned numbers in bytes) Exercise 173 : (63000) 10 = (in decimal-zoned format) Exercise 174 : (-63000) 10 = (in decimal-zoned format) Exercise 175 : (1010) 10 = (in decimal-zoned format) Exercise 176 : (-1010) 10 = (in decimal-zoned format) Exercise 177 : (4095) 10 = (in decimal-zoned format) Exercise 178 : (-4095) 10 = (in decimal-zoned format) Exercise 179 : (4097) 10 = (in decimal-zoned format) Exercise 180 : (-4097) 10 = (in decimal-zoned format)

181 181 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing character strings in bytes) Exercise 181 : “17“ = (in alphanumeric EBCDIC) Exercise 182 : “-17“ = (in alphanumeric EBCDIC) Exercise 183 : “AF$BD“ = (in alphanumeric EBCDIC) Exercise 184 : “-AF4BD“ = (in alphanumeric EBCDIC) Exercise 185 : “ALBERTO“ = (in alphanumeric EBCDIC) Exercise 186 : “15-9“ = (in alphanumeric EBCDIC) Exercise 187 : “-4095“ = (in alphanumeric EBCDIC) Exercise 188 : “4095“ = (in alphanumeric EBCDIC) Exercise 189 : “*&$//“ = (in alphanumeric EBCDIC) Exercise 190 : “12+3“ = (in alphanumeric EBCDIC) Exercise 191 : “I LOVE HER“ = (in alphanumeric EBCDIC) Exercise 192 : “US$ 2,584.73“ = (in alphanumeric EBCDIC) Exercise 193 : “US$ 1 MILLION“ = (in alphanumeric EBCDIC) Exercise 194 : “PANCHO’S BAR“ = (in alphanumeric EBCDIC)

182 182 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercises must be considered as a program starting at address X’ ’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9. Exercise 195: DC C'123' Exercise 196: DC C'+123' Exercise 197: DC C'-123' Exercise 198: DC C'12.3' Exercise 199: DC C'1AB8' Exercise 200: DC C'01101' Exercise 201: DC C'A+B=C' Exercise 202: DC CL4'A' Exercise 203: DC CL4'ABCDEF' Exercise 204: DC 3CL2'A' Exercise 205: DC 2CL3'A,B' Exercise 206: DC C'ME&&YOU' Exercise 207: DC C'''S MUSIC' Exercise 208: DC Exercise 209: DC CL3'*'

183 183 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 210: DC 3C'*' Exercise 211: DC X'123' Exercise 212: DC X'-123' Exercise 213: DC X'1AB2C3' Exercise 214: DC X'1AB2F4G3' Exercise 215: DC XL3'12D' Exercise 216: DC XL3'AABBCCDDEE' Exercise 217: DC X'1,22,333,4444' Exercise 218: DC XL2'1,22,333' Exercise 219: DC 2X'1,22,333' Exercise 220: DC 2XL2'1,22' Exercise 221: DC B' ' Exercise 222: DC B'1' Exercise 223: DC BL2'1111' Exercise 224: DC B'1, ' Exercise 225: DC BL2'1, '

184 184 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 226: DC 2B'1000' Exercise 227: DC 2BL2'1000' Exercise 228: DC F'10' Exercise 229: DC F'+10' Exercise 230: DC F'-10' Exercise 230: DC F'-15,+16' Exercise 231: DC 2F'22' Exercise 232: DC 2F'33,44' Exercise 233: DC FL3'258' Exercise 234: DC 2FL1'255' Exercise 235: DC F'128000' Exercise 236: DC H'10' Exercise 237: DC H'+10' Exercise 238: DC H'-10' Exercise 239: DC H'-15,+16'

185 185 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 240: DC 2H'22' Exercise 241: DC 2H'33,44' Exercise 242: DC HL3'258' Exercise 243: DC 2HL1'255' Exercise 244: DC H'128000' Exercise 245: DC P'123' Exercise 246: DC P'+123' Exercise 247: DC P'-123' Exercise 248: DC PL4'456' Exercise 249: DC PL1'789' Exercise 250: DC P'1,-22,333,-4444' Exercise 251: DC PL2'1,-22,333,-4444' Exercise 252: DC 3P'0' Exercise 253: DC PL3'0' Exercise 254: DC 2P'1,22,333'

186 186 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 255: DC 2PL2'1,22,333' Exercise 256: DC Z'123' Exercise 257: DC Z'+123' Exercise 258: DC Z'-123' Exercise 259: DC ZL4'456' Exercise 260: DC ZL1'789' Exercise 261: DC Z'1,-22,333,-4444' Exercise 262: DC ZL3'1,-22,333,-4444' Exercise 263: DC 3Z'0' Exercise 264: DC ZL3'0' Exercise 265: DC 2Z'1,22,333' Exercise 266: DC 2ZL3'1,22,333'

187 187 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 267: SIMBZZ DC A(0) Exercise 268: SIMBAA DC A(127) Exercise 269: SIMBBB DC A(X'8000') Exercise 270: SIMBCC DC A(B'1111') Exercise 271: SIMBDD DC A(C'*') Exercise 272: SIMBEE DC A(*) Exercise 273: SIMBFF DS CL17 Exercise 274: SIMBGG DC A(*) Exercise 275: SIMBHH DC A(SIMBGG) Exercise 276: SIMBII DC A(SIMBAA+12) Exercise 277: SIMBJJ DC A(SIMBII-SIMBBB) Exercise 278: SIMBKK DC AL1(*-SIMBKK) Exercise 279: SIMBLL DC 5AL1(*-SIMBLL)

188 188 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 280: SIMBMM DC AL2(3,5,7) Exercise 281: SIMBNN DC A(SIMBII+5*2) Exercise 282: SIMBOO DC A(SIMBNN+X' ') Exercise 283: SIMBPP DC 4AL2(*-SIMBPP) Exercise 284: SIMBQQ DC A(SIMBVV) Exercise 285: SIMBRR DC A(SIMBKK,SIMBJJ) Exercise 286: SIMBSS DC A(SIMBTT+40) Exercise 287: SIMBTT DC A(SIMBUU,*,80) Exercise 288: SIMBUU DC 2A(*-SIMBUU) Exercise 289: SIMBVV DC A(C'AMO') Exercise 290: SIMBWW DC A(X'7FFFFFFF')

189 189 Alberto Romano Schiesari – Prev.Page (Q) Exercises (Representing fields in bytes) Exercise 291: YY1 DC Y(SIMBWW) Exercise 292: YY2 DC Y(10) Exercise 293: YY3 DC Y(L'YY2) Exercise 294: SS1 DC S(SIMBAA) Exercise 295: SS2 DC S(SS1) Exercise 296: SS3 DC S(10) Exercise 297: SS4 DC S(*) Exercise 298: SS5 DC A(125),F'33',C'*',2H'6,18' Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' Exercise 300: LAST DC 256AL1(255+LAST-*)

190 190 Alberto Romano Schiesari – Prev.Page (Q) Exercise 301 (Decoding instructions) Exercise 301 : Decode the following set of instructions; for each one, specify: - Operation code (machine code) - Menmonic Assembler code - Instruction address (suppose 1st instruction at address X’ ’) - Operands (register, base register, index register, displacement; if operand is in storage, compute the operand address; to compute the operand’s addresses suppose the general registers with the following contents: R00= R04= R08= R12=00000C00 R01= R05= R09= R13=00000D00 R02= R06= R10=00000A00 R14=00000E00 R03= R07= R11=00000B00 R15=00000F00 Instructions to decode: 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD

191 191 Alberto Romano Schiesari – Prev.Page Answers

192 192 Alberto Romano Schiesari – Prev.Page (A) Exercises 1-12 (Convert decimal to binary) Exercise 1 : (987654) 10 = ( ) 2 Exercise 2 : (4095) 10 = ( ) 2 Exercise 3 : (7) 10 = (111) 2 Exercise 4 : (1023) 10 = ( ) 2 Exercise 5 : (4096) 10 = ( ) 2 Exercise 6 : (255) 10 = ( ) 2 Exercise 7 : (1024) 10 = ( ) 2 Exercise 8 : ( ) 10 = ( ) 2 Exercise 9 : (256) 10 = ( ) 2 Exercise 10 : (1025) 10 = ( ) 2 Exercise 11 : (999888) 10 = ( ) 2 Exercise 12 : (65432) 10 = ( ) 2

193 193 Alberto Romano Schiesari – Prev.Page (A) Exercises (Convert decimal to hexadecimal) Exercise 13 : (987654) 10 = (F1206) 16 Exercise 14 : (4095) 10 = (FFF) 16 Exercise 15 : (7) 10 = (7) 16 Exercise 16 : (1023) 10 = (3FF) 16 Exercise 17 : (4096) 10 = (1000) 16 Exercise 18 : (255) 10 = (FF) 16 Exercise 19 : (1024) 10 = (400) 16 Exercise 20 : ( ) 10 = (98BD91) 16 Exercise 21 : (256) 10 = (100) 16 Exercise 22 : (1025) 10 = (401) 16 Exercise 23 : (999888) 10 = (F41D0) 16 Exercise 24 : (65432) 10 = (FF98) 16

194 194 Alberto Romano Schiesari – Prev.Page (A) Exercises (Convert binary to hexadecimal) Exercise 25 : ( ) 2 = (7C7521) 16 Exercise 26 : ( ) 2 = (2071FE0FE) 16 Exercise 27 : (1100) 2 = (C) 16 Exercise 28 : ( ) 2 = (7F1) 16 Exercise 29 : ( ) 2 = (AAA8CC7) 16 Exercise 30 : ( ) 2 = (199999) 16 Exercise 31 : ( ) 2 = (8001) 16 Exercise 32 : ( ) 2 = (201) 16 Exercise 33 : ( ) 2 = (1FC07F) 16 Exercise 34 : (1) 2 = (1) 16 Exercise 35 : ( ) 2 = (CAFE) 16 Exercise 36 : ( ) 2 = (56B8E01F8F) 16

195 195 Alberto Romano Schiesari – Prev.Page (A) Exercises (Convert hexadecimal to binary) Exercise 37 : (CAFE) 16 = ( ) 2 Exercise 38 : (CDF) 16 = ( ) 2 Exercise 39 : (1AB4D) 16 = ( ) 2 Exercise 40 : (15) 16 = (10101) 2 Exercise 41 : (F) 16 = (1111) 2 Exercise 42 : (87B54) 16 = ( ) 2 Exercise 43 : (1001) 16 = ( ) 2 Exercise 44 : (234) 16 = ( ) 2 Exercise 45 : (CAD) 16 = ( ) 2 Exercise 46 : (7F7) 16 = ( ) 2 Exercise 47 : (1990) 16 = ( ) 2 Exercise 48 : (33) 16 = (110011) 2

196 196 Alberto Romano Schiesari – Prev.Page (A) Exercises (Convert binary to decimal) Exercise 49 : (11) 2 = (3) 10 Exercise 50 : ( ) 2 = (2175) 10 Exercise 51 : ( ) 2 = (2709) 10 Exercise 52 : ( ) 2 = (24703) 10 Exercise 53 : ( ) 2 = (16259) 10 Exercise 54 : ( ) 2 = (15416) 10 Exercise 55 : (11) 2 = (3) 10 Exercise 56 : ( ) 2 = (510) 10 Exercise 57 : ( ) 2 = ( ) 10 Exercise 58 : ( ) 2 = (4096) 10 Exercise 59 : ( ) 2 = (249) 10 Exercise 60 : ( ) 2 = (32769) 10

197 197 Alberto Romano Schiesari – Prev.Page (A) Exercises (Convert hexadecimal to decimal) Exercise 61 : (11) 16 = (17) 10 Exercise 62 : (AAF45) 16 = (700229) 10 Exercise 63 : (1B567) 16 = (111975) 10 Exercise 64 : (100) 16 = (256) 10 Exercise 65 : (1000) 16 = (4096) 10 Exercise 66 : (FF) 16 = (255) 10 Exercise 67 : (FFF) 16 = (4095) 10 Exercise 68 : (CDF) 16 = (3295) 10 Exercise 69 : (CAFE) 16 = (51966) 10 Exercise 70 : (FACA) 16 = (64202) 10 Exercise 71 : (DAD0) 16 = (56016) 10 Exercise 72 : (F1E2D3C4) 16 = ( ) 10

198 198 Alberto Romano Schiesari – Prev.Page (A) Exercises (Add numbers in binary) Exercise 73 : ( ) 2 + ( ) 2 = ( ) 2 Exercise 74 : ( ) 2 + ( ) 2 = ( ) 2 Exercise 75 : (1111) 2 + (1) 2 = (10000) 2 Exercise 76 : (1111) 2 + (111) 2 = (10110) 2 Exercise 77 : (100001) 2 + (11110) 2 = (111111) 2 Exercise 78 : ( ) 2 + ( ) 2 = ( ) 2 Exercise 79 : ( ) 2 + ( ) 2 = ( ) 2 Exercise 80 : ( ) 2 + (101111) 2 = ( ) 2 Exercise 81 : (111) 2 + (1111) 2 + (100) 2 = (11010) 2 Exercise 82 : (11) 2 + (111) 2 + (1111) 2 + (11111) 2 = (111000) 2 Exercise 83 : (1111) 2 + (1001) 2 + (111) 2 + (101) 2 + (11) 2 + (1) 2 = (101000) 2 Exercise 84 : (111) 2 + (1000) 2 + (1) 2 + (1100) 2 = (11100) 2

199 199 Alberto Romano Schiesari – Prev.Page (A) Exercises (Subtract numbers in binary) Exercise 85 : ( ) 2 - ( ) 2 = ( ) 2 Exercise 86 : ( ) 2 - ( ) 2 = ( ) 2 Exercise 87 : (1111) 2 - (1) 2 = (1110) 2 Exercise 88 : (1111) 2 - (111) 2 = (1000) 2 Exercise 89 : (100001) 2 - (11110) 2 = (11) 2 Exercise 90 : ( ) 2 - ( ) 2 = ( ) 2 Exercise 91 : ( ) 2 - ( ) 2 = ( ) 2 Exercise 92 : ( ) 2 - ( ) 2 = ( ) 2 Exercise 93 : (111) 2 - (1111) 2 = ( ) 2 Exercise 94 : (10001) 2 - (111111) 2 = ( ) 2 Exercise 95 : (0) 2 - (1) 2 = ( ) 2 Exercise 96 : (0) 2 - (10) 2 = ( ) 2

200 200 Alberto Romano Schiesari – Prev.Page (A) Exercises (Add numbers in hexadecimal) Exercise 97 : (F12B) 16 + (321) 16 = (F44C) 16 Exercise 98 : (1100) 16 + (111) 2 = (1211) 16 Exercise 99 : (1000F) 16 + (F0001) 16 = (100010) 16 Exercise 100 : (A9B8C7) 16 + (D6E5F4) 16 = (1809EBB) 16 Exercise 101 : (CAFE) 16 + (CDF) 16 = (D7DD) 16 Exercise 102 : (B001) 16 + (FD) 16 = (B0FE) 16 Exercise 103 : (999) 16 + (111) 16 = (AAA) 16 Exercise 104 : (123456) 16 + (789ABC) 16 = (19BBF12) 16 Exercise 105 : (FFF) 16 + (EEE) 16 = (1EED) 16 Exercise 106 : (DDD) 16 + (333) 16 = (1110) 16 Exercise 107 : (987AED) 16 + (CF01) 16 = (9949EE) 16 Exercise 108 : (FACA) 16 + (CAFE) 16 = (1C5C8) 16

201 201 Alberto Romano Schiesari – Prev.Page (A) Exercises (Subtract numbers in hexadecimal) Exercise 109 : (F1C5) 16 - (101) 16 = (F0C4) 16 Exercise 110 : (1AD87C) 16 - (FDE9) 2 = (19DA93) 16 Exercise 111 : (112233) 16 - (44556) 16 = (CDCDD) 16 Exercise 112 : (AABBCC) 16 - (DDEEF) 16 = (9CDCDD) 16 Exercise 113 : (F1E2D3) 16 - (C4B5A6) 16 = (2D2D2D) 16 Exercise 114 : (FF00001) 16 - (10000F) 16 = (FDFFFF2) 16 Exercise 115 : (CAFE) 16 - (FACA) 16 = (...FFFFD034) 16 Exercise 116 : (CDF) 16 - (FDC) 16 = (...FFFFFD03) 16 Exercise 117 : (10001) 16 - (20001) 16 = (...FFFF0000) 16 Exercise 118 : (10000) 16 - (FFFE) 16 = (2) 16 Exercise 119 : (0) 16 - (9) 16 = (...FFFFFFF7) 16 Exercise 120 : (0) 16 - (1A) 16 = (...FFFFFFE6) 16

202 202 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing binary numbers in bytes) Exercise 121 : (1) 10 = ( ) 2 = (0001) 16 = ( ) 2 = ( ) 16 Exercise 122 : (-1) 10 = ( ) 2 = (FFFF) 16 = ( ) 2 = (FFFFFFFF) 16 Exercise 123 : (10) 10 = ( ) 2 = (000A) 16 = ( ) 2 = ( A) 16 Exercise 124 : (-10) 10 = ( ) 2 = (FFF6) 16 = ( ) 2 = (FFFFFFF6) 16 Exercise 125 : (17) 10 = ( ) 2 = (0011) 16 = ( ) 2 = ( ) 16 Exercise 126 : (-17) 10 = ( ) 2 = (FFEF) 16 = ( ) 2 = (FFFFFFEF) 16

203 203 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing binary numbers in bytes) Exercise 127 : (254) 10 = ( ) 2 = (00FE) 16 = ( ) 2 = (000000FE) 16 Exercise 128 : (-254) 10 = ( ) 2 = (FF02) 16 = ( ) 2 = (FFFFFF02) 16 Exercise 129 : (100000) 10 = (impossible to represent in 2 bytes) = ( ) 2 = (000186A0) 16 Exercise 130 : ( ) 10 = (impossible to represent in 2 bytes) = ( ) 2 = (FFFE7960) 16 Exercise 131 : (32000) 10 = ( ) 2 = (7D00) 16 = ( ) 2 = (00007D00) 16 Exercise 132 : (-32000) 10 = ( ) 2 = (8300) 16 = ( ) 2 = (FFFF8300) 16

204 204 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing binary numbers in bytes) Exercise 133 : (63000) 10 = (impossible to represent in 2 bytes) = ( ) 2 = (FFFFF618) 16 Exercise 134 : (-63000) 10 = (impossible to represent in 2 bytes) = ( ) 2 = (FFFF09E8) 16 Exercise 135 : (1010) 10 = ( ) 2 = (03F2) 16 = ( ) 2 = (000003F2) 16 Exercise 136 : (-1010) 10 = ( ) 2 = (FC0E) 16 = ( ) 2 = (FFFFFC0E) 16 Exercise 137 : (4095) 10 = ( ) 2 = (0FFF) 16 = ( ) 2 = (00000FFF) 16 Exercise 138 : (-4095) 10 = ( ) 2 = (F001) 16 = ( ) 2 = (FFFFF001) 16

205 205 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing binary numbers in bytes) Exercise 139 : (4097) 10 = ( ) 2 = (1001) 16 = ( ) 2 = ( ) 16 Exercise 140 : (-4097) 10 = ( ) 2 = (EFFF) 16 = ( ) 2 = (FFFFEFFF) 16

206 206 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing packed numbers in bytes) Exercise 141 : (1) 10 = [ ] = [ 1C ] Exercise 142 : (-1) 10 = [ } = [ 1D ] Exercise 143 : (10) 10 = [ ] = [ 010C ] Exercise 144 : (-10) 10 = [ ] = [ 10D ] Exercise 145 : (17) 10 = [ ] = [ 017C ] Exercise 146 : (-17) 10 = [ ] = [ 017D ] Exercise 147 : (254) 10 = [ ] = [ 254C ] Exercise 148 : (-254) 10 = [ ] = [ 254D ] Exercise 149 : (100000) 10 = [ ] = [ C ] Exercise 150 : (100000) 10 = [ ] = [ D ] Exercise 151 : (32000) 10 = [ ] = [ 32000C ] Exercise 152 : (-32000) 10 = [ ] = [ 32000D ]

207 207 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing packed numbers in bytes) Exercise 153 : (63000) 10 = [ ] = [ 63000C ] Exercise 154 : (-63000) 10 = [ ] = [ 63000D ] Exercise 155 : (1010) 10 = [ ] = [ 01010C ] Exercise 156 : (-1010) 10 = [ ] = [ 01010D ] Exercise 157 : (4095) 10 = [ ] = [ 04095C ] Exercise 158 : (-4095) 10 = [ ] = [ 04095D ] Exercise 159 : (4097) 10 = [ ] = [ 04097C ] Exercise 160 : (-4097) 10 = [ ] = [ 04097D ]

208 208 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing zoned numbers in bytes) Exercise 161 : (1) 10 = [ ] = [ F1 ] Exercise 162 : (-1) 10 = [ } = [ D1 ] Exercise 163 : (10) 10 = [ ] = [ F1F0 ] Exercise 164 : (-10) 10 = [ ] = [ F1D0 ] Exercise 165 : (17) 10 = [ ] = [ F1F7 ] Exercise 166 : (-17) 10 = [ ] = [ F1D7 ] Exercise 167 : (254) 10 = [ ] = [ F2F5F4 ] Exercise 168 : (-254) 10 = [ ] = [ F2F5D4 ] Exercise 169 : (100000) 10 = [ ] = [ F1F0F0F0F0F0 ] Exercise 170 : ( ) 10 = [ ] = [ F1F0F0F0F0D0 ] Exercise 171 : (32000) 10 = [ ] = [ F3F2F0F0F0 ] Exercise 172 : (-32000) 10 = [ ] = [ F3F2F0F0D0 ]

209 209 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing zoned numbers in bytes) Exercise 173 : (63000) 10 = [ ] = [ F6F3F0F0F0 ] Exercise 174 : (-63000) 10 = [ ] = [ F6F3F0F0D0 ] Exercise 175 : (1010) 10 = [ ] = [ F1F0F1F0 ] Exercise 176 : (-1010) 10 = [ ] = [ F1F0F1D0 ] Exercise 177 : (4095) 10 = [ ] = [ F4F0F9F5 ] Exercise 178 : (-4095) 10 = [ ] = [ F4F0F9D5 ] Exercise 179 : (4097) 10 = [ ] = [ F4F0F9F7 ] Exercise 180 : (-4097) 10 = [ ] = [ F4F0F9D7 ]

210 210 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing character strings in bytes) Exercise 181 : “17“ = [ F1F7 ] Exercise 182 : “-17“ = [ 60F1F7 ] Exercise 183 : “AF$BD“ = [ C1C66BC2C4 ] Exercise 184 : “-AF4BD“ = [ 60C1C6F4C2C4 ] Exercise 185 : “ALBERTO“ = [ C1D3C2C5D9E3D6 ] Exercise 186 : “15-9“ = [ F1F560F9 ] Exercise 187 : “-4095“ = [ 60F4F0F9F5 ] Exercise 188 : “4095“ = [ F4F0F9F5 ] Exercise 189 : “*&$//“ = [ 5C505B6161 ] Exercise 190 : “12+3“ = [ F1F24EF3 ] Exercise 191 : “I LOVE HER“ = [ C940D3D6E5C540C8C5D9 ] Exercise 192 : “US$ 2,584.73“ = [ E4E25B40F26BF5F8F44BF7F3 ] Exercise 193 : “US$ 1 MILLION“ = [ E4E25B40F140D4C9D3D3C9D6D5 ] Exercise 194 : “PANCHO’S BAR“ = [ D7C1C5C3C8D67DE240C2C1D9 ]

211 211 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) Exercises must be considered as a program starting at address X’ ’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9. * Address Contents Exercise 195: DC C'123' 0000 F1.F2.F3 Exercise 196: DC C'+123' E.F1.F2.F3 Exercise 197: DC C'-123' F1.F2.F3 Exercise 198: DC C'12.3' 000B F1.F2.4B.F3 Exercise 199: DC C'1AB8' 000F F1.C1.C2.F8 Exercise 200: DC C'01101' 0013 F0.F1.F1.F0.F1 Exercise 201: DC C'A+B=C' 0018 C1.4E.C2.7E.C3 Exercise 202: DC CL4'A' 001D C Exercise 203: DC CL4'ABCDEF' 0021 C1.C2.C3.C4 Exercise 204: DC 3CL2'A' 0025 C1.40.C1.40.C1.40 Exercise 205: DC 2CL3'A,B' 002B C1.6B.C2.C1.6B.C2 Exercise 206: DC C'ME&&YOU' 0031 D4.C5.50.E8.D6.E4 Exercise 207: DC C'''S MUSIC' D.E2.40.D4.E4.E2.C9.C3 Exercise 208: DC 003F 7C.7C.D6.C9 Exercise 209: DC CL3'*' C.40.40

212 212 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Address Contents Exercise 210: DC 3C'*' C.5C.5C Exercise 211: DC X'123' Exercise 212: DC X'-123' *** error *** Exercise 213: DC X'1AB2C3' 004B 1A.B2.C3 Exercise 214: DC X'1AB2F4G3' *** error *** Exercise 215: DC XL3'12D' 004E D Exercise 216: DC XL3'AABBCCDDEE' 0051 CC.DD.EE Exercise 217: DC X'1,22,333,4444' Exercise 218: DC XL2'1,22,333' 005A Exercise 219: DC 2X'1,22,333' Exercise 220: DC 2XL2'1,22' Exercise 221: DC B' ' Exercise 222: DC B'1' Exercise 223: DC BL2'1111' F Exercise 224: DC B'1, ' FF Exercise 225: DC BL2'1, ' FF

213 213 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Address Contents Exercise 226: DC 2B'1000' 007B Exercise 227: DC 2BL2'1000' 007D (align) Exercise 228: DC F'10' A Exercise 229: DC F'+10' A Exercise 230: DC F'-10' 008C FF.FF.FF.F6 Exercise 230: DC F'-15,+16' 0090 FF.FF.FF.F Exercise 231: DC 2F'22' Exercise 232: DC 2F'33,44' 00A C C Exercise 233: DC FL3'258' 00B Exercise 234: DC 2FL1'255' 00B3 FF.FF 00B (align) Exercise 235: DC F'128000' 00B F4.00 Exercise 236: DC H'10' 00BC 00.0A Exercise 237: DC H'+10' 00BE 00.0A Exercise 238: DC H'-10' 00C0 FF.F6 Exercise 239: DC H'-15,+16' 00C2 FF.F

214 214 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Address Contents Exercise 240: DC 2H'22' 00C Exercise 241: DC 2H'33,44' 00CA C C Exercise 242: DC HL3'258' 00D Exercise 243: DC 2HL1'255' 00D5 FF.FF 00D7 00 (align) Exercise 244: DC H'128000' 00D8 F4.00 Exercise 245: DC P'123' 00DA 12.3C Exercise 246: DC P'+123' 00DC 12.3C Exercise 247: DC P'-123' 00DE 12.3D Exercise 248: DC PL4'456' 00E C Exercise 249: DC PL1'789' 00E4 9C Exercise 250: DC P'1,-22,333,-4444' 00E5 1C.02.2D.33.3C D Exercise 251: DC PL2'1,-22,333,-4444' 00ED 00.1C.02.2D.33.3C.44.4D Exercise 252: DC 3P'0' 00F5 0C.0C.0C Exercise 253: DC PL3'0' 00F C Exercise 254: DC 2P'1,22,333' 00FB 1C.02.2C.33.3C.1C.02.2C.33.3C

215 215 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Address Contents Exercise 255: DC 2PL2'1,22,333' C.02.2C.33.3C 00.1C.02.2C.33.3C Exercise 256: DC Z'123' 0111 F1.F2.C3 Exercise 257: DC Z'+123' 0114 F1.F2.C3 Exercise 258: DC Z'-123' 0117 F1.F2.D3 Exercise 259: DC ZL4'456' 011A F0.F4.F5.C6 Exercise 260: DC ZL1'789' 011E C9 Exercise 261: DC Z'1,-22,333,-4444' 011F F1.F2.D2.F3.F3.C3.F4.F4.F4.D4 Exercise 262: DC ZL3'1,-22,333,-4444' 0129 F0.F0.C1.F0.F2.D2.F3.F3.C3 F4.F4.F4.D4 Exercise 263: DC 3Z'0' 0135 C0.C0.C0 Exercise 264: DC ZL3'0' 0138 F0.F0.F0 Exercise 265: DC 2Z'1,22,333' 013B C1.F2.C2.F3.F3.C3 C1.F2.C2.F3.F3.C3 Exercise 266: DC 2ZL3'1,22,333' 0147 F0.F0.C1.F0.F2.C2.F3.F3.C3 F0.F0.C1.F0.F2.C2.F3.F3.C3

216 216 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Address Contents (align) Exercise 267: SIMBZZ DC A(0) 015C Exercise 268: SIMBAA DC A(127) F Exercise 269: SIMBBB DC A(X'8000') Exercise 270: SIMBCC DC A(B'1111') F Exercise 271: SIMBDD DC A(C'*') 016C C Exercise 272: SIMBEE DC A(*) Exercise 273: SIMBFF DS CL ??.??.??.??.??.??.??.??.?? ??.??.??.??.??.??.??.?? (align) Exercise 274: SIMBGG DC A(*) Exercise 275: SIMBHH DC A(SIMBGG) 018C Exercise 276: SIMBII DC A(SIMBAA+12) C Exercise 277: SIMBJJ DC A(SIMBII-SIMBBB) C Exercise 278: SIMBKK DC AL1(*-SIMBKK) Exercise 279: SIMBLL DC 5AL1(*-SIMBLL)

217 217 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Endereço Conteúdo Exercise 280: SIMBMM DC AL2(3,5,7) 019E Exercise 281: SIMBNN DC A(SIMBII+5*2) 01A A Exercise 282: SIMBOO DC A(SIMBNN+X' ') 01A A4 Exercise 283: SIMBPP DC 4AL2(*-SIMBPP) 01AC Exercise 284: SIMBQQ DC A(SIMBVV) 01B D8 Exercise 285: SIMBRR DC A(SIMBKK,SIMBJJ) 01B Exercise 286: SIMBSS DC A(SIMBTT+40) 01C EC Exercise 287: SIMBTT DC A(SIMBUU,*,80) 01C D C Exercise 288: SIMBUU DC 2A(*-SIMBUU) 01D Exercise 289: SIMBVV DC A(C'AMO') 01D8 00.C1.D4.D6 Exercise 290: SIMBWW DC A(X'7FFFFFFF') 01DC 7F.FF.FF.FF

218 218 Alberto Romano Schiesari – Prev.Page (A) Exercises (Representing fields in bytes) * Address Contents Exercise 291: YY1 DC Y(SIMBWW) 01E0 01.DC Exercise 292: YY2 DC Y(10) 01E2 00.0A Exercise 293: YY3 DC Y(L'YY2) 01E Exercise 294: SS1 DC S(SIMBAA) 01E Exercise 295: SS2 DC S(SS1) 01E8 91.E6 Exercise 296: SS3 DC S(10) 01EA 00.0A Exercise 297: SS4 DC S(*) 01EC 91.EC 01EE (align) Exercise 298: SS5 DC A(125),F'33',C'*',2H'6,18' 01F D C 00 (align) Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' F1.6B.F1

219 219 Alberto Romano Schiesari – Prev.Page (A) Exercise 300 (Representing fields in bytes) * Endereço Conteúdo Exercise 300: LAST DC 256AL1(255+LAST-*) 0209 FF.FE.FD.FC.FB.FA.F9.F8.F7.F6.F5.F4.F3.F2.F1.F0 * 0219 EF.EE.ED.EC.EB.EA.E9.E8.E7.E6.E5.E4.E3.E2.E1.E0 * 0229 DF.DE.DD.DC.DB.DA.D9.D8.D7.D6.D5.D4.D3.D2.D1.D0 * 0239 CF.CE.CD.CC.CB.CA.C9.C8.C7.C6.C5.C4.C3.C2.C1.C0 * 0249 BF.BE.BD.BC.BB.BA.B9.B8.B7.B6.B5.B4.B3.B2.B1.B0 * 0259 AF.AE.AD.AC.AB.AA.A9.A8.A7.A6.A5.A4.A3.A2.A1.A0 * F.9E.9D.9C.9B.9A * F.8E.8D.8C.8B.8A * F.7E.7D.7C.7B.7A * F.6E.6D.6C.6B.6A * 02A9 5F.5E.5D.5C.5B.5A * 02B9 4F.4E.4D.4C.4B.4A * 02C9 3F.3E.3D.3C.3B.3A * 02D9 2F.2E.2D.2C.2B.2A * 02E9 1F.1E.1D.1C.1B.1A * 02F9 0F.0E.0D.0C.0B.0A

220 220 Alberto Romano Schiesari – Prev.Page (A) Exercise 301 (Decoding instructions) Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ////////----//////// //////// //////////// Suppose the general registers with the following values: R00= R04= R08= R12=00000C00 R01= R05= R09= R13=00000D00 R02= R06= R10=00000A00 R14=00000E00 R03= R07= R11=00000B00 R15=00000F00

221 221 Alberto Romano Schiesari – Prev.Page (A) Exercise 301 (Decoding instructions) Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ////////----//////// //////// //////////// 1ABB - Operation code (machine code) = 1A - Mnemonic Assembler code = AR (add register) - Instruction address = X’ ’ - Operands = 1st operand = register 11; 2nd operand = register CF0 - Operation code (machine code) = 41 - Mnemonic Assembler code = LA (load address) - Instruction address = X’ ’ -Operands = 1st operand = register 2; 2nd operand : index register = register 7 2nd operand : base register = register 8 2nd operand : displacement = X’CF0’ 2nd operand address = X’ ’+X’ ’+X’CF0’= X’00001BF0’ Continues...

222 222 Alberto Romano Schiesari – Prev.Page (A) Exercise 301 (Decoding instructions) Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ////////----//////// //////// //////////// 0A13 - Operation code (machine code) = 0A - Mnemonic Assembler code = SVC (supervisor call) - Instruction address = X’ ’ - Operands = supervisor call code = X’13’ = (19) 10 = open 980F Operation code (machine code) = 98 - Mnemonic Assembler code = LM (load multiple) - Instruction address = X’ ’ -Operands = 1st operand = register 0; 3rd operand : register = register 15 (X’F’) 2nd operand : base register = register 3 2nd operand : displacement = X’344’ 2nd operand address = X’ ’+X’344’= X’ ’ Continues...

223 223 Alberto Romano Schiesari – Prev.Page (A) Exercise 301 (Decoding instructions) Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ////////----//////// //////// //////////// 45E00CB4 - Operation code (machine code) = 45 - Mnemonic Assembler code = BAL (branch and link) - Instruction address = X’ C’ -Operands = 1st operand = register 14 (X’E’); 2nd operand : index register = register 0 2nd operand : base register = register 0; 2nd operand : displacement = X’CB4’ 2nd operand address = X’CB4’= X’00000CB4’ 90EC0D00 - Operation code (machine code) = 90 - Mnemonic Assembler code = STM (store multiple) - Instruction address = X’ ’ -Operands = 1st operand = register 14 (X’E’); 3rd operand : register = register 12 (X’C’) 2nd operand : base register = register 0; 2nd operand : displacement = X’D00’ 2nd operand address = X’D00’= X’00000D00’ Continues...

224 224 Alberto Romano Schiesari – Prev.Page (A) Exercise 301 (Decoding instructions) Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ////////----//////// //////// //////////// FA CC - Operation code (machine code) = FA - Mnemonic Assembler code = AP (add packed) - Instruction address = X’ ’ - 1st operand length = 9 bytes; 1st operand base register = register 3; 1st operand displacement= X’054’; 1st operand address= X’ ’+X’054’ = X’ ’ - 2nd operand length = 3 bytes; 2nd operand base register = register 4; 2nd operand displacement = X’8CC’; 2nd operand address= X’ ’+X’8CC’ = X’00000CCC’ D Operation code (machine code) = D2 - Mnemonic Assembler code = MVC (move character) - Instruction address = X’ A’ - 1st operand length = 131 bytes; 1st operand base register = register 3; 1st operand displacement= X’344’; 1st operand address= X’ ’+X’344’ = X’ ’ - 2nd operand length = 131 bytes; 2nd operand base register = register 5; 2nd operand displacement = X566’; 2nd operand address= X’ ’+X’566’ = X’00000A66’

225 225 Alberto Romano Schiesari – Prev.Page Programming Hints

226 226 Alberto Romano Schiesari – Prev.Page Programming Hints Interesting things, useful things, awful but used things, etc...

227 227 Alberto Romano Schiesari – Prev.Page Programming Hints 1 base register load PROG START 0 USING *,3 LR 3,15 LOAD FIRST AND ONLY BASE REGISTER * REG 3 CONTAINS THE ENTRY POINT ADDRESS * THIS TYPE OF LOAD (WITH LR) IS OFTEN USED IN MVS PROG START 0 USING *,3 BALR 3,0 LOAD INTO R3 THE ADDRESS JUST AFTER BALR BCTR 3,0 SUBTRACTS 1 BCTR 3,0 SUBTRACTS 1 ONCE MORE * HERE REGISTER 3 IS OK; * IT HAS THE ENTRY POINT ADDRESS

228 228 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4096(4) LOAD INTO R4 THE VALUE OF R NO! Why not? Because maximum displacement is 4095 (X ’ FFF ’ ) !!! Assembly error ! May I do this way?

229 229 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG 4 LA 4,4095(4) ADD 4095 * RESULT = 4096 AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X ’ ’ * OK ! R3 AND R4 PROPERLY LOADED ! You may do this way...

230 230 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4095 LOAD NUMBER 4095 INTO REG 4 LA 4,1(4) ADD 1 * RESULT = 4096 AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X ’ ’ * OK ! R3 AND R4 PROPERLY LOADED ! Or that way...

231 231 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG 4 LA 4,4095(3,4) ADD ENTRY POINT * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X ’ ’ * OK ! R3 AND R4 PROPERLY LOADED ! Even this way...

232 232 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,2048 LOAD NUMBER 1 INTO REG 4 LA 4,2048(3,4) ADD ENTRY POINT * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X ’ ’ * OK ! R3 AND R4 PROPERLY LOADED ! You may do like this...

233 233 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1000 CARREGA NRO 1000 NO REG 4 LA 4,3096(3,4) SOMA ENTRY POINT * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X ’ ’ * OK ! R3 AND R4 PROPERLY LOADED ! Or like this...

234 234 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,PROG+4096 LOAD “ DIRECTLY ” ENTRY POINT Is it correct? NO! Why not? Because the address PROG isn ’ t in the range of first base register (R3), so far the only one correctly loaded. Assembly error.

235 235 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS L 4,=A(PROG+4096) CARREGA “ DIRETO ” ENTRY POINT And about this way? IT DEPENDS ON... ! The contents of the literal is being loaded into R4. If the literal is outside the range of the FIRST BASE REGISTER (R3) (THE ONLY ONE CORRECTLY LOADED SO FAR), THEN this is INVALID to prepare the second base register. Assembly error. (case 1) ELSE, this way (using the literal) is VALID. (case 2)

236 236 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load CASE 1 : Literal is outside range of the 1st base register (R3), and it is the only one prepared so far. You can ’ t do this way ! Assembly error. PROG START 0 USING *,3,4 LR 3,15 L 4,=A(PROG+4096)... ( L needs the 2nd base register prepared, but... L prepares the 2nd base register! Execution time error!) END ( literals are declared after END)... =A(PROG+4096) Program = 8k This part is served by 1st base register This part is served by 2nd base register

237 237 Alberto Romano Schiesari – Prev.Page Programming Hints 2 base registers load CASE 2 : Literal is in the range of the first base register (R3), and it is the only one prepared so far, so you can do this way. PROG START 0 USING *,3,4 LR 3,15 L 4,=A(PROG+4096) B SKIP LTORG =A(PROG+4096) SKIP... END (other literals declared here)... =... =... Program = 8k This part is served by 1st base register Forces the literal to be defined here. This part is served by 2nd base register

238 238 Alberto Romano Schiesari – Prev.Page Complete Developed Programs Complete developed programs

239 239 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE01

240 240 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE01 START 0 NO BASE REGISTER REQUIRED ! LA 15,0 LOAD RETURN CODE INTO REG 15 BR 14 BYE BYE... END

241 241 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE02

242 242 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE02 START 0 * DUE TO THE LITERAL, A BASE REGISTER IS NEEDED * THE ADDRESS OF THE LITERAL MUST BE CONVERTED TO BASE+DISPLACEMENT * IN THE L INSTRUCTION. * INICIALIZATION USING *,15 INDICATES BASE REGISTER AND ITS * PRESUMED VALUE AT EXECUTION TIME * NOTE THAT BASE REGISTER 15 IS ALREADY * LOADED WITH ENTRY POINT BY THE * OPERATING SYSTEM * FINALIZATION L 15,=F'0' RETURN CODE INTO REG 15 * WOW! * IN THE SAME INSTRUCTION ( L ) REG 15 IS USED TO ADDRESS THE LITERAL * AND IT HAD BEEN LOADED WITH ZERO. * SO, THE VALUE USED AS BASE VALUE IN THE BASE REGISTER IS DESTROYED. * IF ONLY 1 MORE INSTRUCTION NEED A BASE REGISTER READY, NO ONE * IS OK BR 14 BYE BYE... END

243 243 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE03

244 244 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE03 START 0 * INICIALIZATION USING *,3 REG 3 IS THE BASE REGISTER * AND ITS PRESUMED VALUE AT EXECUTION TIME IS THE ENTRY POINT LR 3,15 LOAD ENTRY POINT INTO BASE REGISTER * BASE REGISTER OK. * FINALIZATION L 15,=F'0' RETURN CODE INTO REG 15 BR 14 BYE BYE... END

245 245 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE04

246 246 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE04 START 0 * INICIALIZATION USING *,3,4,5,6,7 BASE REGISTERS ARE 3,4,5,6 AND 7 * PRESUMED CONTENTS AT RUN TIME: * REG 3 = ENTRY POINT * REG 4 = ENTRY POINT + X'1000' * REG 5 = ENTRY POINT + X'2000' * REG 6 = ENTRY POINT + X'3000' * REG 7 = ENTRY POINT + X'4000' STM 14,12,12(R13) SAVE REGISTERS INTO CALLER' SAVEAREA * LOAD BASE REGISTERS LR 3,15 LOAD ENTRY POINT INTO R3 LA 4,1 LOAD #1 INTO R4 LA 4,4095(3,4) R4 = R3 + X'1000' * LINKAGE CONVENTIONS LA 15,SAVEZZZZ LOAD MY SAVEAREA ADDRESS INTO 15 ST 15,8(13) SAVE MY SAVEAREA ADDRESS INTO * CALLER'S SAVEAREA LR 13,15 LOAD R13 WITH MY SAVEAREA ADRS * EXECUTE PROGRAM

247 247 Alberto Romano Schiesari – Prev.Page Complete Developed Programs OPEN (RELAT,OUTPUT) OPEN PRINT FILE MVC LINGERAL,=CL133' HELLO WORLD' MOVE MESSAGE PUT RELAT,LINGERAL PRINT LINE CLOSE (RELAT) CLOSE PRINT FILE * FINALIZATION L 2,=F'0' RETURN CODE INTO R2 L 13,SAVEZZZZ+4 RESTORE CALLER SAVEAREA ADDRESS ST 2,16(13) RET CODE INTO R15 RESTORE AREA LM 14,12,12(13) RESTORE REGISTERS BR 14 BYE BYE... * * AREAS AND DATASETS * RELAT DCB LRECL=133,DSORG=PS,RECFM=FA,DDNAME=SYSPRINT,MACRF=PM LINGERAL DC CL133' ' PRINT LINE * END, LAST SOURCE STATEMENT

248 248 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE05

249 249 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTST05 START 0 * REGISTER EQUATES SO THAT THEY APPEAR AT THE CROSS REFERENCE R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15

250 250 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * INICIALIZING USING *,R3,R4,R5,R6,R7 INDICATE BASE REGISTERS AND ITS * PRESUMED CONTENTS AT EXECUTION STM R14,R12,12(R13) SAVE REGISTERS IN CALLER' * SAVEAREA * LOAD BASE REGISTERS LR R3,R15 LOAD R3 WITH ENTRY POINT LA R4,1 LOAD R4 WITH 1 LA R4,4095(R3,R4) R4 = R LA R5,1 LOAD R5 WITH 1 LA R5,4095(R4,R5) R5 = R LA R6,1 LOAD R6 WITH 1 LA R6,4095(R5,6) R6 = R LA R7,1 LOAD R6 WITH 1 LA R7,4095(R6,R7) R7 = R * ADJUST POINTERS TO SAVEAREAS ST R13,SAVEZZZZ+4 SAVE CALLER SAVEAREA'S ADDRESS * IN MY SAVEAREA LA R15,SAVEZZZZ LOAD R15 WITH MY SAVEAREA ADDRS ST R15,8(R13) SAVE MY SAVEAREA'S ADDRESS * IN CALLER'S SAVEAREA LR R13,R15 LOAD R13 WITH MY SAVEAREA ADDRS

251 251 Alberto Romano Schiesari – Prev.Page Complete Developed Programs EX R15,*+4+4 SAVE PARM IN MY AREA * BY EXECUTING THE MVC BELLOW B GO EXECUTE THE PROGRAM MVC PARMTEXT(0),2(R1) MOVE PARM TO MY AREA * DEFINE INITIALIZATION AREA SAVEZZZZ DC 18F'0' MY SAVEAREA PARMTEXT DC CL100' ' MY PARM AREA DC F'0' PARM LENGTH * EXECUTES THE PROGRAM BAL R14,ROTMAIN WHOLE PROGRAM (EXCEPT INIT) * FINALIZATION L R2,=F'22' LOAD R2 WITH RETURN CODE L R13,SAVEZZZZ+4 RESTORE CALLER'S SAVEAREA ST R2,16(R13) STORE RETURN CODE WHERE R15 * WILL BE LOADED FROM LM R14,R12,12(R13) RESTORE REGISTERS BR R14 BYE BYE... * * ROUTINES *

252 252 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * * ROTMAIN * DC A(0) RETURN ADDRESS ROTMAIN ST R14,*-4 SAVE RETURN ADDRESS * GET INTO AND DO WHAT I HAVE TO DO OPEN (RELAT,OUTPUT) OPEN FILE MVC LINGERAL,=CL133' HELLO WORLD' MOVE MESSAGE BAL R14,IMPLIN PRINT LINE WITH ABOVE MESSAGE MVC LINGERAL+1(25),=C'TAMANHO PARM INFORMADO = ' MOVE MSG L LOAD R14 WITH PARM LENGTH CVD R14,WDOUBLE CONVERT IT TO PACKED DECIMAL UNPK LINGERAL+26(3),WDOUBLE CONVERT IT TO ZONED DECIMAL OI LINGERAL+28,X'F0' FORCE ZONE F BAL R14,IMPLIN PRINT LINE WITH PARM LENGTH MVC LINGERAL+1(18),=C'PARM INFORMADO = ' MESSAGE MVC LINGERAL+19(100),PARMTEXT PARM TEXT BAL R14,IMPLIN PRINT LINE WITH PARM TEXT CLOSE (RELAT) CLOSE FILE * EXIT ROUTINE L R14,ROTMAIN-4 RESTORE RETURN ADDRESS BR R14 RETURN

253 253 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * * PRINT A LINE * DC A(0) RETURN ADDRESS IMPLIN ST R14,*-4 SAVE RETURN ADDRESS PUT RELAT,LINGERAL PRINT LINE MVC LINGERAL,=CL133' ' CLEAR LINE AP LINS,=P'1' UPDATE LINE COUNTER L R14,IMPLIN-4 RESTORE RETURN ADDRESS BR R14 RETURN * * DECLARE FILES AND AREAS * * FILES RELAT DCB LRECL=133,DSORG=PS,RECFM=FA,DDNAME=SYSPRINT,MACRF=PM * AREAS WDOUBLE DC D'0' DOUBLE FOR WORK LINGERAL DC CL133' ' PRINT LINE LINS DC PL4'0' LINE COUNTER * END, LAST SOURCE STMT

254 254 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE06 The input file has the following contents: From To Position Position Length Description Branch code Branch name Branch address Branch balance (no info) The output lines must be as following : From To Position Position Length Description Branch code Spaces Branch name Spaces Branch address Spaces Branch balance Spaces This program reads an input file, and for each record read, it prints a detail line

255 255 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE06 START 0 * REGISTER EQUATES SO THAT THEY APPEAR AT THE CROSS REFERENCE R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15

256 256 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * INICIALIZING USING *,R3,R4,R5,R6,R7 INDICATE BASE REGISTERS AND ITS * PRESUMED CONTENTS AT EXECUTION STM R14,R12,12(R13) SAVE REGISTERS IN CALLER' * SAVEAREA * LOAD BASE REGISTERS LR R3,R15 LOAD R3 WITH ENTRY POINT LA R4,1 LOAD R4 WITH 1 LA R4,4095(R3,R4) R4 = R LA R5,1 LOAD R5 WITH 1 LA R5,4095(R4,R5) R5 = R LA R6,1 LOAD R6 WITH 1 LA R6,4095(R5,6) R6 = R LA R7,1 LOAD R6 WITH 1 LA R7,4095(R6,R7) R7 = R * ADJUST POINTERS TO SAVEAREAS ST R13,SAVEZZZZ+4 SAVE CALLER SAVEAREA'S ADDRESS * IN MY SAVEAREA LA R15,SAVEZZZZ LOAD R15 WITH MY SAVEAREA ADDRS ST R15,8(R13) SAVE MY SAVEAREA'S ADDRESS * IN CALLER'S SAVEAREA LR R13,R15 LOAD R13 WITH MY SAVEAREA ADDRS

257 257 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * TAKE PARM AND LET IT IN PARMTEXT L R1,0(R1) LOAD R1 WITH PARM ADDRESS MVC SAVE PARM LENGTH L LOAD R15 WITH PARM LENGTH LTR R15,R15 IS THERE PARM? BZ IF LENGTH ZERO, NO PARM CAME BCTR R15,R0 SUBTRACT 1 FROM R15 EX R15,*+4+4 SAVE PARM IN MY AREA B GO EXECUTE THE PROGRAM MVC PARMTEXT(0),2(R1) MOVE PARM TO MY AREA * DEFINE INITIALIZATION AREAS SAVEZZZZ DC 18F'0' MY SAVEAREA PARMTEXT DC CL100' ' MY PARM AREA DC F'0' PARM LENGTH * EXECUTES THE PROGRAM BAL R14,ROTMAIN WHOLE PROGRAM (EXCEPT INIT) * FINALIZATION L R2,=F'0' LOAD R2 WITH RETURN CODE L R13,SAVEZZZZ+4 RESTORE CALLER'S SAVEAREA ST R2,16(R13) STORE RETURN CODE LM R14,R12,12(R13) RESTORE REGISTERS BR R14 BYE BYE...

258 258 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * * ROUTINES * * * ROTMAIN * DC A(0) RETURN ADDRESS ROTMAIN ST R14,*-4 SAVE RETURN ADDRESS * GET INTO AND DO WHAT I HAVE TO DO OPEN (BRANCHES,INPUT) OPEN FILE OPEN (REPOR,OUTPUT) OPEN FILE RDAGAIN BAL 14,READREC READ AN INPUT FILE RECORD BAL R14,PROCREC PROCESS THE RECORD B RDAGAIN BACK TO READ ENDRECS CLOSE (REPOR) CLOSE OUTPUT FILE CLOSE (BRANCHES) CLOSE INPUT FILE * EXIT ROUTINE L R14,ROTMAIN-4 RESTORE RETURN ADDRESS BR R14 RETURN

259 259 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * * PRINT A LINE * DC A(0) RETURN ADDRESS PRILINE ST R14,*-4 SAVE RETURN ADDRESS PUT REPOR,DETLINE PRINT LINE MVC DETLINE,=CL133' ' CLEAR LINE L R14,PRILINE-4 RESTORE RETURN ADDRESS BR R14 RETURN * * READ A RECORD * DC A(0) RETURN ADDRESS READREC ST R14,*-4 SAVE RETURN ADDRESS GET BRANCHES,LRECAREA READ A LOGICAL RECORD L R14,READREC-4 RESTORE RETURN ADDRESS BR R14 RETURN

260 260 Alberto Romano Schiesari – Prev.Page Complete Developed Programs * * PROCESS A RECORD * DC A(0) RETURN ADDRESS PROCREC ST R14,*-4 SAVE RETURN ADDRESS MVC DETLINE+1(4),LRECAREA MOVE BRANCH CODE MVC DETLINE+7(30),LRECAREA+4 MOVE BRANCH NAME MVC DETLINE+38(20),LRECAREA+34 MOVE BRANCH ADDRESS MVC DETLINE+60(13),LRECAREA+54 MOVE BRANCH BALANCE BAL R14,PRILINE PRINT DETAIL LINE L R14,PROCREC-4 RESTORE RETURN ADDRESS BR R14 RETURN * * DECLARE FILES AND AREAS * * FILES REPOR DCB LRECL=133,DSORG=PS,RECFM=FA,DDNAME=SYSPRINT,MACRF=PM BRANCHES DCB LRECL=80,DSORG=PS,DDNAME=BRANCHES,MACRF=GM,EODAD=ENDRECS * AREAS WDOUBLE DC D'0' DOUBLE FOR WORK LRECAREA DC CL80' ' LOGICAL RECORD INPUT AREA DETLINE DC CL133' ' DETAIL LINE * END, LAST SOURCE STMT

261 261 Alberto Romano Schiesari – Prev.Page Complete Developed Programs If the input file is an in-stream data file with this records (the ruler in blue is just to facilitate the visualization): BRANCH 0001 NAME *BRANCH 0001 ADDRESS* BRANCH 0002 NAME *BRANCH 0002 ADDRESS* BRANCH 0003 NAME *BRANCH 0003 ADDRESS* BRANCH 0004 NAME *BRANCH 0004 ADDRESS* BRANCH 0005 NAME *BRANCH 0005 ADDRESS* The output produced is the following (the ruler in blue is just to facilitate the visualization): BRANCH 0001 NAME * BRANCH 0001 ADDRESS* BRANCH 0002 NAME * BRANCH 0002 ADDRESS* BRANCH 0003 NAME * BRANCH 0003 ADDRESS* BRANCH 0004 NAME * BRANCH 0004 ADDRESS* BRANCH 0005 NAME * BRANCH 0005 ADDRESS*

262 262 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE07

263 263 Alberto Romano Schiesari – Prev.Page Complete Developed Programs

264 264 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE08

265 265 Alberto Romano Schiesari – Prev.Page Complete Developed Programs

266 266 Alberto Romano Schiesari – Prev.Page Complete Developed Programs PGMTSE09

267 267 Alberto Romano Schiesari – Prev.Page Complete Developed Programs

268 268 Alberto Romano Schiesari – Prev.Page THE END


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