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Dr A Sahu Dept of Comp Sc & Engg. IIT Guwahati. Hierarchy of I/O Control Devices 8155 I/O + Timer 8155 I/O + Timer 8255 I/O 8255 I/O 8253/54 Timer 8253/54.

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Presentation on theme: "Dr A Sahu Dept of Comp Sc & Engg. IIT Guwahati. Hierarchy of I/O Control Devices 8155 I/O + Timer 8155 I/O + Timer 8255 I/O 8255 I/O 8253/54 Timer 8253/54."— Presentation transcript:

1 Dr A Sahu Dept of Comp Sc & Engg. IIT Guwahati

2 Hierarchy of I/O Control Devices 8155 I/O + Timer 8155 I/O + Timer 8255 I/O 8255 I/O 8253/54 Timer 8253/54 Timer 2 Port (A,B), No Bidirectional HS mode (C) 4 mode timer 2 Port (A,B) A is Bidirectional HS mode (C) Extra controls 6 mode timer 8259 Interrupt controller 8259 Interrupt controller 8237 DMA controller 8237 DMA controller 8251 Serial I/O USART controller 8251 Serial I/O USART controller

3 Asynchronous Communication 8251 USART Architecture USART Registers Programming UART RS 232 Port Interfacing CRT Monitor using a UART and RS- 232 port

4 Serial – Cheaper – Slower Parallel – Faster – Data skew – Limited to small distances Data Transmission Parallel Serial Synchronous ASynchronous

5 Sender Receiver Data a a Transmission Gaps Asynchronous transmission Synchronous transmission CLK

6 Character oriented Each character carried start bit and stop bits When No data are being transmitted – Receiver stay at logic 1 called mark, logic 0 is Space Framing: – Transmission begins with one start bit (low/0) – Followed by DATA (8bit) and – Stop bits (1 or 2 bits of logic high)

7 Asynchronous transmission 8 bit Data Start BitStart Bits 1 0 0 0 1 1 1 0 LSB MSB Time 1 start bit 1 or 2 Stop bit Source data

8 Serial Input Data (SID) Serial Output Data (SOD) – Instruction SIM is necessary to output data – Interpretations (ACC contents) D7D6D5D4D3D2D1D0 SODSDE (0/1 Dis/Ena SOD) XFor interrupts MVI A, 80 ; Set D 7 in the ACC=1 RAR ;Set D 6 =1 and bring carry into D 7 SIM; output D 7 MVI A, 80 ; Set D 7 in the ACC=1 RAR ;Set D 6 =1 and bring carry into D 7 SIM; output D 7

9 Transmit an ASCII Char stored in Register B MVI B ASCIIDatabyte; get data byte in B MVI C,0BH; set up counter for 11 bits XRAA; reset carry to 0 NXTbit:MVIA,80H;set D7=1 in ACC RAR;bring Carry in D7 and set D6=1 SIM;output D7 CALL DELAYBittime;wait for fixed time (BWT) STC;set Carry 1 MOV A,B;Place ASIII car in acc RAR; place ASCII D0 in Carry ;and shift 1 in D7 MOV B,A;Save B DCR C JNZNXTbit RET MVI B ASCIIDatabyte; get data byte in B MVI C,0BH; set up counter for 11 bits XRAA; reset carry to 0 NXTbit:MVIA,80H;set D7=1 in ACC RAR;bring Carry in D7 and set D6=1 SIM;output D7 CALL DELAYBittime;wait for fixed time (BWT) STC;set Carry 1 MOV A,B;Place ASIII car in acc RAR; place ASCII D0 in Carry ;and shift 1 in D7 MOV B,A;Save B DCR C JNZNXTbit RET

10 Programmable chip 8251 Requirement of HW control serial I/O – An input/output port are required for interfacing – Converts data bits in to Parallel to serial & vice versa – Data transfer to be synchronized between I/O – USART (Universal Synchronous Asynchronous Receiver and Transmitter )

11 Writing a program compatible with all different serial communication protocols is difficult and it is an inefficient use of microprocessor. UART: Universal Asynchronous Receiver/Transmitter chip. USART: Universal Synchronous/Asynchronous Receiver/Transmitter chip. The microprocessor sends/receives the data to the UART in parallel, while with I/O, the UART transmits/receive data serially. 8251 functions are integrated into standard PC interface chip.

12 CPU 8251 status (8 bit) status (8 bit) data (8 bit) data (8 bit) serial port xmit/ rcv xmit/ rcv UART/USART 8251 USART 8250/16450 UART is a newer version of 8251. 16550 is the latest version UART.

13 Data Bus Buffer Data Bus Buffer Transmit Buffer Transmit Buffer Receive Buffer Receive Buffer Transmit Control Transmit Control Receive Control Receive Control R/W Control Logic R/W Control Logic Modem Control InternalLineInternalLine InternalLineInternalLine D7-D0 RESET CLK C/D b RD b WR b CS b DSR b DTR b CTS b RTS b TXD TXRDY TXE TXC RXD RXRDY RXC SYBDET/BD

14 CS b C/D b RD b WR b Meaning 1XXXData Bus Tri-state 0X11 0101Status  CPU 0110Control Word  CPU 0001Data  CPU (accept data from Data Buffer) 0010Data  CPU (Out put data to Data buffer)

15 R/W Control Logic R/W Control Logic RESET CLK C/D b RD b WR b CS b Data Buffer register D7-D0 C/D b =0 RD b or WR b Control Register 16 bit Control Register 16 bit Status Register 8 bit Status Register 8 bit C/D b =1 WR b =0 C/D b =1 RD b =0 Internal DataBusInternal DataBus Internal DataBusInternal DataBus Transmitter Receiver

16 Data Buffer Register Data Buffer Register D0 D7 InternalData BusInternalData Bus InternalData BusInternalData Bus Transmitter Buffer Register Transmitter Buffer Register Receiver Buffer Register Receiver Buffer Register Out put Register Out put Register Input Register Input Register Transmitter Control Logic Transmitter Control Logic Receiver Control Logic Receiver Control Logic TxD TxC b TxRDY TxE RxD RxC b RxRDY

17 D7 D6 D5 D4 D3 D2 D1 D0 Framing Control # of Stop bits Framing Control # of Stop bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Parity Control X0=No Parity 01: Even 11: Odd Parity Control X0=No Parity 01: Even 11: Odd Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock

18 EH IR RTS ER SBRK RxE DTR TxE TxE:transmit enable (0/1 Enable Disable) DTR:data terminal ready (1=ENABLE DTR) RxE:receiver enable (1/0=EN/DISABLE) SBPRK: send break character 1= force TxD low ER:error reset (Reset Flags: Parity,Over run, Framing Error of Status Word) RTS:request to send (1= Enable Request to send) IR:internal reset (Reset 8251 to mode) EH:enter hunt mode (1=search for Sync Character)

19 DSR SYN DET SYN DET FE OE PE Tx EMPTY Tx EMPTY RxRDY TxRDY TxRDYtransmit ready (DB Buffer is empty) RxRDYreceiver ready TxEMPTYtransmitter empty PEparity error (1=when PE detected) OEoverrun error FEframing error (Aynsc only, Valid stop bit not detected) SYNDETsync. character detected DSRdata set ready (DSR set at 0 level)

20 RS232: Data transmitted as Voltage to terminal – 20KBps, 50Mters only – Improved to RS 422A (9 pine), RS 423A (15 pin-VGA) Modem (Data transmitted by Frequency) Data Terminal Equipment (DTE) CPU Data Terminal Equipment (DTE) CPU Data Communication Equipment (DCE) I/O Data Communication Equipment (DCE) I/O 237237 237237 237237 237237 RS-232 Cable Transmit Receive +9V -9V +9V -9V +3V -0.2V 3V 0.2V

21 PinSignalFunction 2TxD: transmitted DataOutput CPU to I/O 3RxD :Received DataInput I/O receive from CPU 4RTS :Request to SendOutput from I/0 5CTS :Clear to sendInput to I/O, HS signal 6DSR: Data set readyCPU send to I/O is ready 7GNDComm. Ref GND 8DCD: Data Carrier DetectI/O to disable reception 20DTR: Data terminal readyOutput to indicate I/O is ready DB-25 DB9

22 Connect a RS 232 port onto a CRT terminal Address the 8251A USART at FF to control transmission Specify initialization instructions and status word to transmit characters – Async mode with 9600 buad – Character length= 7 bit + 2 stop bit – No parity check Write instruction to initialize USART and read status word and Setup a loop until the transmitter is ready

23 237237 237237 237237 237237 Transmit Receive 8251A TxD RxD RxC b TxC b CLK CTS b GND 8085 MPU 8085 MPU D7 D0 CS b C/D b A7 A1 A0 Voltage Converter IOR b IOW b Reset Out CLK Out RD b WR b RESET CLK D7 D0 Control & Status Register Address=FFH C/D b line should be high, == > A 0 =1 Control & Status Register Address=FFH C/D b line should be high, == > A 0 =1

24 D7D6D5D4D3D2D1D0 11001010 Two Stop bitsNo parity7 bit charactersBaud=TxC/16 =153.6k/16 =9600 D7D6D5D4D3D2D1D0 X0X1X0X1 ERR Reset Receive Disable Transmit Enable Mode Word COMMAND WORD STATUS CAH 11H D7D6D5D4D3D2D1D0 XXXXXXX1 Transmit Ready 01H

25 SETUP: MVIA,CAH ; load mode word OUTFFH;Write mode word in control register MVI A,11H; load command word to enable TX OUTFFH;Enable the transmitter STATUS:IN FFH; Read the status register ANI 01H; Mask all bit except D0 JZ STATUS ; if D0=0 the TX buffer if full SETUP: MVIA,CAH ; load mode word OUTFFH;Write mode word in control register MVI A,11H; load command word to enable TX OUTFFH;Enable the transmitter STATUS:IN FFH; Read the status register ANI 01H; Mask all bit except D0 JZ STATUS ; if D0=0 the TX buffer if full

26 Message is “HELLO CS421” 2070 0E ; 13 characters to follow 2071 48; Letter H 2072 45; Letter E 2073 4C; Letter L 2074 4C ; Letter L 2075 4F ; Letter H 2076 20; space 2077 43; Letter C 2078 53; Letter S 2079 34; Digit 4 2080 32;Digit 2 2081 31; Digit 1 2082 0D; Carriage return 2083 0A; Linefeed Message is “HELLO CS421” 2070 0E ; 13 characters to follow 2071 48; Letter H 2072 45; Letter E 2073 4C; Letter L 2074 4C ; Letter L 2075 4F ; Letter H 2076 20; space 2077 43; Letter C 2078 53; Letter S 2079 34; Digit 4 2080 32;Digit 2 2081 31; Digit 1 2082 0D; Carriage return 2083 0A; Linefeed

27 LXI H 2070H ; Meory ptr for Message MOV C, M ; Set up Ctr register MVI A,40; Reset 8251 OUTFFH MVIA,CA; Initialize 82512 OUT FFH MVI A,11 ; initialize for transmit OUT FFH LXI H 2070H ; Meory ptr for Message MOV C, M ; Set up Ctr register MVI A,40; Reset 8251 OUTFFH MVIA,CA; Initialize 82512 OUT FFH MVI A,11 ; initialize for transmit OUT FFH STATUS: IN FFH ANI 01H;Ckeck TxRDY JZ STATUS ; is txRDY 1 ? If not wait INX H ; Pont to Next Char MOV A,M ; place the Char in ACC OUT FEH ; Send the Char to Transmitter DCR C ; DCr cnt JNZ STATUS ;Again Send the rest of Char HLT STATUS: IN FFH ANI 01H;Ckeck TxRDY JZ STATUS ; is txRDY 1 ? If not wait INX H ; Pont to Next Char MOV A,M ; place the Char in ACC OUT FEH ; Send the Char to Transmitter DCR C ; DCr cnt JNZ STATUS ;Again Send the rest of Char HLT

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