# I/O Placement for FPGAs with Multiple I/O Standards.

## Presentation on theme: "I/O Placement for FPGAs with Multiple I/O Standards."— Presentation transcript:

I/O Placement for FPGAs with Multiple I/O Standards

Outline 1.Introduction 2.The Constrained I/O Placement Problem 3.Previous Work 4.Proposed Solution 5.Placement of Core Logic and I/O 6.Experimental Results 7.Conclusion

Background FPGA GTL CTT LVTTL Proliferation of different I/O standards: Multi-I/O standard interface is required. GTL, LVTTL, CTT, AGP-2X,...

Banked I/O A flexible economical organization to interface w/ different standards bank1bank2 bank3 bank5bank6 bank7 bank8 bank4 One reference voltage, V REF, per bank. One supply voltage, V CCO, per bank. FPGA

Constrained I/O Placement V REF /V CCO requirements by different I/O objects E.g. Input objectOutput object LVTTLV REF = N/A V CCO = 3.3 V REF = N/A V CCO = 3.3 CCTV REF = 1.50 V CCO = N/A V REF = N/A V CCO = 3.3 SSTL2 IV REF = 1.25 V CCO = N/A V REF = N/A V CCO = 2.5 Two objects are allowed in same bank only if they have no V REF and V CCO conflicts.

Previous Work J. Anderson, et al. “A placement algorithm for FPGA designs with multiple I/O standards”, FPLA’00. –A heuristic –Use simulated annealing to minimize (wirelength + timing cost + banking violation cost) –Proposed two procedures to fix banking violations if possible Shortcomings –Can fail to find a valid I/O placement –Unable to tell if an instance is feasible or not

This Work An exact algorithm proposed. Always find a valid placement if there is one. Give a “proof” when an instance is infeasible. Based on Integer Linear Programming. Feasible run time. Run time independent of device size.

I/O Classification 4 Types of I/O objects i.Type A: require a V CCO but not a V REF. ii.Type B: require a V REF but not a V CCO. iii.Type C: require both a V CCO and a V REF. iv.Type D: require neither V CCO nor V REF. Subtypes A i : require V CCO = V Ci (i = 1, 2, …) B j : require V REF = V Rj (j = 1, 2, …) C ij : require V CCO = V Ci and V REF = V Rj (i = 1, 2, …; j = 1, 2, …)

“Bin” Packing Multiple Bin Types: T1T1 T 11 T 12 T2T2 T 21 T 22 T 13 T 23 … … … T i : V CCO = V Ci ; V REF not set. T ij : V CCO = V Ci ; V REF = V Rj Problem: Want to pack all I/O objects using a minimum # bins.

Restrictions: T2T2 T 21 T 22 T 23 … … … AiAi BjBj C ij D T1T1 T 11 T 12 T 13 A i  {T i,T i1,T i2,…} B j  {T 1j,T 2j,T 3j,…} C ij  {T ij } D  any type of bin A1A1 B3B3 item type  bin type

Solution Theorem: I/O placement is feasible  minimum # bins needed  8. We derived an integer linear program formulation. Use only a handful of integer variables (always less than 32 for Xilinx Virtex-E FPGA). The ILP can be solved in seconds. Highly scalable since run time is independent of no. of I/O objects.

Timing Optimization Solution of ILP tells us how many banks of each type T i /T ij are needed. Freedom in choosing which banks are configured to T i /T ij. Freedom in permuting I/O objects within a bank. Freedom in permuting I/O objects of same subtype. Timing/wirelength can be optimized by exploiting the above freedom.

Core Logic and I/O Placement S.A. to place core logic, I/O simultaneously Fix I/O banking violations ILP to compute feasible I/O placement S.A. to place core and change I/O placement to improve timing successful? User re-place I/O manually N Y end Old Flow:Our Flow:

Experimental Results 3 batches of test cases at various difficulty levels. Assume a device of 8 banks with 100 user I/O pins per bank. #V CCO /#V REF Avg. time (s) Max. time (s) #feasible: #infeasible Batch 12/20.01 98:2 Batch 23/40.222.4676:24 Batch 34/7130.791929.669:91

Conclusion Presented an ILP formulation to solve the constrained I/O placement problem. Advantages: exact, efficient. Proposed a complete placement flow for performance-driven placement under I/O placement constraints.