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1 Pixel Area Detector Development at NSRRC Kuan-Li Yu, Te-Hui Lee, Hui-Fang Chuang, Hsin-Wei Chen, Chao-Chih Chiu, Duan-Jen Wang 2011/06/13.

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Presentation on theme: "1 Pixel Area Detector Development at NSRRC Kuan-Li Yu, Te-Hui Lee, Hui-Fang Chuang, Hsin-Wei Chen, Chao-Chih Chiu, Duan-Jen Wang 2011/06/13."— Presentation transcript:

1 1 Pixel Area Detector Development at NSRRC Kuan-Li Yu, Te-Hui Lee, Hui-Fang Chuang, Hsin-Wei Chen, Chao-Chih Chiu, Duan-Jen Wang 2011/06/13

2 2 Outlines Sensor ASIC: preamp, comparator, counter Bump bonding Readout system –Timing control –Interlock –Data transfer and display

3 3 Operation Principle

4 4 Background Knowledge We started from scratch since We learned sensor design from BNL. We learned microstrip detector installation and operation from D. Peter Siddons at BNL.

5 5 General Specification Detector area x mm Sensor pixels per area detector81,320 x 40 = 3,252,800 (3 M pixels) Module per area detector8 x 5 = 40 modules Frame rate10 frame per second (fps) Chips per module2 x 4 Pixel size170 x 170 um 2 Energy range6 ~ 30 keV Counter in chip16 or 20 bit (two operation mode) Charge amplifier (CS AMP + shaper) 4 gains 0.25 V/fC, 0.5 V/fC, 1 V/fC, 2V/fC Intermodule gap between sensor to sensor area (Vertical) 3.4 mm, 20 pixels Sensor guard ring, wire bonding pads and mechanical structure Intermodule gap between sensor to sensor area (Horizontal) 1.7 mm, 10 pixels Sensor guard ring and mechanical structure.

6 6 Sensor

7 7 Sensor Structure

8 8 Sensor Wafer 6 inches

9 9

10 10 ASIC

11 11 ASIC ASIC is designed by outsourcing t-WIN Technology Service Inc and manufactured by MXIC. –http://www.t-win.com.twhttp://www.t-win.com.tw Analog Front End (AFE) –Preamp, shaper –High-pass filter –DAC, comparator Pseudo Random Counter (PRC) Serial Peripheral Interface (SPI) –Parameters settings –Counter values reading

12 12 Requirements of Analog Front End CS amplifier and shaper Input: 50 nA/10 ns = 0.5 fC (10 keV photons) Output: amplification 2 V/fC Power consumption = 24 uW –Operation current = 8 V Time response < 1 us Implementation area 4,000 um 2 Radiation hardened Low Equivalent Noise Charge (ENC)

13 13 Input current pulse Output signal

14 14 AFE Test IC 2.8 mm Preamp + shaper One pixel Preamp + shaper + comparator

15 15 Pixel Circuit Analog Front End (AFE) Pseudo Random Counter (PRC) Serial Peripheral Interface (SPI)

16 16 Analog Front End (AFE) preampshaper Threshold DAC comparator Amplification selection

17 17 Pseudo Random Counter (PRC) Overflow detection

18 18 Pseudo Random Counter (PRC) 20-bit counting mode 20-bit reading mode Used=1,048,575,CLKNUM=1,048,576, %, Last=0X7FFFF, First=0XFFFFF FFFFF(0),FFFFE(1),FFFFC(2),FFFF8(3),FFFF1(4),FFFE3(5),FFFC7(6),FFF8E(7),FFF1C(8),FFE38(9),FFC71(10),FF8E3( 11),FF1C7(12),FE38E(13),FC71C(14),F8E38(15),F1C71(16),E38E3(17), …., 7FFFF

19 19 Pixel Layout AFE PRC SPI 170 um

20 20 Power Consumption Estimation AFE : –CSA(9)+SHP(9)+CMP(7.5)+BIAS(4.5)+DAC(4.5) = 35 uA SPI : –60 uA when clock running PRC : –30 uA when clock running Total working current/pixel: 40 uA ~ 50 uA Power Consumption –45 x 106 x 94 x 8 = A –3.587 A x 3 V = W –10.76 W/(66 mm x 38.3 mm) = 0.42 W/cm 2

21 21 Heat Conduction Experiment (14 W) Mechanical support Aluminum nitride plate Copper plate WaterCu Plate TT 27 °C40 °C13 °C Water Heat load will be smaller Smaller and shorter PCB Embedded water pipe

22 22 Power Management in One Pixel Counting mode –AFE ON, PRC ON, SPI OFF Reading mode –AFE OFF, PRC ON, SPI ON Standby mode –AFE OFF, PRC OFF, SPI OFF

23 23 Bump Bonding Process

24 24 Bump Bonding Platform load cell prism microscope Vacuum chuck

25 25 Motor controller Control computer

26 26 Readout System

27 27 Readout System

28 28 Serial Control Board (SCB) Indium

29 29 Memory Control Board (MCB)

30 30 Timing Control Board (TCB) Power supply to MCB and SCB Data transfer timing and exposure time control Synchronization of all modules Interlock signal monitoring –Cooling water flow and temperature –HV bias leakage current –SCBs temperature monitoring HV bias voltage supply and control

31 31 Image Data Transfer High pulsatile data rate is converted to sustained slower data rate by FIFO memory time Data rate

32 32 SCB to MCBWrite data to FIFO 20-bit PRC decode MCB Timing Control 1 usec

33 33 Data Transfer Speed Serial to parallel conversion speed –20 MHz x 8 =160 Mbps PRC decoding speed –16-bit PRC = 16 bit/125 ns = 128 Mbps –20-bit PRC = 20 bit/200 ns = 100 Mbps National Instruments (NI) PCIe 6537 parallel interface –16 bit x 50 MHz/4 MCB = 200 Mbps Estimated data transfer time for one module –203,300 / 20,000,000 * 1.5 ≒ 15.2 ms (20-bit) –162,640 / 20,000,000 * 1.5 ≒ 12.2 ms (16-bit)

34 34 Start count Image Combine and Display SAMBA Report received images Image Viewer (FITS)

35 35 Develop a device support for areaDetector module Write a driver inherits from ADDriver tpsDetector

36 36 Schedule July 2011: AFE Test IC Dec. 2011: Single operational module Aug. 2012: Integrated 40 modules Dec. 2012: Integrated with EPICS control

37 37 Thank you for your attention.

38 38 Serial Control Board (SCB) Mechanical support for ASIC and sensor Wire bonding with ASIC Thermal conduction for ASIC heat dissipation

39 39 Memory Control Board (MCB) SCB ASIC parameter settings Serial to parallel signal conversion engine FIFO data flow control Pseudo Random Counter (PRC) –Lookup table generation –Hardware decode (20-bit, 200 ns) SCB and ASIC temperature monitoring


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