# Floorplanning. Non-Slicing Floorplan Representation Rectangle-Packing-Based Module Placement, H. Murata, K. Fujiyoushi, S. Nakatake and Y. Kajitani, IEEE.

## Presentation on theme: "Floorplanning. Non-Slicing Floorplan Representation Rectangle-Packing-Based Module Placement, H. Murata, K. Fujiyoushi, S. Nakatake and Y. Kajitani, IEEE."— Presentation transcript:

Floorplanning

Non-Slicing Floorplan Representation Rectangle-Packing-Based Module Placement, H. Murata, K. Fujiyoushi, S. Nakatake and Y. Kajitani, IEEE International Conference on Computer-Aided Design, 1995, pages 472-479. Rectangle-Packing-Based Module Placement, H. Murata, K. Fujiyoushi, S. Nakatake and Y. Kajitani, IEEE International Conference on Computer-Aided Design, 1995, pages 472-479.

Sequence Pair (SP) A floorplan is represented by a pair of permutations of the module names: e.g. 1 3 2 4 5 3 5 4 1 2 A sequence pair (s 1, s 2 ) of n modules can represent all possible floorplans formed by the n modules by specifying the pair-wise relationship between the modules.

Sequence Pair Consider a pair of modules A and B. If the arrangement of A and B in s 1 and s 2 are: –(…A…B…, …A…B…), then the right boundary of A is on the left hand side of the left boundary of B. –(…A…B…, …B…A…), then the upper boundary of B is below the lower boundary of A.

Example Consider the sequence pair: (13245,41352 ) Any other SP that is also valid for this packing? 2 5 4 1 3

Floorplan Realization Floorplan realization is the step to construct a floorplan from its representation. How to construct a floorplan from a sequence pair? We can make use of the horizontal and vertical constraint graphs (G h and G v ).

Floorplan Realization Whenever we see (…A…B…, …A…B…), add an edge from A to B in G h with weight w A. Whenever we see (…A…B…, …B…A…), add an edge from B to A in G v with weight h A. Add a source vertex s to G h and G v pointing, with weight 0, to all vertices without incoming edges. Finally, find the longest paths from s to every vertex in G h and G v (how?), which are the coordinates of the lower left corner of the module in the packing.

Example 2 5 4 1 3 (13245,41352 ) 2 1.2 1 1.1 1 1.2 2 2.41.2 1 32 5 4 1.1 2.4 s 0 0 GhGh 1 32 5 4 s 0 0 GvGv 1 1 1 2

Constraint Graphs How many edges are there in G h and G v in total? Is there any transitive edges in G h and G v ? How to remove the transitive edges? Can we reduce the size of G h and G v to linear, i.e., no. of edges is of order O(n), by removing all the transitive edges?

Moves Three kinds of moves in the annealing process: M1: Rotate a module, or change the shape of a module M2: Interchange 2 modules in both sequences M3: Interchange 2 modules in the first sequence Does this set of move operations ensure reachability? Why?

Pros and Cons of SP Advantages: –Simple representation –All floorplans can be represented. –The solution space is finite. (How big?) Disadvantages: –Redundant representation. The representation is not 1-to-1. –The size of the constraint graphs, and thus the runtime to construct the floorplan, is quadratic.

Questions Is the SP representation for general non- slicing floorplan P-admissible? Can we improve the runtime to realize a floorplan from its SP representation? (FAST-SP: A Fast Algorithm for Block Placement on Sequence Pair, X. Tang and D.F. Wong, ASP-DAC 2001, pp. 521-526.)

Mosaic Floorplan Representation Revisiting Floorplan Representations, B. Yao, H. Chen, C.K. Cheng and R. Graham, International Symposium on Physical Design, 2001, pages 138-143. Revisiting Floorplan Representations, B. Yao, H. Chen, C.K. Cheng and R. Graham, International Symposium on Physical Design, 2001, pages 138-143.

Mosaic Floorplan A mosaic packing can be represented by a pair of twin binary trees: A B C D E F C AF D E B T1T1 B AE D C F T2T2

Twin Binary Trees An arbitrary pair of trees may not correspond to a valid packing. They must be twin binary to each other, i.e., their labelings are complement of each other.

Labeling The labeling of a tree T can be obtained by traversing the tree in in-order and append a bit 0 (1) to the labeling if a node, except the leftmost (rightmost) node, with no left (right) child is visited: C AB D C AB D 1 1 0 Labeling of T = 101 T

Twin Binary Trees A B C D E F C AF D E B T1T1 B AE D C F T2T2 1 1 1 0 0 0 0 1 1 Labeling of T 1 = 10011 0 Labeling of T 2 = 01100

Floorplan Representations Slicing Floorplan: –A New Algorithm for Floorplan Design, DAC 1986, pp. 101- 107. Mosaic Floorplan: –Corner Block List: An Effective and Efficient Topological Representation of Non-slicing Floorplan, ICCAD 2000, pp. 8-12. –The Quarter-State Sequence (Q-sequence) to Represent the Floorplan and Applications to Layout Optimization, ASP-DAC 2000, pp. 829-832. –Revisiting Floorplan Representations, ISPD 2001, pp. 138-143.

Floorplan Representations Non-slicing Floorplan: –Rectangle-Packing-Based Module Placement, ICCAD 1995, pp. 472-479. –Module Placement on BSG-structure and IC Layout Applications, ICCAD 1996, pp. 484-491. –An O-tree Representation of Non-slicing Floorplan and its Applications, DAC 1999, pp. 268-273. –B*-tree: A New Representation for Non-slicing Floorplans, DAC 2000, pp. 458-463. –TCG: A Transitive Closure Graph-based Representation for Non- slicing Floorplans, DAC 2001, pp. 764-769. –Twin Binary Sequences: A Non-redundant Representation for General Non-slicing Floorplan, ISPD 2002, pp. 196-201.

Similar presentations