Other: NSF-Funded NSEC, Center for High-Rate Nanomanufacturing (CHN): High-rate Directed Self-Assembly of Nanoelements Nanotemplate: Layer of assembled nanostructures transferred to a wafer. Template is intended to be used for thousands of wafers. Nanotube Memory Device Partner: Nantero first to make memory devices using nanotubes Properties: n onvolatile, high speed at 10 15 cycles), resistant to heat, cold, magnetism, vibration, and cosmic radiation. Proof of Concept Testbed
Simple Carbon Nanotube Switch Diameter: 1.2 nm Elastic Modulus: 1 TPa Electrostatic Gap: 2 nm Binding Energy to Substrate: 8.7x10 -20 J/nm Length at which adhesion = restoring force: 16 nm Actuation Voltage at 16 nm = 2 V Resonant frequency at 16 nm = 25 GHz Electric Field = 10 9 V/m or 10 7 V/cm + Geom. (F-N tunneling at > 10 7 V/cm) Stored Mechanical Energy (1/2 k x 2 ) = 4 x 10 -19 J = 2.5 eV 4 x 10 -19 = ½ CV 2 gives C = 2 x 10 -19 F << electrode capacitance! Much more energy stored in local electrodes than switch.
NEMS Switch Fabrication: To be discussed. (a) Silicon chip with 500 nm of thermally grown oxide, 20 nm of tungsten, and PMMA. (b) Electron beam lithography was used to define features in the PMMA layer. An ICP etch was used to pattern the tungsten and etch down into the oxide. (c) A Cr/Au layer was evaporated and lifted off by removing the tungsten. (d) DEP was performed to assemble a small bundle of nanotubes traversing the trench between the two side electrodes.
NEMS Switch Operation (a) Scanning electron micrograph of a switch. Atomic force microscopy scans before (b) and after (c) switch actuation. (d) Initial (solid lines), second (dashed lines), and third (dotted lines) I-V sweeps for the device seen in (a-c). This device had a vertical gap of 24 nm and a trench width of 195 nm.