1. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 1 1 Chapter 12 Field Programmable Gate Array Testing

2. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 2 2 What is this chapter about?  Field Programmable Gate Arrays (FPGAs)  Have become a dominant digital implementation media  Reconfigurable to implement any digital logic function  Focus on  Testing challenges due to programmability and complexity  Overview of testing approaches  Test and diagnosis of various resources  New frontiers in FPGA testing

3. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 3 3 FPGA Testing  Overview of FPGAs  Architecture, Configuration, & Testing Problem  Testing Approaches  BIST of Programmable Resources  Logic Resources –Logic Blocks, I/O Cells, & Specialized Cores –Diagnosis  Routing Resources  Embedded Processor Based Testing  Concluding Remarks

4. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 4 4 Field Programmable Gate Arrays  Configuration Memory  Programmable Logic Blocks (PLBs)  Programmable Input/Output Cells  Programmable Interconnect Typical Complexity = 5 million – 1 billion transistors

5. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 5 5 11100110100010001001010100010111 0001010010101010100100100010001 01010010010011001001000011110001 1001010001000011001000101000100 1001001000101001010101001001001 0100010100101000101001010010001 0010101011101010101010101010101 01011110111110000000000000011010 01111100001001110000011100100101 00000000111110010010001010011100 10010100001111000111000100101010 1010101010101001010010101010010 0101010101010101001001001 Basic FPGA Operation  Writing configuration memory (configuration)  defines system function  Input/Output Cells  Logic in PLBs  Connections between PLBs & I/O cells  Changing configuration memory data (reconfiguration)  changes system function  Can change at anytime  Even while system function is in operation –Dynamic partial reconfiguration

6. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 6 6 FPGA Architectures  Early FPGAs  NxN array of unit cells –Unit cell = CLB + routing l Special routing along center axes  I/O cells around perimeter  Next Generation FPGAs  MxN array of unit cells  Added small block RAMs at edges  More Recent FPGAs  Added larger block RAMs in array  Added multipliers  Added Processor Cores (PC)  Latest FPGAs  Added DSP cores w/multipliers  I/O cells along columns for BGA PC

7. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 7 7 Combinational Logic Functions  Gates are combined to create complex circuits  Multiplexer example  If S = 0, Z = A  If S = 1, Z = B  Common digital circuit  Heavily used in FPGAs –Select input (S) controlled by configuration memory bit A S B Z 0101 ABSABS Z Logic symbol 0 1 S A B Z 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 Truth table

8. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 8 8 Look-up Tables  Using multiplexer example  Configuration memory holds truth table  Input signals connect to select inputs of multiplexers to select output value of truth table for any given input value 0101 ABSABS Z Multiplexer S A B Z 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 Truth table B A S 0101 Z 0101 0101 0101 0101 0101 0101 0 0 1 1 0 1 0 1 1 0 1 1

9. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 9 9 Basic Prog. Logic Block (PLB) Structure  Look-up table (LUT) for combinational logic  Store truth table in LUT (typically 3 to 6 inputs)  Some LUTs can also act as RAM/shift register  Flip-flops for sequential logic  Programmable clock enable, set/reset  Special logic  Large logic functions with Shannon expansion  Fast carry for adders and counters carry in LUT/ RAM Carry & Control Logic Flip-flop/ Latch 4 carry out 3 Control Output Q output Input[1:4] clock, enable, set/reset

10. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 10 10 Data In Address Decoder Write Enable In0 In1 In2 en0 en1 en2 en3 en4 en5 en6 en7 Look-up Table Based RAMs  Normal LUT mode performs read operations  Address decoder with write enable generates load signals to latches for write operations  Small RAMs but can be combined for larger RAMs In0 In1 In2 0101 Z 0101 0101 0101 0101 0101 0101 0 0 1 1 0 1 0 1 Read Address Write Address

11. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 11 11 Bi- directional Buffer Tri-state Control Output Data Input Data to/from internal routing resources Pad Input/Output Cells  Bi-directional buffers  Programmable for input or output signals  Tri-state control for bi-directional operation  Flip-flops/latches for improved timing –Set-up and hold times –Clock-to-output delay  Pull-up/down resistors  Routing resources  Connections to core of array  Programmable I/O voltage & current levels

12. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 12 12 Interconnect Network  Wire segments of varying length  xN = N PLBs in length –Typical values of N = 1, 2, 4, 6, 8  Long lines –xH = half the array in length –xL = full array in length  Programmable Interconnect Points (PIPs)  Transmission gate connects to 2 wire segments –Controlled by configuration memory bit  Four basic types of PIPs config bit Wire A Wire B

13. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 13 13  Break-point PIP  Connect or isolate 2 wire segments  Cross-point PIP  2 nets straight through  1 net turns corner and/or fans out  Compound cross-point PIP  Collection of 6 break-point PIPs –Can route 2 isolated signal nets  Multiplexer PIP  Directional and buffered  Main routing resource in recent FPGAs  Select 1-of-N inputs for output –Decoded MUX PIP – N configuration bits select from 2 N inputs –Non-decoded MUX PIP – 1 configuration bit per input Programmable Interconnect Points

14. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 14 14 Recent Architectural Trends  Addition of specialized cores:  Memories –Single and dual-port RAMs –FIFO (first-in first-out) –ECC (error correcting codes)  Digital signal processors (DSPs) –Multipliers –Accumulators –Arithmetic/logic units (ALUs)  Embedded processors –Hard core (dedicated processors) l With dedicated program/data memories l Otherwise, programmable RAMs in FPGA used for program/data memories –Soft core (synthesized from a HDL) = PLBs = I/O cells = special cores = routing resources

15. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 15 15 FPGA Resources  Types and sizes of resources vary with FPGA family  Example: LUTs vary from 3-input to 6-input –4-input LUTs are most common  Typical ranges for some commercially available FPGAs FPGA ResourceSmall FPGALarge FPGA Logic PLBs per FPGA 25625,920 LUTs and flip-flops per PLB 18 Routing Wire segments per PLB 45406 PIPs per PLB 1393,462 Specialized Cores Bits per memory core 12836,864 Memory cores per FPGA 16576 DSP cores 0512 Other Input/output cells 621,200 Configuration memory bits 42,10479,704,832

16. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 16 16 Configuration Interfaces  Master mode (Serial or Parallel options)  FPGA retrieves configuration from ROM at power-up  Slave (Serial or Parallel options)  FPGA configured by external source (i.e., a  P)  Used for dynamic partial reconfiguration  Boundary Scan Interface  4-wire IEEE standard serial interface for testing  Write and read access to configuration memory  Interfaces to FPGA core internal routing network  Not available in all FPGAs clock PROM with Config Data data out CCLK FPGA in Master Mode Din Dout CCLK FPGA in Slave Mode Din Dout CCLK FPGA in Slave Mode Din Dout

17. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 17 17 FPGA Configuration Memory  PLB addressable  Good for partial reconfiguration  X-Y coordinates of PLB location to be written –“Z” coordinate identifies which resources will be configured  Frame addressable  Vertical or horizontal frame –Vertical frames most common  Access to all PLBs in frame –Only portion of logic and routing resources accessible in a given frame –Many frames required to configure PLBs & routing

18. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 18 18 Configuration Techniques  Full configuration & readback  Simple configuration interface –Automatic internal calculation of frame address  Long download time for large FPGAs  Partial reconfiguration & readback  Only change portions of configuration memory with respect to reference design –Reduces download time for reconfiguration  Requires a more complicated configuration interface –Command Register (CMR) –Frame Length Register (FLR) –Frame Address Register (FAR) –Frame Data Register (FDR)

19. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 19 19 Configuration Techniques  Compressed configuration  Requires multiple frame write capability –Write identical frames of config data to multiple frame addresses  Extension of partial reconfiguration interface capabilities –Frame address is much smaller than frame of configuration data  Reduces download time for initial configuration depending on –Regularity of system function design –% utilization of array l Unused portions written with default configuration data

20. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 20 20 FPGA Testing Taxonomy Test Approach AttributeClassification Test pattern application and output response analysis Internal (BIST)External System-level testingOff-lineOn-line System applicationIndependentDependent Target programmable resources LogicRouting PLBsI/O cellsCoresLocalGlobal  On-line test while system is operational  Off-line test while system is out-of-service  Application-dependent testing tests only those FPGA resources used by intended system function  Application-independent testing tests all FPGA resources

21. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 21 21 FPGA Test Configurations  More test configurations required for routing resources than for logic resources  Data below from publications on actual test configuration implementations in commercial FPGAs FPGANumber of Test Configurations VendorSeriesPLBsRoutingCoresReference Lattice ORCA2C9270 [Abramovici 2001] [Stroud 2002b] ORCA2CA14410 AtmelAT40K/AT94K4563[Sunwoo 2005] CypressDelta39K2041911[Stroud 2000] Xilinx 4000E/Spartan121280 [Stroud 2003] 4000XL/XLA122060 Virtex/Spartan-II1228311[Dhingra 2005] Virtex-415? [Milton 2006]

22. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 22 22 A Simple PLB Architecture  Two 3-input LUTs  Can implement any 4-input combinational logic function  Can implement full adder –Carry in LUT C –Sum in LUT S  1 flip-flop  Programmable: –Active levels –Clock edge –Set/reset  22 configuration memory bits  8 per LUT –C7-C0 and S7-S0  6 control bits –CB5-CB0 Cout D2-0 D3 FF CB 4 Clock Set/Reset Sout 01 CB 3 01 01 01 Clock Enable CB = Configuration Memory Bit Smux CEmux SRmux SOmux CB 5 CB 1 CB 0 CB 2 LUT C 8x1 LUT S 8x1 3 C0C0C0C0 C1C1C1C1 C2C2C2C2 C3C3C3C3 C4C4C4C4 C5C5C5C5 C6C6C6C6 C7C7C7C7 111 110 101 100 011 010 001 000 D2-0 out LUT

23. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 23 23 Test Configurations for Simple PLB  All configuration memory bits must be tested for both logic values (0 and 1) assuming exhaustive input patterns  Output effects for each logic value must be observed  Exclusive-OR (XOR) and exclusive-NOR (XNOR) functions are good for testing LUTs  Put opposite functions in adjacent LUTs to produce opposite logic values at inputs to subsequent logic functions  Fault coverage results below are based on collapsed single stuck-at gate-level fault model (174 faults total) Configuration BitsConfiguration #1Configuration #2Configuration #3 LUT C (C7 - C0)XNOR (01101001) XOR (10010110) LUT S (S7 - S0) XOR (10010110)XNOR (01101001) CB0 - CB5000010111110000001 Individual FC149/174 = 85.6% 108/174 = 62.1% Cumulative FC85.6%97.7%100%

24. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 24 24 BIST for FPGAs  Basic idea:  Program some logic resources to act as –Test pattern generators (TPGs) –Output response analyzers (ORAs) –Resources under test l Logic resources as blocks under test (BUTs) l Routing resources as wires under test (WUTs)  Goal:  Minimize number of test configurations to minimize download time –Download time dominates total test time

25. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 25 25 TPG and ORA Implementations  TPG implementation depends on test algorithm  May be implemented in different resources (see table below)  Multiple TPGs prevent faulty TPG from escaping detection  Lower bound on number of PLBs per TPG, T PLB = B IN  N FF –B IN = number of inputs to BUT –N FF = number of FFs/PLB  ORAs most efficiently implemented in PLBs  Number of PLBs needed for ORAs, O PLB = (N BUT × B OUT )  N FF –B OUT = number of outputs from BUT –N BUT = number of BUTs Resource Under TestTPGsORAs PLBsPLBs or DSP coresPLBs LUT RAMsPLBs or DSP and RAM coresPLBs I/O cellsPLBs or DSP and RAM coresPLBs Cores (memories, DSPs, etc.)PLBs InterconnectPLBs

26. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 26 26 TPG Algorithms  Small logic functions (PLBs, IOBs) can be tested with pseudo-random test patterns  LFSRs or counting patterns  Large logic functions (RAMs, DSPs) require specialized test algorithms for high fault coverage  Below are examples of typical RAM test algorithms Algorithm March Test Sequence March Y ↨ (w0); ↑(r0, w1,r1); ↓(r1, w0, r0);↑(r0) March LR w/o BDS ↨ (w0); ↓(r0, w1); ↑(r1, w0, r0, r0, w1); ↑(r1, w0); ↑(r0, w1, r1, r1, w0); ↑(r0) March LR with BDS ↨ (w00); ↓(r00, w11); ↑(r11, w00, r00, r00, w11); ↑(r11, w00); ↑(r00, w11, r11, r11, w00); ↑(r00, w01, w10, r10); ↑(r10, w01, r01); ↑(r01) Notation: w0 = write 0 (or all 0’s), r1 = read 1 (or all 1’s) ↑= address up, ↓= address down, ↨ = address either way

27. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 27 27 Output Response Analyzers  Comparison-based  XOR with OR feedback from flip-flop –Latches mismatches observed due to faults  Results retrieval  ORA with shift register –Requires additional logic  Configuration memory readback –Read contents of ORA flip-flops l Good with partial configuration memory readback capabilities Pass/ Fail BUT j output n BUT k output n BUT j output 1 BUT k output 1 Pass/ Fail shift data shift mode BUT j output BUT k output Pass/ Fail BUT j output BUT k output

28. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 28 28 Logic Resource BIST Architectures  Basic comparison  Multiple TPGs drive alternating columns (rows) of blocks under test (BUTs)  BUTs in center of array observed by 2 sets of ORAs and compared with 2 other BUTs  BUTs along edges of array observed by only 1 set of ORAs –Some loss of diagnostic resolution  Originally used to test PLBs –Later used to test specialized cores Basic Comparison =TPG =BUT =ORA

29. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 29 29 Logic Resource BIST Architectures  Circular Comparison  Multiple TPGs drive alternating columns (rows) of blocks under test (BUTs)  All BUTs observed by 2 sets of ORAs and compared with 2 other BUTs –Good diagnostic resolution  Originally used to test specialized cores –Later used to test PLBs and I/O cells Circular Comparison =TPG =BUT =ORA

30. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 30 30 Logic Resource BIST Architectures  Expected Results comparison  Multiple TPGs –One set of TPGs drive BUTs –Other set of TPGs produce expected results for comparison with outputs of BUTs  BUTs observed by 1 set of ORAs and compared with expected results from TPGs –Simple diagnosis since failing ORA position indicates faulty BUT  Good when expected results can be algorithmically generated easily –Example: RAM test algorithms  Originally used to test RAM cores Expected Results expected results test patterns =TPG =BUT =ORA

31. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 31 31 Logic Resource Diagnostic Procedure 1.Record ORA results; 1= failure indication. 2.For every set of 2 or more consecutive ORAs with 0s, enter 0s for all BUTs observed by these ORAs; the BUTs are fault- free. 3.For every adjacent 0 and 1 followed by an empty space, enter 1 to indicate BUT is faulty; continue while such entries exist. 4.If an ORA indicates a failure but both BUTs monitored by the ORA are fault-free, one of the following conditions exist: A.A fault in routing resources between one of the BUTs and the ORA, B.ORA is faulty, or C.There are more than 2 consecutive BUTs with equivalent faults (for circular comparison only); reorder circular comparison and repeat test and diagnostic procedure. 5.Remaining BUTs marked as unknown may be faulty; reorder circular comparison or rotate basic comparison architecture by 90 , repeat test and diagnostic procedure.

32. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 32 32 Diagnostic Procedure Examples  Note that B4 and B5 have equivalent faults in Example A  Circular comparison provides better diagnostic resolution  Also indicates when more than 2 consecutive BUTs with equivalent faults (Example C) Example AExample BExample C BIST ArchitectureBasicCircularBasicCircularBasicCircular Diagnostic Step123123123123123123 B100000000100 O12000000000000111111 B2000000000000 O23000000000000000000 B3000000000000 O34111111111111000000 B411110000 O45000000111111111111 B511?1100 O56111111111111001000 B6?00?00100 O61000000000

33. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 33 33 Testing Routing Resources  Comparison-based BIST approach  Developed for on-line FPGA BIST  Testing restricted to routing resources for 2 rows or 2 columns of PLBs  Small Self-Test AReas (STARs)  Comparison-based ORA  Later applied to off-line BIST  Fill FPGA with STARs  Tests run concurrently  Diagnostic resolution to STAR  Easier BIST development  But more BIST configurations STAR WUTs TPG ORA FPGA T O T O T O T O T O

34. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 34 34 Testing Routing Resources  Original parity-based BIST approach  Parity bit routed over fault-free resources –What is fault-free until you’ve tested it?  Modified parity-based approach  N-bit up-counter with even parity, and  N-bit down-counter with odd parity –Gives opposite logic values for l Stuck-on PIPs & bridging faults  Parity used as test pattern –N+1 wires under test  Good for small PLBs –like our simple PLB example  Make STARs as small as possible  Better diagnostic resolution  Easier BIST development parity-checkbased-ORA WUTs paritybit TPG ORA ORAORAORAORA WUTs TPG C1C1C1C1 Par + C0C0C0C0

35. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 35 35 Testing Routing Resources  Testing typically separated by routing resources  Global - interconnects non-adjacent logic resources  Local - interconnects adjacent logic resources and connects logic resources to global routing  Additional test configurations swap positions of TPGs and ORAs to reverse direction of signal flow to test directional, buffered routing resources  Multiplexer PIPs are a good example =TPG =ORA global routing local routing PLB feed-through local routing adjacent PLBs

36. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 36 36 Reducing Test Time  Orient BIST architecture to configuration memory  Align along rows/columns depending on FPGA structure  Downloading BIST configurations  Compressed configuration for initial download  Partial reconfiguration for subsequent downloads –Reduce number of frames written between configurations l Keep routing constant between BIST configurations l Optimize order of BIST configuration application  Retrieving BIST results  Partial configuration memory readback –Eliminates ORA logic for scan chain l Allows concurrent testing of more resources –Minimize number of frames to be read  Dynamic partial reconfiguration –Read BIST results after a series of BIST configurations l Slight loss in diagnostic resolution

37. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 37 37 Embedded Processor Based BIST  New area of R&D in FPGA testing  Basic idea:  Embedded processor core –Hard or soft core  Configures FPGA for BIST –Via internal configuration access port (ICAP) l Alternative: download initial BIST configuration  Executes BIST sequence –May provide TPG functionality  Retrieves BIST results –May perform diagnostic procedure  Reconfigures FPGA for subsequent BIST configurations  Soft core requires two test sessions to test area occupied by processor core during first test session = ORA = BUT Processor core, TPGs and interface to ICAP circuitry Test session #1 Processor core, TPGs and interface to ICAP circuitry Test session #2

38. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 38 38 Embedded Processor BIST  Overall reduction in total test time  Algorithmic reconfiguration faster than external download –  10 to 25 times faster –Results below from actual implementation in commercial FPGA  Can be loaded into processor program memory for on-demand BIST and diagnosis of FPGA  Good for fault-tolerant applications where system function is reconfigured around diagnosed fault(s) ResourceFunctionExternalProcessorSpeed-up PLB BIST Download7.680 sec0.101 sec76.0 Execution0.016 sec0.085 sec0.2 Total time7.696 sec0.186 sec41.4 Routing BIST Download20.064 sec0.110 sec182.4 Execution0.026 sec0.343 sec0.075 Total time20.090 sec0.453 sec44.3 Total Test Time27.786 sec0.639 sec 43.5

39. EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 39 39 Concluding Remarks  Growing use of FPGAs in systems and SOCs  FPGA testing is necessary but difficult due to  Programmability  Complex programmable interconnect network  Constantly growing size and changing architectures  Incorporation of new and different specialized cores  Test & diagnosis allows fault-tolerant applications  New FPGA capabilities assist in testing solutions  Dynamic partial reconfiguration and readback  Configuration/reconfiguration by embedded processor cores