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O RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 Pixel : LS1, Run2 and Fase 2 Slides per Clara 17 September 2014 G. Darbo–

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Presentation on theme: "O RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 Pixel : LS1, Run2 and Fase 2 Slides per Clara 17 September 2014 G. Darbo–"— Presentation transcript:

1 o RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 Pixel : LS1, Run2 and Fase 2 Slides per Clara 17 September 2014 G. Darbo– INFN / Genova Indico agenda: https://agenda.infn.it/conferenceDisplay.py?confId=8420

2 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Activities – 2015 Plan 2014: CSN1 funded (Feb and May) R&D Phase 2 activities for ATLAS & CMS inner trackers. Development of 3D and Active Edge sensors with FBK – 3 Batches (ATLAS/CMS) Bump-bonding: development of Indium bumps (6” sensors) and produce modules Develop a technology for pixel detector hybridization using C (dielectric) instead of R (bump-bonding) coupling Completion of CO2 test plant (combined ATLAS / LHCb) 2015: Activities and line of funding Continue with 3D Sensor plan: produce modules, test in lab and TB, irradiate, procure sensors for next FBK run. Bump-bonding: for testing FBK sensors and to develop for future RD53 requirements CO 2 cooling: contribute to ATLAS stave R&D, thermal simulation and test with CO 2 plant Multi-module R/O: use leading experience of ROD designer (BO) to develop a 16 module table-top road for architecture study and for test-beam application. Upgrade to USBPix3: most diffused single module system based on USB. Upgrade also for use if HV/HR-CMOS HV/HR-CMOS: presented a new project in CSN5 (BO, GE, MI)

3 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September D Sensor Program Planned 3 run at FBK in 2014 – Funded by CSN1 in Feb No.1: DRIE process setting up for thin columns. Process in completion. Found that 5-6 µm are the best suitable column diameter. No.2: test planar process with SiSi DWB and Epi substrates. Layout completed, mask submission, wafer expected in 6 weeks. No.3: 3D single side process with SiSi DWB and Epi substrates. Layout in discussion. Compatible layout with other foundries (CNM) to simplify common test of devices. Note: A second 3D run is foreseen at the end of 2015 / early 2016 – layout matching RD-53 layout. Schedule presented in Feb’14. Still up to date. Need approval from MEMS3 committee of 3 rd batch! Schedule presented in Feb’14. Still up to date. Need approval from MEMS3 committee of 3 rd batch!

4 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September FBK: Status of Batches Batch 1: study of columns In measurement Batch 2: study SiSi subtrates Mask submitted 158 um 5.6 um 3.8 um CMSATLAS Test structures for Si-Si qualification Batch 3: 3D sensors Layout study and Simulation of a 3D pixel cell

5 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September CCPD Hybridization HV/HR-CMOS chip coupled capacitively to R/O chip (CCPD – Capacitively Coupled Pixel Detector) instead of “classic” bump-bonding Develop a technique to insert uniform, well defined thickness of dielectric between R/O and HV/HR-CMOS chips Should be a cost effective, rad-hard process to transfer to industry Test program in progress: See preliminary results next slide Activities will continue in the HVR_CCPD project in CSN5 (new experiment) Involving BO, GE & MI Also scientists outside ATLAS will participate. R/O CHIP Process Recipe Spin SU-8 photoresist Pattern pillars by mask Spacer define the distance between chips Target to D = 5 µm, C ~ 4 fF for 18 µm pad diameter. Proper qualified glue Glue deposition R/O CHIP DETECTOR CHIP Align & pressure

6 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Deposition of Pillars (spacers) 2-inch mask below with different Densities of spacers – FE-I4/FE-I3 Structures. SU deposited on 2-inch wafer from Siegert Credits: V. Ceriale FE-I4 with matrix of SU8 spacers: 200 µm x 200 µm columns 4.7 µm high FE-I4 with matrix of SU8 spacers: 40 µm x 40 µm columns 4.7 µm high

7 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September CO 2 Cooling Plant

8 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Milestones

9 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September SPARE SLIDES

10 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September D Sensors – Proposed Process New generation of 3D sensors 6” wafer new process at FBK Smaller pixel (event pileup) reduce column distance (2x10 16 n eq /cm 2 ) Thinner pixel (≤1.5ke threshold) TCAD simulation: Optimal Q, Lower C det,… Bias voltage applied to back side (as IBL) Single side 3D process on: Si-Si DWB (Direct Wafer Bonding) Epitaxial wafers P + Epi layer / P + High Ωcm wafer P ++ Low Ωcm wafer -V b Charge Amp. Bump-bond 100÷150µm metal Thin-down TCAD capacitance simulation Layout: 2 n-columns in 25x150 µm 2 Total capacitance for d col =5µm 100 µm thick  71 fF/pix 150 µm thick  88 fF/pix It was 200 fF/pix for IBL Single side 3D process p ++ col n ++ col Epi – SiSi DWB

11 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September DRIE for Ohmic Columns 158 um 5.6 um 3.8 um 7.6 um

12 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September DRIE for Junction Columns ID#Nominal diameter (um) Depth (um) Surface diameter (um) Diameter at tip (um) LEFT CENTER RIGHT

13 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Planar test batch CMSATLAS Test structures for Si-Si qualification p-type SiSi DWB wafers from ICEMOS 100-mm and 130-mm HR active sensor thickness p-spray & p-stop isolation Layout ready, masks ordered To start now, to be completed in 6-7 weeks

14 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Wafers Sets – To Bump-Bond In program 4 sensor batches that would need BB in 2014/15: 3D double side – October - Funds (MI) assigned for 2014 Planar ATLAS/CMS Batch 2 – November – Funds (FI/PI) assigned D and Active edge batches coming 2015 – no funds yet. In 2015 request 14 ATLAS FE-I4 (13x) CMS Single chip (24x) (1E, 2E, 3E, 4E) CMS Quads (6x) (2E, 3E) MEDIPIX2 (4x) NA62 test chip (20x) CMSATLAS Test structures for Si-Si qualification 3D Double Side BatchPlanar ATLAS/CMS “Batch 2”

15 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September SU Results 1.26 µm of bow. Column highs are very uniform: 4.7 µm over 2 cm Results obtained with a spinning rotation of 2500 rpm and SU Profile scan direction

16 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Future Plan: M-Module R/O Le caratteristiche della scheda sono: Completa compatibilità firmware e software con il ROD/BOC IBL ROD/BOC in one card Possibilità di operare senza crate (table-top) Connessione ottica o elettrica di 16 FE-I4 Possibilità di connessione esterna via Gbit ETH, S-Link (Modalità compatibile con FW/SW IBL) Possibilità di utilizzo per test GBT/FELIX, con uscita PCIe e protocolli Infiniband, rapid-io, GBe Costi: Prototipaggio e fabbricazione di due schede 10 k€ Realizzazione di 5 schede per i laboratori italiani 15 k€ Componenti off-shelf per il sistema 10 k€ Attività BO-GE Prototipi 2015 Produzione 5 schede 2016

17 RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September Got Funded 3D Funded 3 batches at FBK: Mechanical test – approved by MEMS3 committee – order placed (3x2200 €) Simple planar to qualify substrates – approved by MEMS3 – order placed (6x2200 €) 3D batch, single side, on hold waiting batch 2. Substrates Ordered 55 wafers from IceMOS (SiSi wafer bonded) – material is on shipment Looking for Epi wafers – indirect contact with SHINETSU – offer received (25 wafers – 11.9 kCHF) – doubts on specifications (epi-layer thickness spread: 104÷156 µm!) Bump-bonding Funded 20 k€ for BB at Selex + 7 k€ for FE-I4B Bump-bond 3D sensors in production at FBK – old design IBL-like Develop In-bumps for high density – incomplete funding (cut the dummy wafers). HV-CMOS hybridization FE-I4B plus consumables to test hybridization CO2 cooling Funded TRACI CO2 cooler


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