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115 December 2003Luciano Musa Radiation tests of the TPC FEE CERN, 30 August 2004 Luciano Musa – CERN / PH - ED Content System overview Radiation Levels.

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Presentation on theme: "115 December 2003Luciano Musa Radiation tests of the TPC FEE CERN, 30 August 2004 Luciano Musa – CERN / PH - ED Content System overview Radiation Levels."— Presentation transcript:

1 115 December 2003Luciano Musa Radiation tests of the TPC FEE CERN, 30 August 2004 Luciano Musa – CERN / PH - ED Content System overview Radiation Levels at the TPC Radiation Facilities and Test Setup Characterization (TID and SEE) of the FEC components Custom (ALTRO and PASA) COTS (LDO, VREF, AMPLIFIERS, TRANSCEIVERS, BUFFERS, CAP., etc.) FPGA (ALTERA ACEX1K30) Characterization of RCU  see the talks of D. Röhrich and C. Soos

2 215 December 2003Luciano Musa Local Monitor and Control BOARD Controller RCU DCS ( 1 MB/s ) DDL ( 200 MB/s ) COUNTING ROOM Each of the 36 TPC Sectors contains 6 Readout Partitions COTS, FPGA ON DETECTOR Overall TPC: 4356 Front End Card 216 RCUs Bus controller ( conf. & R/O ) FEC 128 ch 1 1 2 2 12 13 DCS int. (Ethernet) DAQ int. (DDL-SIU) Trigger int. (TTC-RX) FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch CUSTOM, COTS, FPGA DETECTOR TTC optical Link (Clock, L1 and L2 ) Data Proc. and Memory System Overview PASSIVE COMPONENTS capacitors and resistors

3 315 December 2003Luciano Musa Sum Flux with E kin > 10MeV (cm -2 s -1 ) Layers1234 absorber side384268187129 Non-absorber side245149112 81 TID @ TPC in 1.6 krad @ TPC out 0.22 krad Georgios Tsiledakis, GSI Simulation with 4 scoring regions Radiation Levels at the TPC Agreement with A, Morsch and B. Pastircak ALICE-INT-2002-28 Version 1.0

4 415 December 2003Luciano Musa Radiation Facilities and Test Setup Test (I) 2002 DUT Collimator Beam Type: 65 MeV protons Proton Flux: 1·10 8, 5·10 8 p cm -2 s -1 100 krad in 30 min at this flux Labview Server X Server with Labview 2 m Ethernet Line Labview Monitor Test Bench Scintillator Attenuator Test at UCL, Louvain-la-Neuve, Belgium

5 515 December 2003Luciano Musa Test Setup for ALTRO and LDO PC Monitors status and errors Continuous current monitoring Analog card Regulator test on daughtercard Radiation Facilities and Test Setup Test (I) 2002

6 615 December 2003Luciano Musa Collimator ALTRO chip Regulator Test Fixture Test (I) 2002 Radiation Facilities and Test Setup

7 715 December 2003Luciano Musa PASA 0.35 µm CMOS EPROM (CMOS) Clock Driver 0.18 µm CMOS Analog Buffer CMOS Radiation Facilities and Test Setup Test (I) 2002 FRONT END CARD

8 815 December 2003Luciano Musa GTL Transceivers (BiCMOS) Voltage Reference (Bipolar) Radiation Facilities and Test Setup Test (I) 2002 FRONT END CARD

9 915 December 2003Luciano Musa Collimator Test Card used to monitor current Radiation Facilities and Test Setup Test (I) 2002

10 1015 December 2003Luciano Musa Radiation Facilities and Test Setup Test (II) 2003 - 2004 Oslo Cyclotron  25 and 28 MeV external proton beam  flux ~ 10 7 – 10 8 protons/s cm²  Beam profile: spot 1.5cm x 1.5cm Test (III) 2004 TSL (Uppsala)  38 and 180 MeV external proton beam  flux ~ 10 7 – 10 8 protons/s cm²  Beam profile: spot  3cm

11 1115 December 2003Luciano Musa Radiation Facilities and Test Setup Test Setup for COTS and FPGA Test (II) and TEST (III) 2003 - 2004

12 1215 December 2003Luciano Musa Tested Parts (1/2) NameType Technology No. Parts TID (krad) ALTRO-16ADC + DPCMOS 4312 PASAShaping/AmpCMOS 4 96 MIC39151Volt. Reg.Bipolar12 30 MIC29371Volt. Reg. Bipolar10 30 TC1173Volt. Reg.Bipolar 6 40 LP3962/61Volt. Reg.CMOS 3 30 TI757Volt. Reg.CMOS 2 30 OPA4364OpAmpBipolar 5 30 AD8604OpAmpCMOS 8 30 MAX4254OpAmpCMOS 1 30 TC1265Ref. Volt.CMOS 2 84 LM4140Ref. Volt.Bipolar 10 30

13 1315 December 2003Luciano Musa Tested Parts (2/2) NameType Technology No. Parts TID (krad) LM4040 / 41Ref. Volt.Bipolar 10 30 LM385Ref. Volt.Bipolar10 30 STM-TS821 / 2Ref. Volt.CMOS 4 30 GTL16612TransceiverBi-CMOS 8 48 MPC9109BufferCMOS 6100 BAT54DiodeBipolar 4 30 MMBT2222ABJTBipolar 4 30 Electrolytic CapCapacitorsTantalum20 100 EPC1441EPROMCMOS10 ACEX1K30FPGACMOS 5 100 TOTAL NUMBER OF TESTED PARTS 146

14 1415 December 2003Luciano Musa Custom Components - ALTRO Register Check 2004 bits PM Check 163840 bits DM Check 655360 bits Write Pattern in Regs and Mem Reset ALTRO ALTRO Status Register Check Current Check ADC Signal Check Reset requested Y N Start ALTRO Test Loop

15 1515 December 2003Luciano Musa analog current standby digital current register errors PM errors DM errors SEU errors and other protocol errors ADC spikes and SEU error counters test phase power status Custom Components - ALTRO ALTRO Test Program

16 1615 December 2003Luciano Musa Memory Error Cross Section:1.10·10 -14 cm 2 bit -1 Register Error Cross Section:7.02·10 -14 cm 2 bit -1 Hamming Error Cross Section:7.50·10 -14 cm 2 bit -1 1 > 00 > 1 Error Cross Section Slightly more flips from 1 to 0 than from 0 to 1 Digital current increases with dose (leakage increases) Analog current stays the same ADC bit flips very rare Small spikes in analog part of ADC above 160 krad Observations total current digital standby current bit-flip ratio Test Results Custom Components - ALTRO

17 1715 December 2003Luciano Musa After 2 weeks at room temperature: 43 mA standby current (+13.5% over total) After 3 months at room temperature: back to normal At a low flux, annealing and damage may compensate Annealing All 4 irradiated chips continue to work today Custom Components - ALTRO Test Results

18 1815 December 2003Luciano Musa Registers Pedestal Memory Data Memory Hamming Machines SEU per hour MTBF 0.0230.361.430.0007 36 hours168 minutes42 minutes58 days For a sub-sector equipped with 200 ALTROS (1 RCU) Worst-case figure Innermost Readout Partition @ absorber side System Level Consequences Custom Components - ALTRO

19 1915 December 2003Luciano Musa PASA Test Results No variations in current consumption No variations in baseline level No variations in gain Negative spikes observed frequently (due to high flux) Test Procedure Monitoring of current consumption Repetitive acquisition of output of 16 ch. Monitoring of baseline value Monitoring of gain Automatic spike detection Test Results (TID = 96 krad) Negative spikes in the baseline 0 70 ADC COUNTS

20 2015 December 2003Luciano Musa COTS – Voltage Regulators beam stopped Switch-off still works MIC39151 8 krad MIC39151 died after 30 krad (switch-off still possible) MIC39151 still usable for the TPC. Batch dispersion might be an issue 50 krad25 krad

21 2115 December 2003Luciano Musa COTS – Reference Voltage Generators (1% output variation @ 45Krad) (~21KRad/min) (output stable within 0.3 %) LM4041 (1.2V) LM4040 (2.5V) Voltage Time (hh:mm:ss)

22 2215 December 2003Luciano Musa COTS – Operational Amplifier (Output stable ‘till ~140 Krad)

23 2315 December 2003Luciano Musa (variations of 10 % in Vce-sat every ~140KRad) COTS – Bipolar Transistor

24 2415 December 2003Luciano Musa (up to 120KRad) COTS – Tantalum Capacitors Voltage Time (ms) 15uF / 10 V

25 2515 December 2003Luciano Musa COTS – Other Results GTL16612 max TID > 80 krad SEU cross section 1.15·10 -12 cm 2 bit -1 MPC9109 max TID > 50 kradSEU cross section 1.3·10 -12 cm -2 bit -1 EPC1441preserves configuration at TID > 20krad

26 2615 December 2003Luciano Musa COTS – FPGA (ACEX1K30) TID is not a problem at the TPC levels Two types of concern ● Upsets in configuration SRAM cells ● Single bit-flips in register elements (can be avoided by design) The ACEX1K30 offers no direct readout of configuration SRAM ● Indirectly detection of configuration upset through the internal logic

27 2715 December 2003Luciano Musa 11001 1110101001 10001 11000 11011 00111 1011100011 00101 00110 01111  Finite State Machine (FSM) protected by Hamming encoding  Basic principle 00000 1000001000 00100 00010 00001 State A State B State C X Returns to the associated state if there is no external signal producing a state transition The arrival of X produces the transition from A to B 1Bit-flip (SEU) The signal Y produces The transition form B to C, Y 01100 Doble Bit-flip Error Arquitectura del Chip ALTRO SEU Protection

28 2815 December 2003Luciano Musa Serial Slow Control Network SCSN FPGA Data in Data out Serial Slow Control Network SCSN 0000000 1000000 0100000 0010000 0001000 0000100 0000010 0000001 0000000. 0000000 1000000 0100000 0010000 0001000 0000100 0000010 0010001 0000000. 0000000 A fixed pattern is shifted through and compared for setups when read out. COTS – FPGA (ACEX1K30) Upset detection in ACEX devices

29 2915 December 2003Luciano Musa COTS – FPGA (ACEX1K30) Device Conf. BitsCross Sec ACEX1K30470 000410 -11 cm 2 Error rate per run (4 hours)Error rate per run per device per system FEC 1.15*10 -4 0.52 Detection of configuration loss by BIST FPGA reconfigured by on board EPROM


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