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Confidential Material MAX 10 FPGAs - Overview Tom Schulte Low Cost Product Marketing 5/9/2014.

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Presentation on theme: "Confidential Material MAX 10 FPGAs - Overview Tom Schulte Low Cost Product Marketing 5/9/2014."— Presentation transcript:

1 Confidential Material MAX 10 FPGAs - Overview Tom Schulte Low Cost Product Marketing 5/9/2014

2 Innovation Leader Across the Board PLDs Lowest Cost, Lowest Power PowerSoCs High-efficiency Power Management FPGAs Cost/Power Balance SoC & Transceivers Design Software Development Kits Embedded Soft and Hard Processors FPGAs Mid-range FPGAs SoC & Transceivers R ESOURCES FPGAs Optimized for High Bandwidth Intellectual Property (IP)  Industrial  Computing  Enterprise 2

3 Low Cost Families – Altera Continues Focus & Investment More performance, features, or density MAX ® II CPLD Products MAX V FPGA Products Cyclone ® Cyclone II Cyclone III Cyclone IV In Design Next Generation MAX 10 Cyclone V SoC Cyclone V SoC Product Planning Future Delivering Next Generation Products

4 MAX 10 FPGAs: Revolutionizing Non-Volatile Integration FPGA Capabilities  Up to 50,000 Logic Elements  Analog Block with ADC  Internal SRAM  PLLs  DSP Blocks  External Memory Interface (e.g. DDR3)  Dual Image Configuration  Nios II Embedded Processor  LVDS, PCI, and 30+ other I/O Standards  Design Security  Sleep Mode Non-volatile Features  Instant-On  User Flash Memory  Voltage Regulator  Internal Oscillator 4

5 MAX 10 FPGAs Simplify FPGA Systems 5 Traditional FPGA (Up to 50k LE) ADC 3.3V I/O Dual Image Configuration Device Analog 1.2V 2.5V3.3V MAX 10 FPGA (Up to 50k LE) 3.3V I/O Analog 3.3V LDO Analog Block Dual Image Configuration Memory Instant-On Configuration V supply LDO V supply Traditional FPGAMAX 10 FPGAs Standard Configuration Time

6 CPLD MAX 10 FPGAs Increase Capabilities of CPLD Systems 6 3.3V I/O MAX 10 FPGA 3.3V I/O Analog Block Single Image CPLDMAX 10 FPGAs Logic Elements240 – 8,0002,000 – 50,000 Instant-On ImagesSingleDual DSPNoYes DDR3 SDRAMNoYes Analog Block w/ADCNoYes Embedded ProcessorNoNios II External Memory Interface Single Image Dual Image DSP User Flash (Nios code)

7 MAX 10 vs. Prior Family – Higher Single Chip Integration FeatureMAX V CPLDsMAX 10 FPGAs Process Technology180 nm55 nm User Logic (max.)2,000 LE’s50,000 LE’s On-chip ConfigurationSingle ImageDual Image, AES User I/O271Up to 500 User Flash Memory8 KbUp to 512 Kb On-chip hard IP blocks- Embedded RAM, DSP, ADC, PLL Remote System UpgradeNoYes 7 Lowering System Cost & Increasing Reliability

8 MAX 10 FPGA - Floorplan Main Architecture Modules  Logic array  On-chip RAM & FLASH  DSP blocks  Up to two analog blocks  Up to eight I/O banks  Up to four PLL’s  Oscillator & Clocks  Soft IP functionality Nios ® II 32-bit processor, Ethernet MAC, PCIe MAC, Video IP Suite, etc. RAM Blocks PLL’SExternal Memory Interfaces Analog Blocks DSP Blocks Logic Array Blocks Config. Flash User Flash 8 Control Block

9 MAX 10 FPGA – Family Plan 9 DeviceLEs Block Memory (Kb) User Flash 1 (Kb) 18x18 Mults PLLs Internal Config. ADC 4, TSD External RAM I/F 10M022, , 2Single- Yes 2 10M044, , 2Dual1, 1 Yes 2 10M088, , 2Dual1, 1 Yes 2 10M1616, , 4Dual1, 1Yes 3 10M2525, , 4Dual2, 1Yes 3 10M4040,0001, , 4Dual2, 1Yes 3 10M5050,0001, , 4Dual2, 1Yes 3 Preliminary and subject to change without notice. Notes: 1.Additional User Flash may be available, depending on configuration options. 2.SDR SDRAM or SRAM only. 3.SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2. 4.ADC blocks available on die but may not be available in low pin count packages.

10 MAX 10 FPGA - Feature Set Options Three Feature Set Variants To Order From Feature SetC: CompactF: FlashA: Analog Single ImageYes Dual Image w/Remote System Upgrade -Yes Analog Features Block--Yes “C” “F” “A” 10

11 Package Plan & Available I/O (Dual Power Supply: 1.2V/2.5V) 11 Product Line 36-WLCSP 3x3mm 2 0.4mm Pitch 81-WLCSP 4x4mm 2 0.4mm Pitch 256-FBGA 17x17mm 2 1.0mm Pitch 324-UBGA 15x15mm 2 0.8mm Pitch 484-FBGA 23x23mm 2 1.0mm Pitch 672-FBGA 27x27mm 2 1.0mm Pitch 10M02 “D”C (27) - -C (160)-- 10M04 “D”- - C/F/A (178)C/F/A (246)-- 10M08 “D”-C/F (56)C/F/A (178)C/F/A (246)C/F/A (250)- 10M16 “D”-- C/F/A (178)C/F/A (246)C/F/A (320) - 10M25 “D”-- C/F/A (178) - C/F/A (360)C/F/A (380) 10M40 “D”-- C/F/A (178) - C/F/A (360)C/F/A (500) 10M50 “D”-- C/F/A (178) - C/F/A (360)C/F/A (500) C: Compact F: Flash A: Analog Preliminary and subject to change without notice Wide Variety of Sizes & Available I/O WLCSPxBGA U = 0.8mm ball spacing F = 1.0mm ball spacing Bare Die Note: Selected items = Pro-active automotive p/n rollout. Other product line/package combinations available upon request & sufficient ROI.

12 Package Plan & Available I/O (Single Power Supply: 3.3V) 12 Product Line 144-EQFP 16x16 mm mm Pitch 153-MBGA 8x8mm 2 0.5mm (1) 169-UBGA 11x11mm 2 0.8mm 10M02 “S”C (101)C (112)C (130) 10M04 “S”C/F/A (101)C/F/A (112)C/F/A (130) 10M08 “S”C/F/A (101)C/F/A (112)C/F/A (130) 10M16 “S” C/F/A (101) - C/F/A (130) 10M25 “S” C/F/A (101) -- 10M40 “S” C/F/A (101) -- 10M50 “S” C/F/A (101) -- C: Compact F: Flash A: Analog Preliminary and subject to change without notice Notes: 1 – “Easy PCB” utilizes 0.8mm PCB design rules 2 - Items in blue = Pro-active automotive p/n’s. Others available upon request & sufficient ROI. Single Supply Option for Simplicity & Convenience xBGA M = 0.5mm ball spacing U = 0.8mm ball spacing EQFP Bare Die

13 MAX 10 FPGA Ordering Information 13 10M 16 x x u484 i 7 x ßß Family 10M: MAX 10 FPGA Product Line 02: 2K LE’s 04: 4K LE’s 08: 8K LE’s 16: 16K LE’s 25: 25K LE’s 40: 40K LE’s 50: 50K LE’s Power Supply S: Single Voltage D: Dual Voltage Package Type & Ball Count V: Wafer level chip-scale E: EQFP M: MBGA U: UBGA F: FBGA 36, , , 484, 672 Grade / Temperature C: Commercial (T J = 0°C to +85°C) I: Industrial (T J = -40°C to +100°C) A: Automotive (T J = -40°C to +125°C) Speed 6, 7, 8 6 = fastest, 8 = slowest ES G = RoHS 6 P = Leaded ßß = Special processing Optional Suffix Feature Option C: Compact features F: Flash features A: Analog features

14 MAX 10 FPGA I/O Standard Support I/O StandardVariantToggle Rate 1 (MHz)Max StrengthLoadApplication Single-Ended LVTTL/LVCMOS 3.3V2 mA10 pFGeneral purpose LVTTL/LVCMOS 3.0V25016 mA10 pFGeneral purpose LVTTL/LVCMOS 2.5V25016 mA10 pFGeneral purpose LVTTL/LVCMOS 1.8V25012 mA10 pFGeneral purpose LVTTL/LVCMOS 1.5V2508 mA10 pFGeneral purpose LVTTL/LVCMOS 1.2V2008 mA10 pFGeneral purpose PCI pFGeneral purpose Schmitt Trigger (RX only)200--General purpose External Memory Interfaces (& Voltage Referenced I/O) SSTL2 Class I25012mA/50 W7 pFDDR1 SSTL2 Class II25016 mA/25 W7 pFDDR1 SSTL18 Class I30012mA/50 W7 pFDDR2 SSTL18 Class II30016 mA/25 W7 pFDDR2 SSTL15 Class I30012mA/50 W7 pFDDR3 SSTL15 Class II30016 mA/25 W7 pFDDR3 SSTL W7 pFDDR3 SSTL W7 pFDDR3L HSUL W7 pFLPDDR2 HSTL18 Class I30012mA/50 W7 pFDDR2+/QDR2+/RLDRAM2 HSTL18 Class II30016 mA/25 W7 pFDDR2+/QDR2+/RLDRAM2 HSTL15 Class I30012mA/50 W7 pFDDR2+/QDR2/QDR2+/RLDRAM2 HSTL15 Class II30016 mA/25 W7 pFDDR2+/QDR2/QDR2+/RLDRAM2 HSTL12 Cass I20012 mA/50 W7 pFGeneral purpose HSTL12 Class II20014 mA/25 W7 pFGeneral purpose LVDS Dedicated LVDS (RX/TX) 3 830/800 Mbps-6 pF 2 Dedicated Mini-LVDS (TX) Mbps-6 pF 2 Dedicated RSDS (TX) Mbps-6 pF 2 Dedicated PPDS (TX) Mbps-6 pF 2 External Resistor LVDS (TX)600 Mbps-6 pF 2 External Resistor Mini-LVDS (TX)380 Mbps- 6 pF 2 External Resistor RSDS (1R) (TX)170 Mbps- 6 pF 2 External Resistor RSDS (3R) (TX)342 Mbps- 6 pF 2 External Resistor PPDS (TX)420 Mbps- 6 pF 2 LVPECL (RX only)830 Mbps 6 pF 2 BLVDS (RX/TX)830/475 Mbps16 mA6 pF 2 14 Notes: 1.Toggle rate (maximum) assumes max. drive strength, fastest slew rate setting for the specified load, and fastest speed grade (–c6). 2.Measured on a single pin, not pair. 3.Only available on the bottom I/O banks (Bank3, Bank4).

15 Rev Early Device Program  Limited # of customers  ES and/or EAP device shipments  10M04, 08, 40, and 50 ES p/n’s  Early.POF /.SOF support 2014 Early Software Program  Limited # of customers  Hidden S/W in v13.1 (10M08 only)  Production S/W in v14.0 (all devices)  Compilation & early timing  EPE Early Information Program  Unlimited # of customers  Monthly bulletins  Advanced Info. Brief  Preliminary handbook  Other “specials” Jul.Aug.Sept.Oct.Nov.Dec.Jan.Feb.Mar.Apr.MayJun.Jul.Aug.Sept.Oct.Nov.Dec. #1 - EIP #3 - EDP MAX 10 FPGA Device Handbook 3 Early Access Programs for MAX 10 FPGA Rev.14.0Rev.13.1 #2 - ESP

16 MAX 10 FPGAs Summary MAX 10 FPGAs revolutionize non-volatile integration  Single-chip, non-volatile solution with the smallest footprint  Only dual-persona single-ship, non-volatile solution  Integrated ADC and other system-cost saving hard IP  Up to 95% dynamic power savings via sleep mode  Ideal for both datapath and control plane applications 16 MAX 10 FPGA Devices MAX 10 FPGA Devices Non-VolatileFPGA

17 What’s Next? 1H 2014Early Information Program 2H 2014Devices & Dev Kits Shipping 17 Would you sign-up for monthly updates on MAX 10 FPGAs (with valid NDA)?

18 Confidential Material Back-Up Information

19 MAX 10 FPGA M153 Package – “Easy PCB” Footprint 19  Click to return to page 13 Intentionally created gaps in ball grid array to allow space for PCB traces and/or through-hole via’s. Goal: “Easy” PCB board design 1.Use 0.8mm pitch design rules instead of 0.5mm rules. 2 layer signal breakout (SMD on both component and PCB) 3 mil line/space 16 mil PTH Shared P/G PTH 2.Avoiding use of blind or buried via’s. 3.Minimize the number of PCB layers needed to route to all device pins. Note: Altera recommended PCB layout (preliminary) in 4Q mm 0.5mm

20 Thank You


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