1Tom Schulte Low Cost Product Marketing 5/9/2014 MAX 10 FPGAs - OverviewTom SchulteLow Cost Product Marketing5/9/2014This section is intended to show how the MAX 10 family fits into Altera’s portfolio, a high level look at the MAX 10 family including features & benefits, high level architecture, benefits vs. existing solutions, family plan, package plan, ordering code, schedules, and Early Access Programs.There is more high level content organized by architectural section (pages ). Use page 21 with embedded bookmarks to jump to the appropriate section and at the end of the subject section, it will return you back to page 21.
2Innovation Leader Across the Board PLDsLowest Cost, Lowest PowerFPGAsCost/Power BalanceSoC & TransceiversFPGAsMid-range FPGAs SoC & TransceiversFPGAsOptimized for High BandwidthPowerSoCsHigh-efficiency Power ManagementResourcesBefore we go into Altera’s Next Generation LOW COST PROGRAMMABLE DEVICES, let’s pause for a moment and consider the value that Altera brings as an Innovation leader across the board. We provide customers with the largest range of device offerings in the FPGA industryMAX brand CPLDsA wide range of FPGAs:(low-cost) Cyclone FPGAs(mid-range) Arria FPGAs(high-performance) Stratix FPGAsFPGA configuration devicesEnpirion power regulator modulesFPGA industry’s best design tools and IPQuartus II softwareQsys System Integration tool with System ConsoleDSP BuilderOpenCLARM & Altera’s Nios II 32-bit processor (16 bit version, planned), memory controllers, VIP Suite, etc.We also want to mention superior product lifecycle managementTypical 15 years+ lifecycle (2x longer than our peers)Periodic review of product lifecycles to minimize customer pain from obsoleting parts that are still in useSo, when customers partner with Altera, they are getting a width and breadth of products that no other Programmable supplier can offer.Embedded Soft and Hard ProcessorsDesignSoftwareDevelopmentKitsIntellectual Property (IP)IndustrialComputingEnterprise
3Low Cost Families – Altera Continues Focus & Investment More performance,features, or densityCyclone VSoCNextGenerationFPGA ProductsCyclone VCyclone IVCyclone IIICyclone IICyclone®MAX 10DeliveringNext Generation ProductsLooking back the past 10 years, Altera has consistently invested in the Low Cost PLD market segment.End applications & customers using Low Cost Products remains an Altera Corp. focus.Since the FPGA market is growing ~ 2x the rate of the CPLD growth, we’ve introduced more Cyclone-class FPGAs over this period of time.The CPLD market is still important to Altera’s strategy & growth.I think we have “demonstrated” our commitment to the Low Cost PLD product segment by introducing more low-cost families than any other PLD supplier.The new MAX 10 FPGAs architecture will have features and densities of both the MAX CPLD and Cyclone FPGA product segments.MAX 10 will complement but not replace existing MAX II, MAX V, Cyclone IV, and Cyclone V families... In some cases, the new family will offer more features, at lower costs.Altera also continues to collect customer feedback for Altera’s next generation low-cost architectures.CPLD ProductsMAX VMAX® II20002013FutureIn DesignProduct Planning333
4MAX 10 FPGAs: Revolutionizing Non-Volatile Integration FPGA CapabilitiesUp to 50,000 Logic ElementsAnalog Block with ADCInternal SRAMPLLsDSP BlocksExternal Memory Interface (e.g. DDR3)Dual Image ConfigurationNios II Embedded ProcessorLVDS, PCI, and 30+ other I/O StandardsDesign SecuritySleep ModeNon-volatile FeaturesInstant-OnUser Flash MemoryVoltage RegulatorInternal OscillatorMAX 10 is a full featured, general purpose programmable logic family that combines a large number of FPGA features listed here along with all the easy to use features normally associated with CPLDs.
5MAX 10 FPGAs Simplify FPGA Systems Traditional FPGAMAX 10 FPGAsVsupplyVsupplyLDOLDOLDO3.3V1.2V2.5V3.3VDual ImageConfiguration DeviceTraditional FPGA(Up to 50k LE)3.3V I/ODual ImageConfiguration MemoryMAX 10 FPGA(Up to 50k LE)3.3V I/OShown on the left is a typical FPGA design along with external components frequently used next to an FPGA.On the right is the MAX 10 implementation, reducing a 6 component solution into 2 components (both available from Altera) and getting into user mode in a few milliseconds (vs. FPGA implementations typically in the 100’s of milliseconds).AnalogAnalogADCAnalog BlockStandardConfiguration TimeInstant-OnConfiguration
6MAX 10 FPGAs Increase Capabilities of CPLD Systems External MemoryInterfaceCPLD3.3VI/OAnalogMAX 10 FPGAUser Flash(Nios code)AnalogBlock3.3V I/ODSPSingle ImageSingleImageDual ImageCPLDMAX 10 FPGAsLogic Elements240 – 8,0002,000 – 50,000Instant-On ImagesSingleDualDSPNoYesDDR3 SDRAMAnalog Block w/ADCEmbedded ProcessorNios IIShown on the left is a typical CPLD design with limited capabilities. On the right is the MAX 10 implementation, providing options to significantly increase the functionality of typical electronic systems…even the option to add “smart” capability with 32-bit embedded processing which could augment or replace microcontrollers.
7MAX 10 vs. Prior Family – Higher Single Chip Integration FeatureMAX V CPLDsMAX 10 FPGAsProcess Technology180 nm55 nmUser Logic (max.)2,000 LE’s50,000 LE’sOn-chip ConfigurationSingle ImageDual Image, AESUser I/O271Up to 500User Flash Memory8 KbUp to 512 KbOn-chip hard IP blocks-Embedded RAM, DSP, ADC, PLLRemote System UpgradeNoYesHere is a quick feature comparison with MAX V CPLDs. You can see that MAX 10 FPGAs add a lot of NEW features which customers can take advantage of to lower total system cost and achieve higher reliability.Using the latest fab process technology from TSMC, 55nm embedded flash + SRAM, Altera is able to fit many more features on a single programmable chip.More user logic, more on-chip memory, more, more, more, as compared to prior MAX CPLDsAnd, just to be clear, while both products are branded “MAX”, the MAX 10 device is a non-volatile FPGA…more than a CPLD.Lowering System Cost & Increasing Reliability
8Main Architecture Modules MAX 10 FPGA - FloorplanDSP BlocksMain Architecture ModulesLogic arrayOn-chip RAM & FLASHDSP blocksUp to two analog blocksUp to eight I/O banksUp to four PLL’sOscillator & ClocksSoft IP functionalityNios® II 32-bit processor, Ethernet MAC, PCIe MAC, Video IP Suite, etc.RAM BlocksAnalog BlocksConfig.FlashUser FlashControl BlockHere’s a look at the floorplan of a typical MAX 10 FPGA device.You’ll see that logic is organized into the familiar columnar structure with Logic Array Blocks, RAM blocks, and DSP blocks organized vertically up and down the die. It’s got up to 8 I/O banks around the periphery of the die – with multiple banks per side offering more choices for different I/O support per device.The I/O can interface to a variety of different voltage levels and I/O standards.The larger density device members (10M16 – 10M50) support the main-stream external memory interfaces: DDR3, DDR2 and LPDDR2. Interfacing to legacy external memory, such as Single Data Rate SDRAM or SRAM, are available on every product.You can see the analog block (or blocks) in the top left of the die. I’ll describe that in more detail in a few moments.Plus there’s the Configuration Flash Memory and User Flash Memory also in the top left hand side of the die.Internal configuration memory Internal configuration memory has the following customer benefits: faster startup time, less board space, and a smaller bill of materials…compared to devices that require external configuration. Another customer benefit of internal configuration storage, increased security because there are no exposed programming interfaces and therefore no way to intercept a configuration bit stream coming into the FPGA because, well, there isn’t one.And, just for clarification, the on-chip FLASH is NOR type memory which is much more reliable than NAND type memory.Logic Array BlocksExternal Memory InterfacesPLL’S
9MAX 10 FPGA – Family Plan Device LEs Block Memory (Kb) User Flash 1 MultsPLLsInternalConfig.ADC 4, TSDExternalRAMI/F10M022,00010896161, 2Single-Yes 210M044,00018912819Dual1, 110M088,0003782562410M1616,000549451, 4Yes 310M2525,000756612, 110M4040,0001,26051212510M5050,0001,638144Here is the family table showing the resources of the family…ranging from 2,000 user logic elements (LE’s)…an ample amount of logic resources for the majority of control plane, simple glue logic functions…all the way up to 50,000 LE’s.There is an ample amount of on-chip RAM and FLASH memory…along with 18x18 multipliers that can be used for massively parallel DSP processing for things like filtering or image processing.High performance, low-jitter PLLs and global clock networks provide lots of on-chip clocking resources.The # of PLL’s available is dependent on the package option…lower pin-count packages only have 1 PLL, F256 or higher pin-count packages have the maximum number of PLLs available.Not shown here but the # of global clocks available = 10 or 20 (10M02-08 has 10 clocks, 10M16-50 has 20 clocks).All of the devices are self-configured and store the device image(s) within secure, integrated FLASH (this is NOT die stack…i.e. Xilinx Spartan-3AN).Another 1st for Altera…the inclusion of up to 2 on-chip analog blocks (ADC + temperature sensing diode).For the larger densities devices, we’ve added some on-chip optimization to simplify creating I/O interfaces to external double data rate SDRAM memories.Note 1 - Under certain conditions, additional on-chip FLASH memory will be available to the user…potentially another 500 Kbits up to 5 Mbits. This would be very useful for Nios CODE storage.Notes:Additional User Flash may be available, depending on configuration options.SDR SDRAM or SRAM only.SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2.ADC blocks available on die but may not be available in low pin count packages.Preliminary and subject to change without notice.
10MAX 10 FPGA - Feature Set Options C: CompactF: FlashA: AnalogSingle ImageYesDual Imagew/Remote System Upgrade-Analog Features Block“C” “F” “A”There are three feature set options in the family you can choose from…denoted with the letters C, F, and A.With a “C” class device, you will get a single boot image is stored within the device.With an “F” class device, you will get single-chip dual configuration image support (an industry 1st) and remote system upgrade capability.And, with an “A” class device, you will get all of the above plus the analog block.You can consider the C-version to be the “Compact” version, which will be the least expensive option for customers. The “F” and “A” variants will give customers access to additional FUNCTIONS and thus will be priced higher than the “C” variant.Three Feature Set Variants To Order From
11Package Plan & Available I/O (Dual Power Supply: 1.2V/2.5V) ProductLine36-WLCSP3x3mm20.4mm Pitch81-WLCSP4x4mm2256-FBGA17x17mm21.0mm Pitch324-UBGA15x15mm20.8mm Pitch484-FBGA23x23mm2672-FBGA27x27mm210M02 “D”C (27)-C (160)10M04 “D”C/F/A (178)C/F/A (246)10M08 “D”C/F (56)C/F/A (250)10M16 “D”C/F/A (320)10M25 “D”C/F/A (360)C/F/A (380)10M40 “D”C/F/A (500)10M50 “D”Note: Selected items = Pro-active automotive p/n rollout.Other product line/package combinations available upon request & sufficient ROI.Preliminary and subject to change without noticeC: CompactF: FlashA: AnalogBesides the three feature set options, there are two voltage regulator options…with or without the on-chip voltage regulator permanently enabled.Let’s look at the Dual Power Supply PACKAGE options first (NOTE – these devices do NOT have the internal regulator enabled).The device density will range from one to 50 thousand logic elements with C, F, and A variants scattered across the package options as shown.Package sizes range from extremely small to larger BGA packages with ball pitch ranging from 0.4mm - 1.0mm ball.The number in the parenthesis equals the # of user I/O available, ranging from 27 to 500.Also, I wish to point out that even though we don’t ADVERTISE this on Altera.com, we do support selling bare die to select customers (INTERNAL NOTE: Customer opportunity must meet minimum order qty’s, ROI, legal addendum, and agree with technical restrictions).BareDieWLCSPxBGAU = 0.8mm ball spacingF = 1.0mm ball spacingWide Variety of Sizes & Available I/O
12Package Plan & Available I/O (Single Power Supply: 3.3V) ProductLine144-EQFP16x16 mm20.4 mm Pitch153-MBGA8x8mm20.5mm(1)169-UBGA11x11mm20.8mm10M02 “S”C (101)C (112)C (130)10M04 “S”C/F/A (101)C/F/A (112)C/F/A (130)10M08 “S”10M16 “S”-10M25 “S”10M40 “S”10M50 “S”Notes:1 – “Easy PCB” utilizes 0.8mm PCB design rules2 - Items in blue = Pro-active automotive p/n’s.Others available upon request & sufficient ROI.Preliminary and subject to change without noticeC: CompactF: FlashA: AnalogHere are the package options for the Single-Supply devices (NOTE – these have the internal regulator enabled):The device density will also range from one to 50 thousand logic elements.I/O counts range from 103 to 130 for the single power supply parts.Looking at the M153 package, we’ve devised an innovative way to provide customers with a small physical size package with good amount of I/O.<< click on the hyperlink to jump to a back-up slide illustrating this innovative new idea >>BareDiexBGAM = 0.5mm ball spacingU = 0.8mm ball spacingEQFPSingle Supply Option forSimplicity & Convenience
13MAX 10 FPGA Ordering Information OptionalSuffixFamily10M: MAX 10 FPGAESG = RoHS 6P = Leadedßß = Special processing10M 16 x x u484 i 7 x ßßProductLineSpeed6, 7, 86 = fastest,8 = slowest02: 2K LE’s04: 4K LE’s08: 8K LE’s16: 16K LE’s25: 25K LE’s40: 40K LE’s50: 50K LE’sPowerSupplyFeatureOptionPackage Type& Ball CountGrade /TemperatureHere is the part number format for the family. Please check with your Altera sales person for valid p/n’s since every permutation of the combination these features is not available. (NOTE – you can also get valid p/n’s from Quartus II s/w).S: Single VoltageD: Dual VoltageC: Compact featuresF: Flash featuresA: Analog featuresV: Wafer level chip-scaleE: EQFPM: MBGAU: UBGAF: FBGA36, 81144153169, 324256, 484, 672C: Commercial (TJ = 0°C to +85°C)I: Industrial (TJ = -40°C to +100°C)A: Automotive (TJ = -40°C to +125°C)
14MAX 10 FPGA I/O Standard Support VariantToggle Rate 1 (MHz)Max StrengthLoadApplicationSingle-EndedLVTTL/LVCMOS 3.3V2 mA10 pFGeneral purposeLVTTL/LVCMOS 3.0V25016 mALVTTL/LVCMOS 2.5VLVTTL/LVCMOS 1.8V12 mALVTTL/LVCMOS 1.5V8 mALVTTL/LVCMOS 1.2V200PCI-Schmitt Trigger (RX only)External Memory Interfaces(& Voltage Referenced I/O)SSTL2 Class I12mA/50 W7 pFDDR1SSTL2 Class II16 mA/25 WSSTL18 Class I300DDR2SSTL18 Class IISSTL15 Class IDDR3SSTL15 Class IISSTL1534 WSSTL135DDR3LHSUL12LPDDR2HSTL18 Class IDDR2+/QDR2+/RLDRAM2HSTL18 Class IIHSTL15 Class IDDR2+/QDR2/QDR2+/RLDRAM2HSTL15 Class IIHSTL12 Cass I12 mA/50 WHSTL12 Class II14 mA/25 WLVDSDedicated LVDS (RX/TX) 3830/800 Mbps6 pF 2Dedicated Mini-LVDS (TX) 3380 MbpsDedicated RSDS (TX) 3340 MbpsDedicated PPDS (TX) 3420 MbpsExternal Resistor LVDS (TX)600 MbpsExternal Resistor Mini-LVDS (TX)External Resistor RSDS (1R) (TX)170 MbpsExternal Resistor RSDS (3R) (TX)342 MbpsExternal Resistor PPDS (TX)LVPECL (RX only)830 MbpsBLVDS (RX/TX)830/475 MbpsProgrammable logic is frequently used to translate between different components which have different I/O voltage levels or I/O standards. As you can see, MAX 10 supports a large number of I/O options.(INTERNAL NOTE: The majority of die/pkg combinations are NOT available in the fastest speed grade. Please check the specific p/n’s to ensure it is available to quote and available in Quartus. For any questions on a p/n, please contact the nearest Low-Cost Product Marketing person).Notes:Toggle rate (maximum) assumes max. drive strength, fastest slew rate setting for the specified load, and fastest speed grade (–c6).Measured on a single pin, not pair.Only available on the bottom I/O banks (Bank3, Bank4).
153 Early Access Programs for MAX 10 FPGA 20132014Jul.Aug.Sept.Oct.Nov.Dec.Jan.Feb.Mar.Apr.MayJun.#1 - EIPRev.13.1Rev.14.0Rev.14.1#2 - ESPDevice HandbookMAX 10 FPGA#3 - EDPThere are three early access programs offered before the family is LAUNCHED. The goal is to get information to customers as soon as possible before the family is publically available.EIPBenefits to customers = Get information early to help decide if these devices can meet your technical requirements. The sign-up process:Customer to “opt-in” to receive s.Sales to fill out form (download from MOLSON) & to factoryESPIf you’re convinced MAX 10 devices can meet your technical requirements and your schedule requires early s/w and device deliveries in 2H 2014, speak with your local Altera sales person to see if you can be admitted into the S/W BETA program. We limit the number of customers because all the customer documentation isn’t yet available, so we have to support customers individually (we have a limited amount of resources).Selection criteriaCustomers must be willing to take BETA s/w, GUI’s, IP, limited documentation, etc.Or Altera partners working on key projects (IP, kits, or virtual ASSP)Or large $ opportunities (INTERNAL NOTE: Greater than $1M and must be Altera “friendly”)(INTERNAL NOTE: Approvals needed:Product Marketing & BU mgr. prioritization & approvals requiredFor Xilinx or Lattice “friendly” customers, BU director or Sales RVP approval needed )EDPThe goal is to align our first shipments of devices to customers who have proto schedules that can’t wait for Altera to complete all of the functional check-out prior to shipment.Early Information ProgramUnlimited # of customersMonthly bulletinsAdvanced Info. BriefPreliminary handbookOther “specials”Early Software ProgramLimited # of customersHidden S/W in v13.1 (10M08 only)Production S/W in v14.0 (all devices)Compilation & early timingEPEEarly Device ProgramLimited # of customersES and/or EAP device shipments10M04, 08, 40, and 50 ES p/n’sEarly .POF / .SOF support
16MAX 10 FPGAs revolutionize non-volatile integration MAX 10 FPGAs SummaryMAX 10 FPGAs revolutionize non-volatile integrationSingle-chip, non-volatile solution with the smallest footprintOnly dual-persona single-ship, non-volatile solutionIntegrated ADC and other system-cost saving hard IPUp to 95% dynamic power savings via sleep modeIdeal for both datapath and control plane applicationsMAX 10 FPGADevicesMAX 10 FPGAs are highly integrated devices offering many popular FPGA features along with other value added functions like analog to digital conversion, non-volatile memory capability, all packaged into a single, easy to design re-programmable device.MAX 10 FPGA devices can reduce the system cost if the DESIGN can take advantage of any of the on-chip hard IP blocks (RAM, FLASH, ADC, PLL, DSP, ETC.) allowing those functions implemented in other components to be absorbed into a single, programmable component.We didn’t talk about the details earlier but the new sleep mode can dramatically reduce the device’s dynamic power.The investment to get started and design for MAX 10 FPGA is minimal…all the s/w support is included in Altera’s Quartus II web edition, download it for free, and get your license file on-line. On-line training classes are also available.( INTERNAL NOTE: To handle any MAX 10 FPGA pricing questions, please download and reference the March 2014 (or later) MSVP price guidelines).FPGANon-Volatile
17What’s Next?1H 2014 Early Information Program2H 2014 Devices & Dev Kits ShippingIf you are interested in continuing to receive MAX 10 related information, would you sign up for the Early Information Program (EIP)?We need you to agree to “opt-in”.(INTERNAL NOTES:Must have mutual NDA legal agreement in place to participate in EIP program.Sales person should now take the time for “uncovering” to learn more about the customers interest, any project details, specific technical requirements, any things they didn’t like, etc. After this “uncovering” conversation, you can then move on to answering some technical questions starting on page 21.)Would you sign-up for monthly updates on MAX 10 FPGAs (with valid NDA)?
19MAX 10 FPGA M153 Package – “Easy PCB” Footprint Intentionally created gaps in ball grid array to allow space for PCB traces and/or through-hole via’s.Goal: “Easy” PCB board designUse 0.8mm pitch design rules instead of 0.5mm rules.2 layer signal breakout (SMD on both component and PCB)3 mil line/space16 mil PTHShared P/G PTHAvoiding use of blind or buried via’s.Minimize the number of PCB layers needed to route to all device pins.8mmAltera will create and update existing Application Note 114 – Design Guidelines for BGA packages to include a PCB layout recommendation for this new M153 package.0.5mm8mmNote: Altera recommended PCB layout (preliminary) in 4Q 2013Click to return to page 13