# EE 319K Introduction to Embedded Systems

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EE 319K Introduction to Embedded Systems
Lecture 10: Sampling, Analog-to-Digital Conversion Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline Local Variables Stack frames Recursion
Fixed-point numbers LCD device driver (Lab 7) Outline Sampling, Nyquist theorem Analog to Digital Conversion Bard, Gerstlauer, Valvano, Yerraballi

Bard, Gerstlauer, Valvano, Yerraballi

Nyquist Theorem A bandlimited analog signal that has been sampled can be perfectly reconstructed from an infinite sequence of samples if the sampling rate fs exceeds 2fmax samples per second, where fmax is the highest frequency in the original signal. If the analog signal does contain frequency components larger than (1/2)fs, then there will be an aliasing error. Aliasing is when the digital signal appears to have a different frequency than the original analog signal. Valvano Postulate: If fmax is the largest frequency component of the analog signal, then you must sample more than ten times fmax in order for the reconstructed digital samples to look like the original signal when plotted on a voltage versus time graph. Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 1) 200Hz signal sampled at 2000Hz
Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 1) 1000Hz signal sampled at 2000Hz
Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 1) 2200Hz signal sampled at 2000Hz This is aliasing
Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 2) 100Hz signal sampled at 1600Hz
Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 2) A signal with DC, 100Hz and 400Hz sampled at 1600Hz Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 2) 1500Hz signal sampled at 1600Hz This is aliasing
Bard, Gerstlauer, Valvano, Yerraballi

Successive approximation ADC VIN is approximated as a static value in a sample and hold (S/H) circuit the successive approximation register (SAR) is a counter that increments each clock as long as it is enabled by the comparator the output of the SAR is fed to a DAC that generates a voltage for comparison with VIN when the output of the DAC = VIN the value of SAR is the digital representation of VIN end of conversion Bard, Gerstlauer, Valvano, Yerraballi

Sample-And-Hold Circuit
S/H Analog Input (AI) is sampled when the switch is closed and its value is held on the capacitor where it becomes the Analog Output (AO) Bard, Gerstlauer, Valvano, Yerraballi

3.3V internal reference voltage 0x000 at 0 V input 0xFFF at 3.3 V resolution = range/precision = 3.3V/4096 alternatives < 1mV Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 PE2=Ain1 used for Lab 8, 9, 10
Twelve analog input channels Single-ended and differential-input configurations On-chip internal temperature sensor Sample rate up to one million samples/second Hz Flexible, configurable analog-to-digital conversion Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs Flexible trigger control Controller (software) We will use software initiated trigger Timers Analog Comparators PWM GPIO Hardware averaging of up to 64 samples for improved accuracy Converter uses an internal 3V reference Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 PE2=Ain1 used for Lab 8, 9, 10 Ain1PE2
Software initiated Use sequencer 3 Bit 3 is done flag Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 PD4=Ain4 used for DLL testing
PE2=Ain1 used for Lab 8, 9, 10 PE4=Ain9 used in book and ADCSWTrigger_4F120.zip Twelve different pins can be used to sample analog inputs. Bard, Gerstlauer, Valvano, Yerraballi

Bard, Gerstlauer, Valvano, Yerraballi

select trigger select channel select sample mode 0 not temperature 1 set completion flag 1 end sequence 0 not differential Speed bits in ADC0_PC_R EM3, EM2, EM1, and EM0 bits in ADC_EMUX_R ADC0_SSCTL3_R = 0x06; Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 Analog to digital conversion Set software trigger
Write to PSSI bit 3 Busy-Wait Raw Interrupt Status = RIS bit 3 Poll until sample complete Read sample Read from SSFIFO3 Clear sample complete flag Write to ISC bit 3 Bard, Gerstlauer, Valvano, Yerraballi