Presentation on theme: "2003-11-061 T R L I T MSC HLR SCP GMSC MSC T I SCP IN MSBTS BSC GSM HLRSCP GMSC MSC TDMA ILR L AXE TSP CPP WPP AXD EAR TMOS/CIF AN ADSL T CCN FNR TeS MS."— Presentation transcript:
T R L I T MSC HLR SCP GMSC MSC T I SCP IN MSBTS BSC GSM HLRSCP GMSC MSC TDMA ILR L AXE TSP CPP WPP AXD EAR TMOS/CIF AN ADSL T CCN FNR TeS MS G ATM Back bone AN RNC 3G UMTS GPRS SGSN GGSN Internet “ MGW ” OSS CSCF HSS AS IPMM/SIP PCU AXE 10 Minutes, AXE based nodes
AXE 10 minutes, Processors Central Processor Regional Processor Adjunct Pro,( I/O) Application Hardware Central Processor Adjunct Pro,( I/O) Soft Real Time Hard Real Time
AXE 10 Minutes, SW Maintenance Corrections/patches are introduced without disturbance New SW packages are introduced in the stand-by side, inherits data from the executive-side and are switch in with a system restart => yearly disturbance
AXE 10 Minutes, Low Level Recovery Fx Forlopp handler A ‘forlopp’ identity, FID, is tied to each resource included in a ‘transaction’, typically a a call or a command. The processing platform provides support for creation of FID and in case of an execution error, identifies all resources concerned and orders release over a standard interface.
AXE 10 Minutes, SW Recovery SW Error Low Level Recovery No Action Filter 99,8% 0,1% System Restart < 0,1%
AXE 10 Minutes, CP ’Classic‘ vs ‘Modern’ HW MIP Application SW APZ-CP OS HW ( -procesor) OS (Tru64™) APZ-VM ASA- compiler Application SWAPZ-CP OS Same HAL OS API
AXE 10 Minutes, Multi-threaded Execution Must be 101% compatible with application SW (includes fault compatibility!) The problem is not to make it work The real problem is to make an efficient implementation with limited over-head including the cost for cache coherency