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Chapter 00 Preface Introduction to VLSI Circuits and Systems 積體電路概論

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1 Chapter 00 Preface Introduction to VLSI Circuits and Systems 積體電路概論
賴秉樑 Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007

2 Goal, Grading and Textbook
Equip students with basic VLSI design capability Design and analyze digital VLSI chips using CMOS technology Understand design issues at the layout, transistor, logic and register-transfer levels An Overview of Full Custom IC Design Flow, Cell-based IC Design Flow, and FPGA Design Flow SPICE Simulation and Physical Layout Full Custom IC Design using Cadence, Hspice Simulation, and Calibre Verification Grading Homework & Project: 30% Midterm exam: 35% Final exam: 35% Textbook John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc. (全華代理), ISBN

3 Course Outline Chapter 01: An Overview of VLSI
Chapter 02: Logic Design with MOSFETs Chapter 03: Physical Structure of CMOS Integrated Circuits Chapter 04: Fabrication of CMOS Integrated Circuits (surpass) Chapter 05: Elements of Physical Design Chapter 06: Electrical Characteristics of MOSFETs Chapter 07: Electrical Analysis of CMOS Logic Gates Chapter 08: Designing High-Speed CMOS Logic Networks Chapter 09: Advanced Techniques in CMOS Logic Circuits Chapter 10: System Specifications Using Verilog HDL Chapter 11: General VLSI System Components (surpass) Chapter 12: Arithmetic Circuits in CMOS VLSI Chapter 13: Memories and Programmable Logic Chapter 14: System-Level Physical Design (surpass) Chapter 15: VLSI Clocking and System Design

4 The Integrated Circuit
1959: Jack Kilby, working at TI, invented a monolithic “integrated circuit” Components connected by hand-soldered wiresand isolated by “shaping”, PN-diodes used as resistors (U.S. Patent 3,138,743) Figure 0.1 Diagram from patent application

5 Integrated Circuits 1961: TI and Fairchild introduce the first logic ICs ($50 in quantity) 1962: RCA develops the first MOS transistor Figure 0.2 Fairchild bipolar RTL Flip-Flop Figure 0.3 RCA 16-transistor MOSFET IC

6 Computer-Aided Design
1967: Fairchild develops the “Micromosaic” IC using CAD Final Al layer of interconnect could be customized for different applications 1968: Noyce, Moore leave Fairchild, start Intel

7 RAMs 1970: Fairchild introduces 256-bit Static RAMs
1970: Intel starts selling1K-bit Dynamic RAMs Figure 0.4 Fairchild bit SRAM Figure 0.5 Intel K-bit DRAM

8 The Microprocessor 1971: Intel introduces the 4004
General purpose programmable computer instead of custom chip for Japanese calculator company Figure 0.6 Intel 4004 Microprocessor

9 Type of IC Designs IC Designs can be Analog or Digital
CMOS design methods Microprocessor/DSP Programmable Logic Fast prototyping with FPGA or CPLD chips Gate Array and Sea of Gates Design Cell-based Design Designs synthesized automatically from a high-level language description Full-custom Design Every transistor designed and laid out by hand Platform-based Design System on a chip

10 Full Custom Design Flow Silicon Ensemble Ultra / Dracula
ASIC Design Flow Cell Based Design Flow Advanced VLSI Research Center Specification System-Level Design & Sim SPW Matlab ASIC BONeS Behavior Synthesis Visual Architect Full-Custom Cell-Based FPGA MathWork RTW Full Custom Design Flow RTL-Level Sim Verilog-XL Synopsys VCS Circuit-Level Design Composer RTL Synthesis Ambit Cell Library Design-Compiler Pre-Layout Circuit-Sim Hspice Spice Model Gate-Level Sim Synopsys VCS SBTSPICE Cell Library Model Verilog-XL Physical Layout Virtuoso Physical Verification Apollo/Hercules Silicon Ensemble Ultra / Dracula Physical Verification & RC Extraction Dracula RC Extraction Star-RC Dracula Post-Layout Sim Hspice Spice Model & RC Post-Layout Sim TimeMill Star-time Star-sim SBTSPICE Tape Out Tape Out

11 System-on-Chip

12 Systematic Design Flow

13 MOS Technology Trends

14 Silicon in 2010 Die Area: 2.5 x 2.5 cm Voltage: 0.6 V
Density Access Time (Gbits/cm2) (ns) DRAM 8.5 10 DRAM (Logic) 2.5 SRAM (Cache) 0.3 1.5 Die Area: 2.5 x 2.5 cm Voltage: 0.6 V Technology: 0.07 m Density Max. Ave. Power Clock Rate (Mgates/cm2) (W/cm2) (GHz) Custom 25 54 3 Std. Cell 10 27 1.5 Gate Array 5 18 1 Single-Mask GA 2.5 12.5 0.7 FPGA 0.4 4.5 0.25

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