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Adders and Subtractors Discussion D4.1

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Adders and Subtractors Adders Carry and Overflow Subtractors Adder-Subtractor

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Half Adder CABS 0001 A 0 B 0 S 0 C 1 0 0 0 1 1 0 1 0 1 1 0 1 Dec Binary 1 1 +1 2 10

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Multiple-bit Addition 0 1 0 1 1 1 A B A 3 A 2 A 1 A 0 0 1 A 0 1 1 1 B 3 B 2 B 1 B 0 B 0 1 0 1 1 1 1 A i +B i +C i SiSi C i+1

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 SiSi

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 S i = C i 'A i 'B i + C i 'A i B i ' + C i A i 'B i ' + C i A i B i

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Full Adder S i = C i '(A i 'B i + A i B i ') + C i (A i 'B i ' + A i B i ) S i = C i '(A i B i ) + C i (A i B i )' S i = C i (A i B i ) S i = C i 'A i 'B i + C i 'A i B i ' + C i A i 'B i ' + C i A i B i

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 111 CiCi AiBiAiBi 00011110 0 1 C i+1

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i B i + C i B i + C i A i

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i B i + C i A i 'B i + C i A i B i '

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Full Adder C i+1 = A i B i + C i (A i 'B i + A i B i ') C i+1 = A i B i + C i (A i B i ) Recall: S i = C i (A i B i ) C i+1 = A i B i + C i (A i B i ) C i+1 = A i B i + C i A i 'B i + C i A i B i '

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Full Adder Half-adder S i = C i (A i B i ) C i+1 = A i B i + C i (A i B i )

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Full Adder A full adder can be made from two half adders (plus an OR gate).

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Full Adder Block Diagram

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4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0

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Full Adder Truth table CiCi AiAi BiBi SiSi C i+1 Behavior C i+1 :S i = C i + A i + B i

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Full Adder Block Diagram

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4-Bit Adder C 1 1 1 0 0:A 0 1 1 0 1 0:B 0 0 1 1 1 C4:S 1 0 1 0 0

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library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity adder4 is port( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); carry : out STD_LOGIC; S : out STD_LOGIC_VECTOR(3 downto 0) ); end adder4; architecture adder4 of adder4 is begin process(A,B) variable temp: STD_LOGIC_VECTOR(4 downto 0); begin temp := ('0' & A) + ('0' & B); S <= temp(3 downto 0); carry <= temp(4); end process; end adder4;

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4-Bit Adder

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Adders and Subtractors Adders Carry and Overflow Subtractors Adder-Subtractor

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Carry and Overflow 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 0111 C = 0 V = 0 0 0 1 0 53 +25 78 35 +19 4E Dec Hex Binary 1 001 1 0 0 Note no carry from bit 6 to bit 7 and no carry from bit 7 to C.

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Carry and Overflow 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0000 C = 0 V = 1 1 1 1 0 53 +91 144 35 +5B 90 Dec Hex Binary 1 111 0 1 1 Thinking SIGNED we added two positive numbers and got a negative result. This can’t be correct! Therefore, the OVERFLOW bit, V, is set to 1. Correct answer (144) is outside the range -128 to +127. Note carry from bit 6 to bit 7 but no carry from bit 7 to C.

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Carry and Overflow 0 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 0001 C = 1 V = 0 0 0 1 0 53 - 45 8 35 +D3 108 Dec Hex Binary 1 111 0 1 0 Thinking SIGNED we added a positive number to a negative number and got the correct positive answer. Therefore, the OVERFLOW bit, V, is cleared to 0. Correct answer (8) is inside the range -128 to +127. Ignore carry Note carry from bit 6 to bit 7 and carry from bit 7 to C.

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Carry and Overflow 1 0 0 1 1 1 1 0 1 1 0 1 0 0 1 1 1000 C = 1 V = 1 1 1 1 1 - 98 - 45 - 143 9E +D3 171 Dec Hex Binary 0 110 1 0 0 Thinking SIGNED we added two negative numbers and got a positive answer. This must be wrong! Therefore, the OVERFLOW bit, V, is set to 1. Correct answer (-143) is outside the range -128 to +127. Ignore carry Note no carry from bit 6 to bit 7 but there is a carry from bit 7 to C.

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Overflow Note that the overflow bit was set whenever we had a carry from bit 6 to bit 7, but no carry from bit 7 to C. It was also set when we had a carry from bit 7 to C, but no carry from bit 6 to bit 7. Upshot: The overflow bit is the EXCLUSIVE-OR of a carry from bit 6 to bit 7 and a carry from bit 7 to C.

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Adders and Subtractors Adders Carry and Overflow Subtractors Adder-Subtractor

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Half Subtractor CABD 0001 0 0 0 1 1 1 1 0 1 1 0 0 A 0 B 0 D 0 C 1 0 1 2 1

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Multiple-bit Subtraction 0 1 0 1 1 1 A B A 3 A 2 A 1 A 0 0 1 A 0 1 1 1 B 3 B 2 B 1 B 0 B 01 1 1 1 1 A i - B i - C i DiDi C i+1 1

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Full Subtractor 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 C i A i B i D i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 DiDi D i = C i (A i B i ) Same as S i in full adder

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Full Subtractor 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 C i A i B i D i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i 'B i + C i A i 'B i ' + C i A i B i

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Full Subtractor C i+1 = A i 'B i + C i (A i 'B i ' + A i B i ) C i+1 = A i 'B i + C i (A i B i )' Recall: D i = C i (A i B i ) C i+1 = A i 'B i + C i (A i B i )' C i+1 = A i 'B i + C i A i 'B i ' + C i A i B i

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Full Subtractor half subtractor D i = C i (A i B i ) C i+1 = A i 'B i + C i (A i B i )'

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Adders and Subtractors Adders Carry and Overflow Subtractors Adder-Subtractor

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0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 C i A i B i S i C i+1 Full Adder Reordered Full Adder 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 C i A i B i D i C i+1 Full Subtractor NOT

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Making a full subtractor from a full adder

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Adder/Subtractor E = 0: 4-bit adder E = 1: 4-bit subtractor

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4-bit Subtractor: E = 1 +1 Add A to !B (one’s complement) plus 1 That is, add A to two’s complement of B D = A - B

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