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Verilog-A: An Introduction for Compact Modelers

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1 Verilog-A: An Introduction for Compact Modelers
4/7/2017 MOS-AK/ESSDERC/ESSCIRC Workshop (Montreux 2006) Verilog-A: An Introduction for Compact Modelers Geoffrey Coram

2 Outline The Problem Modeling Languages Diode Example Guidelines
4/7/2017 Outline The Problem Modeling Languages Diode Example Guidelines Admonishments Compiler Optimizations Conclusion References (and Further Examples) Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

3 Many models, many simulators
4/7/2017 Many models, many simulators VBIC Eldo ACM Spectre USIM ADS Smash HiCUM BSIM HSIM Mextram Nanosim PSP APLAC HiSIM HSPICE HVEKV Golden Gate MM20 AMS from McAndrew, BMAS 2003 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

4 The Solution VBIC Eldo ACM Spectre USIM ADS Smash HiCUM BSIM HSIM
4/7/2017 The Solution VBIC Eldo ACM Spectre USIM ADS Smash HiCUM BSIM HSIM Modeling Interface Mextram Nanosim PSP APLAC HiSIM HSPICE HVEKV Golden Gate MM20 AMS from McAndrew, BMAS 2003 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

5 Modeling Languages Programming languages: MATLAB FORTRAN (SPICE2)
4/7/2017 Modeling Languages Programming languages: FORTRAN (SPICE2) C (SPICE3) Fast, direct access to simulator Must compute derivatives No standard interface Intimate knowledge of simulator required MATLAB Excellent for data fitting Does not run directly in any analog simulator Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

6 Behavioral Modeling Languages
4/7/2017 Behavioral Modeling Languages VHDL-AMS First analog behavioral modeling language working group (IEEE ) Painfully slow to come to fruition … Europe prefers VHDL (for digital) Runs in: AMS Designer (Cadence), DiscoveryAMS (Synopsys), ADVance MS (Mentor), Smash (Dolphin), … only AMS simulators! No clear definition of “VHDL-A” (except by R. Shi’s MCAST model compiler) Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

7 Behavioral Modeling Languages
4/7/2017 Behavioral Modeling Languages Verilog-A Verilog-AMS Pushed by Cadence, came to market earlier Verilog-A from Open Verilog International became part of Accellera Verilog-AMS IEEE 1800 authorized to develop SystemVerilog-AMS Verilog-AMS runs in the same AMS simulators as VHDL-AMS Verilog-A runs in Spectre, HSpice, ADS, Eldo… and internal simulators of semiconductor companies Clear definition of “A” Verilog-AMS LRM 2.2 was driven by the requirements for compact modeling Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

8 V-AMS LRM 2.2 Additions Highlights for compact modeling:
4/7/2017 V-AMS LRM 2.2 Additions Highlights for compact modeling: output / operating point “parameters” vdsat, id_chan also gm, cgs using new ddx() operator $simparam to access simulator quantities (gmin) $param_given paramsets – replace and extend Spice .model cards Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

9 4/7/2017 VHDL-AMS Diode -- Modified from library IEEE; use IEEE.math_real.all; use IEEE.electrical_systems.all; use IEEE.FUNDAMENTAL_CONSTANTS.all; entity diode is generic (Isat: current := 1.0e-14); -- Saturation current [Amps] port (terminal p, n : electrical); end entity diode; architecture ideal of diode is quantity v across i through p to n; constant TempC : real := 27.0; -- Ambient Temperature [Degrees] constant vt : real := PHYS_K*( TempC )/PHYS_Q; -- Thermal Voltage begin i == Isat*(limit_exp(v/vt) - 1.0); end architecture ideal; Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

10 VHDL-AMS Diode is is a keyword! TempC is a constant!
4/7/2017 VHDL-AMS Diode -- Modified from library IEEE; use IEEE.math_real.all; use IEEE.electrical_systems.all; use IEEE.FUNDAMENTAL_CONSTANTS.all; entity diode is generic (Isat: current := 1.0e-14); -- Saturation current [Amps] port (terminal p, n : electrical); end entity diode; architecture ideal of diode is quantity v across i through p to n; constant TempC : real := 27.0; -- Ambient Temperature [Degrees] constant vt : real := PHYS_K*( TempC )/PHYS_Q; -- Thermal Voltage begin i == Isat*(limit_exp(v/vt) - 1.0); end architecture ideal; is is a keyword! TempC is a constant! Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

11 Verilog-A Diode `include "disciplines.vams" module diode(a,c);
4/7/2017 Verilog-A Diode `include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) – 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

12 Verilog-A Diode `include "disciplines.vams" module diode(a,c);
4/7/2017 Verilog-A Diode `include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) – 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule thermal voltage – uses simulation temperature Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

13 Verilog-A Diode disciplines define through and across variables
4/7/2017 Verilog-A Diode disciplines define through and across variables `include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) – 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

14 Verilog-A Diode `include "disciplines.vams"
4/7/2017 Verilog-A Diode `include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) – 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule modules combine entity and architecture; replace Spice primitives Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

15 Verilog-A Diode `include "disciplines.vams"
4/7/2017 Verilog-A Diode `include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) – 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule parameters have ranges (and defaults) Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

16 Verilog-A Diode `include "disciplines.vams" module diode(a,c);
4/7/2017 Verilog-A Diode `include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) – 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule built-in function with improved convergence Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

17 Verilog-A Jump Start Looks much like C
4/7/2017 Verilog-A Jump Start Looks much like C Intuitive and easy to read and learn Start with an existing model and modify Based on through and across variables Set up is for KCL and KVL Understand the “contribution” operator I(di,si) <+ Ids; // current di to si V(d ,di) <+ I(b_rd)*rd; // voltage d to di Dynamic flows are done via ddt() I(t,b) <+ ddt(C * V(t,b)); Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

18 Best Practices Models formulated in currents I(V) and charges Q(V)
4/7/2017 Best Practices Models formulated in currents I(V) and charges Q(V) most natural for modified nodal analysis (MNA) Q(V) not C(V) to ensure conservation of charge ddt(Q(V)) != ddt(C(V) * V) != C(V) * ddt(V) No access to previous timesteps watch non-quasi-static formulations allows model to run in RF simulator Noises as current sources No discontinuities Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

19 Discontinuities Spice requires continuous derivatives
4/7/2017 Discontinuities Spice requires continuous derivatives Consider this code: if (vbs == 0.0) begin qbs = 0.0; capbs = czbs+czbssw+czbsswg; end else if (vbs < 0.0) begin qbs = … … I(b,s) <+ ddt(qbs); Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

20 Automatic derivative differs from intended value
4/7/2017 Discontinuities Resulting C code: if (vbs == 0.0) { qbs = 0.0; dqbs_dvbs = 0.0; //capbs=czbs+czbssw+czbsswg; } else if (vbs < 0.0) { qbs = … … Automatic derivative differs from intended value Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

21 Discontinuities HiSIM2 Verilog-A (beta code)
4/7/2017 Discontinuities HiSIM2 Verilog-A (beta code) Clipping in C code may affect values and derivatives differently if ( Vds <= `epsm10 ) begin Pds = 0.0 ; Psl = Ps0 ; Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

22 Compiler Optimizations
4/7/2017 Compiler Optimizations Common subexpressions id = is * (exp(vd/vtm) – 1.0); gd = is/vtm * exp(vd/vtm); Eliminating internal nodes if (rs == 0.0) V(b_res) <+ 0.0; else I(b_res) <+ V(b_res) / rs; Dependency trees replace analysis() and initial_step Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

23 analysis() Consider this code: if (analysis("tran")) begin qd = … …
4/7/2017 analysis() Consider this code: if (analysis("tran")) begin qd = … … No capacitance in: small-signal ac analysis, harmonic balance, envelope following Pseudo-transient homotopy Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

24 analysis() Consider this code: if (analysis("noise")) begin
4/7/2017 analysis() Consider this code: if (analysis("noise")) begin flicker = strongInversionNoiseEval(vds, temp); But what about PNOISE, HBNoise, …? Compiler/Simulator MUST do this optimization Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

25 Events Consider this code: @(initial_step) begin isdrain = jsat * ad;
4/7/2017 Events Consider this code: @(initial_step) begin isdrain = jsat * ad; What happens for a dc sweep? don’t want re-computing for bias sweep need re-computing for temperature sweep Even for transient, initial_step is true for every iteration at time=0 Compiler/Simulator MUST do this optimization Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

26 4/7/2017 ADMS “Magic” Names ADMS uses special block names to identify sections of code Eg PSP Verilog-A: begin : initializeModel NSUB0_i = `CLIP_LOW(NSUB0,1e20); //… Doesn’t hurt for other compilers … Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

27 Software Practices Use consistent indentation
4/7/2017 Software Practices Use consistent indentation Align code vertically on = Use meaningful names use maximum size (8) to help vertical alignment Include comments: brief description, reference documentation Physical constants are not dated and could change model results would then change define physical constants for a model Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

28 PSP Model Code // 4.2.4 Surface potential at source side
4/7/2017 PSP Model Code // Surface potential at source side Gf = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; Gf = sqrt(Gf2); xi = Gf * `invSqrt2; inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns) Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

29 PSP Model Code equation number from documentation and explanation
4/7/2017 PSP Model Code // Surface potential at source side Gf = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; Gf = sqrt(Gf2); xi = Gf * inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns) equation number from documentation and explanation Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

30 PSP Model Code alignment for readability
4/7/2017 PSP Model Code // Surface potential at source side Gf = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; Gf = sqrt(Gf2); xi = Gf * `invSqrt2; inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns) alignment for readability Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

31 PSP Model Code indentation of blocks
4/7/2017 PSP Model Code // Surface potential at source side Gf = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; Gf = sqrt(Gf2); xi = Gf * `invSqrt2; inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns) indentation of blocks Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

32 Other Model Code no reference to documentation
4/7/2017 Other Model Code //----Self Heating Effect //(implemented only on mobility)------ PD = (VDE-VS)*Id; if (SH_switch ==1) begin I(TH) <+ PD; RTHNOM = RTHNOM_298K*(1+alpha_SHE*(Tempp-TNOMK)); RTH = RTHNOM*(1+alpha_SHE*(Tempp+V(TH)-TNOMK)); I(TH) <+ - V(TH)/(RTH); I(TH) <+ - ddt(CTH*V(TH)); end else begin I(TH) <+ 0; Tratio_SH=(Tempp+V(TH)*SH_switch)/TNOMK; BEX=BEX0/pow( abs(VG-VS) +1e-1,par_SHE); KP_T=KP0*pow(Tratio_SH,BEX); no reference to documentation inconsistent indentation Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

33 Other Model Code correct indentation //----Self Heating Effect
4/7/2017 Other Model Code //----Self Heating Effect //(implemented only on mobility)------ PD = (VDE-VS)*Id; if (SH_switch ==1) begin I(TH) <+ PD; RTHNOM = RTHNOM_298K*(1+alpha_SHE*(Tempp-TNOMK)); RTH = RTHNOM*(1+alpha_SHE*(Tempp+V(TH)-TNOMK)); I(TH) <+ - V(TH)/(RTH); I(TH) <+ - ddt(CTH*V(TH)); end else begin I(TH) <+ 0; end Tratio_SH=(Tempp+V(TH)*SH_switch)/TNOMK; BEX=BEX0/pow( abs(VG-VS) +1e-1,par_SHE); KP_T=KP0*pow(Tratio_SH,BEX); correct indentation Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

34 Other Model Code cryptic comments – where is Eeff??
4/7/2017 Other Model Code // new model for mobility reduction, //linked to the charges model // !! mb 98/10/11 (r10) introduced fabs(Eeff) (jpm) // if ((qb + eta_qi*qi) > 0.0) begin E0_Q_1 = T0*(qb + eta_qi*qi); end else begin E0_Q_1 = T0*(qb + eta_qi*qi); end T0_GAMMA_1 = T0*GAMMA_sqrt_PHI; // !! mb 97/06/02 ekv v2.6 beta = KP_Weff * T0_GAMMA_1 / (Leq * E0_Q_1+1e-60); // !! mb 97/07/18 cryptic comments – where is Eeff?? Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

35 Coding Style Verilog-A can be very readable
4/7/2017 Coding Style Verilog-A can be very readable Characterization engineers and simulator people will read it Make a good impression! Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

36 4/7/2017 Conclusion Verilog-A is a powerful and easy-to-use compact modeling language Writing a good compact model still requires care and rigor Many examples now available Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

37 References Designer’s Guide http://www.designers-guide.org/
4/7/2017 References Designer’s Guide Forum Verilog-A model library (VBIC, MOS11, JFET, etc.) MCAST (Prof. CJ Richard Shi) Automatic compiler beats hand-coded C Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

38 4/7/2017 Examples Verilog-A model library at VBIC, MOS11, JFET, etc. Silvaco “public domain” models (non-commercial use) https://src.silvaco.com/ResourceCenter/en/ downloads/verilogA.jsp BSIM3, BSIM4, BJT, etc. But: watch out PSP Mextram HiCUM eb/hic_new/hic_intro.html Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)


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