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Bridging Theory in Practice Transferring Technical Knowledge to Practical Applications.

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1 Bridging Theory in Practice Transferring Technical Knowledge to Practical Applications

2 The ABCs of ESD, EOS, and SOA

3

4 Intended Audience: Electrical engineers with a knowledge of simple electrical circuits An understanding of MOSFET devices Topics Covered: What is Electrostatic Discharge (ESD) What is Electrical Over Stress (EOS) What is Safe Operating Area (SOA) Expected Time: Approximately 90 minutes The ABCs of ESD, EOS, and SOA

5 What is ESD – Where does ESD come from – MOSFET Gate susceptibility – Test Standards – Component level vs. module level tests What is EOS What is SOA The ABCs of ESD, EOS, and SOA

6 We are all familiar with a common form of electrostatic discharge (ESD): ESD is the sudden transfer of electrostatic charge between objects at different electrostatic potentials Electrostatic Discharge (ESD) Shaggy Carpet

7 Where Does ESD Come From Triboelectric Charging – Mechanical Contact and Separation – Walking on carpet Ionic Charging – Not properly balanced Air Ionizer can charge an object (instead of intended operation to neutralize/balance charge) –Charged object comes into contact with a grounded object (such as machine pick-up probe or grounded human operator) –This is example of charged device model (CDM) eventmore to come!!! Direct Charging – Mobile Charge Transfer – Plugging in a cable (e.g. USB to PC)

8 Where Does ESD Come From? Which levels can occur? – Below 3-4kV you see, hear or feel nothing! – Just above 4kV, air-gap-sparks can occur – 1mm == 1kV (5mm spark ~ 5kV) Why does a 2kV protected device survive the real world? – You are charged relatively to earth, not to pin7 – You do not have 4kV between your thumb and your index finger

9 Where Does ESD Come From? Influence of Air Humidity – Higher relative air humidity does cause a moisture film on surfaces – Charge is more distributed, lower voltages thus occur – But dry air does not have a higher inherent resistance 15%35% office room (winter) without air humidity regulation anti-static wool synthetic 1005102030405060708090 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ESD Voltage (kV) % Relative Air Humidity

10 p-type SiO 2 nn MOSFET Gate Susceptibility SourceDrainGate Insulating SiO 2 Gate Often, the source is grounded

11 p-type SiO 2 nn Charge Is Applied to the MOSFET Gate SourceDrainGate But, the charge is stuck on gate due to insulating SiO 2 Cgs

12 A Quick Review of Voltage and Capacitance Voltage Think of voltage as an amount of possible electrical work A high voltage means additional electrical work is possible If the voltage is improperly directed or used, unintended (and potentially harmful) work will be performed Capacitance Capacitors are one way of storing electrical work/energy If a capacitor can store a large amount of electrical work, it has a large capacitance If a capacitor can store only a small amount of electrical work, it has a small capacitance Battery +12VGround

13 Variables and Constants: C Capacitance Permittivity of Silicon Dioxide Q ChargeA Area of Capacitor Plates V Voltaged Distance Between Conductors Two Basic Equations: Rearranging yields: A Quick Review of Voltage and Capacitance 0ox A C d

14 Quick Review Summary: is a constant for a given material (SiO 2 ) As the charge (Q) on the capacitor increases - the voltage across the capacitor increases….

15 p-type SiO 2 nn SourceDrainGate p-type SiO 2 nn Gate Charge Induces a Gate Voltage SourceDrainGate POP

16 p-type SiO 2 nn SourceDrainGate p-type SiO 2 nn SourceDrainGate Induced Gate Voltage Creates a Hole in the SiO 2 Allowable E-field within SiO 2 exceeded

17 p-type SiO 2 nn SourceDrainGate p-type SiO 2 nn SourceDrainGate Induced Gate Voltage Creates a Hole in the SiO 2 Gate-Source Short MOSFET cannot turn on

18 Gate susceptibility summary: As the charge (Q) on the capacitor increases - the voltage across the capacitor increases…. If the transistor decreases in size - the thickness of the SiO 2 gate (d) decreases - but, the area (A) of the gate decreases faster - For the same amount of charge, the voltage across the capacitor is higher for a smaller transistor More advanced technologies may require additional ESD precautions

19 Induced Voltage for 3 m and 1.2 m CMOS Processes 3 m Process (Minimum Size Transistor) – t ox = 400 Å = 4x10 -8 m – L= 3 m – W= 3 m – Q= 1.16x10 -11 C 1.2 m Process (Minimum Size Transistor) – t ox = 200 Å = 2x10 -8 m – L= 1.2 m – W= 1.2 m – Q= 1.16x10 -11 C Note:

20 ESD Standards & Test: Overview ESD Standards & Tests should simulate real world events as realistic as possible There is no single/one size fits all ESD Test available Different handling/mounting conditions have resulted in different ESD tests – e.g. car-manufacturers follow different ESD standards than component- suppliers: both are talking about ESD but not about the same applied ESD- standards Be careful to know complete standard definition –ESD 2kV, 2kV HBM,… does not mean much: The Standard is missing e.g JEDEC22-A114; MIL-STD-883, Method 3015.7, ……(more complete)

21 ESD Standards & Tests: Overview A Standard consists of … – … a used MODEL (HBM, MM, …) Standard=+ModelValuesProcedure+ Therefore Standards can differ in each subset, in the –MODEL –VALUES –TEST PROCEDURE HBM 2kV is not specific – 2kV JEDEC22-A114 is better defined –… VALUES for the elements used in the model (R=1500 Ohm, C=100pF) –… plus TEST PROCEDURE: how to apply the standard (e.g. 3 pulses)

22 ESD Models: Human Body Model Human Body Model (HBM) consists of a Capacitor and a series Resistor Values are defined in the specific standard – Commonly used: C =100pf, R=1500 Ohm (JEDEC, Mil, etc.) Test Procedure is defined in the specific standard – Commonly used: 1 to 3 pulses, both polarities, 3 devices/voltage level HBM Standards (R=1500 Ohm, C=100 pF) JEDEC JESD 22-A114 [2] Military Standard Mil.883 3015.7 [3] ANSI/ESD STM5.1 [4] IEC 61340-3-1 Human ESD Model (R=2000 Ohm, C=150 pF – 330 pF) ISO/TR 10605 [5] Human Body Representative (R=330 Ohm, C=150 pF) IEC 61000-4-2 [6] Commonly used for component tests

23 ESD Models: Human Body Model Waveform HBM Jedec22-A1114 Waveform: – 10ns rise time typically (short) 2-10ns are allowed – Peak current: Rule of Thumb: – 1kV = 2/3 Ampere V ESD (V)I peak - I peak+10% (A) 10000.67 – 0.74 20001.33 – 1.45 40002.67 – 2.93 1kV ][1500 Vesd Ipeak

24 ESD Models: Machine Model Machine Model (MM) consists of a Capacitor and no series Resistor Values are defined in the specific standard – Commonly used: C =200pF, Test Procedure is defined in the specific standard – Commonly used: 1 to 3 pulses, both polarities, 3 devices/level MM Standards (C=200 pf) JEDEC JESD 22-A115 [11] ANSI/ESD STM5.2 Philips Standard (C=200 pF, R=10-25 Ohm, L=0.75-2.5µH) Standard?? Some definitions use MM standard with a 25 Ohm series resistor, which at least doubles the achievable ESD Level!

25 ESD Models: Machine Model MM stress is similar to HBM – Oscillations due to setup parasitics MM and HBM failure modes are similar Less reproducible than HBM V ESD (kV)I peak - I peak+30% (A) 0.11.5 - 2.0 0.22.8 - 3.8 0.45.8 - 8.0 Source: T. Brodbeck; Models.pdf

26 Charged Device Model Test Models an ESD event which occurs when a device acquires electrostatic charge and then touches a grounded object Device placed in dead-bug position Device discharges through ground probe Field Plate Dielectric High Voltage Source

27 CDM Waveform: Highly dependent on die size and package capacitance 500V with 4pF verification module t r <400psec / I p1 ~4.5A / I p2 <0.5I p1 / I p3 <0.25I p1 Source: AEC-Q100-011B

28 AEC-Q100 A utomotive E lectronic C ouncil (AEC) Stress Test Qualification 100 : AEC Q100 – xxx AEC Q100 validated suppliers have to fulfill the ESD regarding qualification described in it –AEC Q100-002: HBM (JEDEC) 2000V OR AEC Q100-003: MM (JEDEC) 200V AND –AEC Q100-011: CDM (JEDEC) Corner Pins 750V / Non-corner pins 500V AEC is not a single standard but a collection of requirements for automotive suppliers

29 Component vs. Module level tests ESD (pulses) testing originates from a subset of the wide field of EMC ( E lectro m agnetic C ompatibility, EMI … I mmunity) Due to the importance in the Semiconductor Industry, ESD testing has evolved into its own field of specialization (Powered) Systems(Unpowered) Components The ESD/EMC world in general can be divided into two main- fields:

30 Goal: UNDISTURBED functionality during and after ESD stress under powered / functional conditions ESD Standards & Tests: System vs. Component ESD is a part of EMC qualification Different behavior criteria in response to ESD on system level exists (class A to D) Goal: UNDESTROYED components after ESD stress: All specification-parameters should stay within its limits ESD is a part of product qualification Pass/fail criteria All pin combinations can occur and are tested Relative measure of robustness during handling/manufacturing Just dedicated pin combinations feasible I/O vs. GND The reference/enemy is always earth potential Relative measure of robustness of end product during operation

31 ESD Test methods (Models) System vs. Component Component Level Module/System Level Human Body Model (HBM) 100pF / 1500 JEDEC-Norm JESD22-A114-B (MIL-STD883D, method 3015) Machine Model (MM) 200pF / 0 JEDEC-Norm JESD22-A115-A (correlates to HBM) Charged Device Model (CDM) Package pF / 0 JEDEC-Norm JESD22-C101-A Human Body Model (HBM) 150pF / 330 EN 61000-4-2 (so called GUN Test) Human Body Model (HBM) 150pF / 2000 ISO 10605 Human Body Model (HBM) 330pF / 2000 ISO 10605

32 ESD Models: Human Body Model Component Test A Pin-to-Pin ESD Tester (like HBM, MM Testers) consists of the HV source and the model with its values, connected to two Terminals The Terminals are not changed for polarity reversal … The capacitance is charged one time positively and one time negatively Tester-Ground along with parasitics stay constant HV Terminal A Terminal B

33 ESD Models: Human Body Model Component Test 2 different Pin-Combination-Types are tested – Supply-Pin-Tests All Pins (individually one at a time) at Terminal A vs. Supply-X at Terminal B Repeat for Supply-Y, Supply-Z, etc. at Terminal B – Non-Supply-Pin-Test All Non-Supplies (individually one at a time) at Terminal A vs. all other non-supplies together at Terminal B Repeat for each non-supply at Terminal A 1 positive and 1 negative pulse for each pin-combination Step-Stress, 500V, 1kV, 2kV and 4kV should be used; different levels and steps can be defined – A new set of 3 devices per level is used ESD Product Qualification Test @ IFX according to JEDEC EIA/JESD 22-A114-B [2] described in IFX Procedure [1]

34 ESD Supply-Pin Test: HBM ESD Each pin vs. Supply-1 (GND) ESD Test P1.1 – All pins vs. Supply 1 (in this case GND) – In this case: 10 different combinations 1+ and 1- pulse for each combination 20 pulses for each voltage step

35 ESD Supply-Pin Test: HBM ESD Each pin vs. Supply-2 (VBB) ESD Test P1.2 – All pins vs. Supply 2 (in this case VBB) – Then subsequently All pins vs. Supply 3 (Vdd) – In this case: 11 different combinations 1+ and 1- pulse for each combination 22 pulses for each voltage step

36 ESD Non-Supply-Pin Test: HBM ESD Each non- supply vs all other non-supply ESD Test P2 – Each non-supply vs. All other non-supply – One non-supply at a time on Terminal A – All other non-supplies at Terminal B – In this case: 8 different combinations 1+ and 1- pulse for each combination 16 pulses for each voltage step

37 ESD Standards & Test: System-Level Test Direct Discharge: Test points of normal accessibility. – The Reference-Pin at System-Level test is Earth and not a part of the DUT Indirect Discharge into couple plate: Test for radiated disturbance immunity

38 HBM: System Level Tests applied to components?? Some Customers ask for system- level test at component level – Component is not powered – Only pins which are accessible to the outside world are tested – Reference pin(s) are the component ground pin(s) – Pass/Fail according to Component test-program – ESD current is 5x higher at a dedicated voltage level compared to component ESD tests ESD @ 2kV Red: IEC (GUN) Blue: JEDEC HBM

39 Pulse Charge Comparison Discharge generated Pulses (RC) ApplicationStandard/Pulse Vma x [V] Duratio n (10- 90%)# of Pulses Ri [Ohm] C [pF ] Ipeak [A]Charge Charge relatively to HBM, JESD22- 114 Component "HBM" JESD 22-1148000150ns115001005.3800nC1 System "GUN" IEC 61000-4- 28000120ns10330150331.2µC1.5 System/Vehic le ISO/TR 10605 inside80001µs32000330302.64µC3.3 System/Vehic le ISO/TR 10605 outside8000360ns32000150301.2µC1.5 Voltage generated Pulses Vehicle ISO 7637: 1-1002ms500010- 20mC25x10^3 Vehicle ISO 7637: 210050µs500010- 0.5nC 6.25x10^- 4 Vehicle ISO 7637: 3a150100ns 1h (3.6x10^6)50-3300nC0.375 Vehicle ISO 7637: 3b150100ns 1h (3.6x10^6)50-2200nC0.25 Vehicle ISO 7637: 587 40- 400ms1-102-431.7C2.13x10^6 Additional Discharge generated Pulses (C) Component "MM" JESD22-11540016MHz1- >80.8nC1x10^-3 Component "CDM" JESD22-1017500.8ns11 8.5- 17-- HBM 8kV is normalized to 1

40 HBM ESD Gate Shorted to Source Very small damage area due to low energy of ESD pulses, normally cannot be seen with naked eye

41 Gate contact metal Gate PolysiliconSource contact metal HBM ESD Gate Shorted to Source This device had a G-S short and you can see the burn mark is right at the boundary region of gate poly and source metal which is common since this is the area of highest E field strength

42 Can ESD Sensitive Devices in an Automobile Be Protected? Electrostatic discharge sensitive components can be protected in an automobile Installation of spark gap topologies Establishing a predictable charge well topology such as capacitors

43 Decrease ESD Sensitivity with a Predictable Charge Well Topology Recall our earlier equation: Place a capacitor across the device/pin to be protected The additional external capacitor sheds the electrostatic discharge energy, reducing the voltage at the pins of the semiconductor device

44 Decrease ESD Sensitivity with a Predictable Charge Well Topology For most robust design, the voltage at this point should be lowered to be less than internal ESD structure breakdown voltage so all current/energy is shed thru external capacitor. Please note that there is no resistor between C_prot and IC so high current/energy can flow into IC if internal ESD structure breaks down and begins to conduct current IC Protected Pin C protection ESD generator ESD current/charge

45 Decrease ESD Sensitivity with a Predictable Charge Well Topology System level/gun tests ESD voltages may need to be 15,000V (direct contact) – Gun tests uses 330pf for source capacitor For automotive technologies having ESD structures with 40- 45V breakdown is common C _prot = (C _gun / V br_ESD ) * V _gun = (330pF / 45V) * 15kV = 110nF

46 Typical internal IC ESD Protection Circuits Ground Referenced ProtectionV Supply Referenced Protection External Pin Protected Circuit External Pin Protected Circuit V Supply IC

47 ESD Summary Electrostatic discharge occurs when excessive static charge on an object builds up to a very high voltage (thousands of volts) and causes device damage during contact and subsequent discharge (current flow) with another object MOS devices with insulating SiO 2 gates are especially susceptible to ESD damage Different test standards have evolved for component level and system level tests and confusion can result if these standards are not understood and clarified in reports and communication The very fast (HBM=nsecs / CDM=psecs) ESD pulses have low energy and result in VERY small physical damage signatures

48 What is ESD – Where does ESD come from – MOSFET Gate susceptibility – Test Standards – Component level vs. module level tests What is EOS What is SOA The ABCs of ESD, EOS, and SOA

49 What is Electrical Over Stress (EOS)? Electrical Over Stress is exactly what it says…. A device is electrically stressed over its specified limits in terms of voltage, current, and/or power/energy Unlike ESD events, EOS is the result of "long" duration stress events (millisecond duration or longer) – Excessive energy from turning off inductive loads – Load Dump – Extended operation at junction temperatures > 150degC – Repetitive excessive thermal cycling – Excessive/extended EMC exposure, etc. EOS often results in large scorch marks, discoloration of metal, melted metallization and/or bond wires, and massive destruction of the semiconductor component

50 What is Electrical Over Stress (EOS)? Failures from EOS can result in the following: – Hard failure: failure is immediate and results in a complete non-operational device – Soft failure: EOS results in a marginal failure or a shift in parametric performance of the device – Latent failure: At first the EOS results in a non-catastrophic damage but after a period of time further degradation occurs resulting in a hard or soft failure

51 EOS: Thermal Lifetime Curve Device temperature Lifetime 1 h 10 h 100 h 1 000 h 10 000 h 0.1 h 150°C 200°C270°C Spec valid, full lifetime, full function Spec restricted, reduced lifetime, limited functionality No spec, no permanent damage, highly reduced lifetime, no function guaranteed Lifetime curve for device worst case parameters Over- temperature shutdown Point of accelerated device qualification Device destruction, irreversible damage, permanent out of control 220°C 260°C Soldering 170°C 270°C Irreversible damage app. 350°C 350°C

52 What indicates EOS? What indicates EOS? What is Electrical Over Stress (EOS)? Degradation/recrystalisation of metal (400ºC) ---also repetitive fast transients<100 ºC Scorched/Melted metal (650ºC) Melted silicon (1200ºC)

53 EOS: Failure signature from excessive load dump Scorched/melted metal

54 EOS Failure Signatures---Generalities Visualization of single- and repetitive pulse events : number of cycles max. Chip temperature melting point in thermal hot spot repetitive mode single mode 1 (e.g.) 10 2 10 6 This isnt a completely black & white effect, but there can be a significant difference in single- and repetitive pulse failure signatures

55 I_ramp(10A/11.8ms) E=2.14 Joules No metal degradation near bond EOS at the hot spot Example – Inductive clamp single pulse I DS(start) =10A, t=11.8 ms, T=25°C, V bb = 12V Failure signature (10A): - No metal degradation - Scorch in DMOS field - NO bond fuse EOS: Failure signature from excessive inductive turn-off energy

56 EOS: Failure signature from repetitive thermal cycling combined with high current Severely degraded recrystalized metal

57 *Assumes T J < 150C, T Leads < 85C, T Wire < 220C, and Wire Length<3mm A common failure for electrical over stresses is MELTED METALLIZATION AND/OR BOND WIRES Electrical Over Stress (EOS) Gold Wire DC Ratings*Aluminum Wire DC Ratings* 25 m 1A 50 m 2.5A 50 m 2A 125 m 8A 350 m 40A

58 How to Electrically Over Stress Components Put components in/out of sockets while power already applied (hot plug) Applying electrical signals which exceeds a components ratings Apply an input signal to a device before applying supply voltage and/or ground Apply an input signal to a device output Use an inexpensive power supply (supply overshoot) Provide insufficient noise filtering on the boards input line(s) Use a poor ground with high resistance and inductance

59 EOS Summary Electrical over stress refers to a condition when a device is electrically stressed over its specified limits EOS often catastrophically damages devices by degrading or melting of metallization and bond wires Operation of devices within the specified Safe Operating Area will eliminate electrical over stress damage

60 What is ESD – Where does ESD come from – MOSFET Gate susceptibility – Test Standards – Component level vs. module level tests What is EOS What is SOA The ABCs of ESD, EOS, and SOA

61 Safe Operating Area (SOA) The safe operating area is a set of conditions specified for a certain device Within the safe operating area, the semiconductor component is specified to operate as expected By definition, no electrical over stress occurs within the specified safe operating area

62 SOA Graph for MOS Transistor I D, Drain Current 0.1A 1A 10A 100A V DS, Drain-Source Voltage 1V 10V100V1000V DC 1ms 200 s 50 s 15 s 4 s Pulse Width R dson =V DS /I D Single pulse, T case = 25C, T junction < 125C

63 SOA Graph for Linear Voltage Regulator V OUT = 5V, T junction < 150C I OUT, Output Current 0A 50mA 100mA 150mA V IN, Input Voltage 10V 15V20V25V T a = 125C T a = 85C T a = 25C Soldered to board with 3cm 2 copper heatsink

64 The ABCs of ESD, EOS, and SOA

65 Thank you! www.btipnow.com


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