Download presentation

Presentation is loading. Please wait.

1
**Types of BJT Biasing Circuits**

By G.Kavitha ECE Dept Paavai Engineering College

2
**Biasing Circuits of the BJT**

Normally, three types of circuits are used to establish dc biasing in a BJT, these are; (a) Fixed bias circuit (b) Collector-to-Base Bias Circuit (c) Voltage-Divider with Self-Bias Circuit (or) Self-Bias (or) Emitter Bias (or) Emitter-Stabilized Bias Circuit While designing the all four types of biasing circuits of BJT it is aimed to obtain Q-point parameters (IBQ, ICQ, VCEQ)

3
Fixed Bias

4
**The Base-Emitter Loop From Kirchhoff’s voltage law:**

+VCC – IBRB – VBE = 0 Solving for base current:

5
**Collector-Emitter Loop**

Collector current: From Kirchhoff’s voltage law:

6
Saturation When the transistor is operating in saturation, current through the transistor is at its maximum possible value.

7
**The end points of the load line are: ICsat**

Load Line Analysis The end points of the load line are: ICsat IC = VCC / RC VCE = 0 V VCEcutoff VCE = VCC IC = 0 mA The Q-point is the operating point: where the value of RB sets the value of IB that sets the values of VCE and IC

8
Collector to Base Bias

9
**Base-Emitter Loop From Kirchhoff’s voltage law: Where IB << IC:**

Knowing IC = IB and IE IC, the loop equation becomes: Solving for IB:

10
**Collector-Emitter Loop**

From Kirchhoff’s voltage law: Since IC IC and IC = IB: Solving for VCE:

11
**Voltage Divider Bias (or) Self Bias**

12
**Approximate Analysis Where IB << I1 and I1 I2 :**

Where bRE > 10R2: From Kirchhoff’s voltage law:

13
**Voltage Divider Bias Analysis**

Transistor Saturation Level Load Line Analysis Cutoff: Saturation:

14
**Emitter-Stabilized Bias Circuit**

15
**Base-Emitter Loop From Kirchhoff’s voltage law: Since IE = (b + 1)IB:**

Solving for IB:

16
**Collector-Emitter Loop**

From Kirchhoff’s voltage law: Since IE IC: Also:

17
**Improved Biased Stability**

Stability refers to a circuit condition in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor Beta () values. Adding RE to the emitter improves the stability of a transistor.

18
**Saturation Level The endpoints can be determined from the load line.**

VCEcutoff: ICsat:

19
**Emitter-Stabilized Bias Circuit**

20
**Base-Emitter Loop From Kirchhoff’s voltage law: Where IB << IC:**

Knowing IC = IB and IE IC, the loop equation becomes: Solving for IB:

21
**Collector-Emitter Loop**

From Kirchhoff’s voltage law: Since IC IC and IC = IB: Solving for VCE:

22
**Base-Emitter Bias Analysis**

Transistor Saturation Level Load Line Analysis Cutoff: Saturation:

23
THANK YOU

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google