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Microprogramming A Case Study. ITSIAC n Accumulator register, ACC, for arithmetic operations. n Instruction has Operation code and storage address, A.

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Presentation on theme: "Microprogramming A Case Study. ITSIAC n Accumulator register, ACC, for arithmetic operations. n Instruction has Operation code and storage address, A."— Presentation transcript:

1 Microprogramming A Case Study

2 ITSIAC n Accumulator register, ACC, for arithmetic operations. n Instruction has Operation code and storage address, A. n (A) means "the contents of location A" n The CPU contains an Arithmetic and Logic Unit, ALU

3 Machine Language instruction set InstructionExplanation ADDACC ACC + (A) SUBACC ACC - (A) LOADACC (A) STORE(A) (ACC) BRANCHBRANCH to A COND BRANCHif ACC = 0 BRANCH to A

4 Registers n CSIAR(Control Storage Instruction Address Register) points to the next microinstruction to be executed. n MIR(Microinstruction Register): contains the current microinstruction being executed. n PSIAR(Primary Storage Instruction Address Register) primary storage address of the next machine language instruction to be interpreted. n SAR(Storage Address Register) the address of the location in primary storage being accessed. n SDR(Storage Data Register) holds the data n TMPR(Temporary Register) the address portion of the machine instruction in the SDR so that it can be placed in the SAR

5 Micro Operations Register transfers (REG is ACC, PSIAR, or TMPR): SDR <-- REG REG <-- SDR SAR <-- REG Primary storage operations: READ WRITE Sequencing operations: CSIAR <-- CSIAR + 1 CSIAR <-- decoded SDR CSIAR <-- constant SKIP(add 2 to CSIAR if ACC = 0; else add 1) Operations involving the accumulator: ACC <-- ACC + REG ACC <-- ACC - REG ACC <-- REG REG <-- ACC ACC <-- REG + 1

6 MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

7 76 0 MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

8 MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

9 MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

10 MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

11 10 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

12 10 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

13 10 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

14 10 50 (ACC) 76 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

15 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC

16 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC 5080

17 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC 5080

18 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC 5080

19 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC 5080

20 50 (ACC) MIR SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR READ TMPR <-- SDR ACC <-- ACC + TMPR CSIAR <-- 0 TMPR <-- ACC ACC <-- PSIAR Control Storage Primary Storage (ADD 50) 5010 CSIAR PSIAR SDR ADD Fetch TMPR SAR ACC 5080


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