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Hardware Verification in Ukraine – Hard Work Ahead Presenter: Gennady Serdyuk.

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Presentation on theme: "Hardware Verification in Ukraine – Hard Work Ahead Presenter: Gennady Serdyuk."— Presentation transcript:

1 Hardware Verification in Ukraine – Hard Work Ahead Presenter: Gennady Serdyuk

2 October 26, 2006(c) Desna Systems, 20062 Agenda Terminology Hardware (HW) design and verification flows HW verification challenge HW verification details Possibilities, obstacles, reality, and the road map of the development of HW verification in Ukraine Conclusions

3 October 26, 2006(c) Desna Systems, 20063 Verification Terminology Model is an abstraction or approximation of a logic design and its behaviour. Test is an execution of a series of trials to determine if its behaviour conforms its specification. –Testing is a process of writing and executing tests. Verification is a process of demonstrating the intent of a design is preserved in its implementation. –Functional verification is the verification of design models. Coverage is a measure of verification completeness. –Functional coverage is a coverage of metrics derived from a functional or design specification. Assertion is an expression that states a safety (invariant) or liveness (eventuality) property. –Assertion coverage is a fraction of passed and failed design model assertions executed during verification.

4 October 26, 2006(c) Desna Systems, 20064 Design and Verification Flows Gate Netlist Architecture/HLM RTL Specification Layout Does it meet the spec? Does it implement the architecture? Are they equivalent? Verification Flow Design Flow

5 October 26, 2006(c) Desna Systems, 20065 Hardware Verification Challenge Complexity –Verifying a 10+ Million gates system-on-a-chip (SoC) design is a long and sophisticated task The chance of getting a non-functional chip is high –70% of ASIC designs need one or more re-spins –a 90 nm re-spin costs over $1M Verification quality must be kept under control without jeopardizing the project schedule –Cadence reports that its customers spend up to 75% of their time in verification –Verification is a time consuming process, but time is money!

6 October 26, 2006(c) Desna Systems, 20066 Hardware Verification Challenge (Cont.) Verification Gap - Verification at multiple model abstraction levels (HLM, RTL, Gates, HW prototype, Silicon ASIC) require specific sets of verification tools and techniques

7 October 26, 2006(c) Desna Systems, 20067 Practical Verification Axioms Verification cannot be biased –Trust but Verify Ronald Reagan There is no design without bugs Verification is hard Verification is expensive Verification is never done If the device is not verified, it does not work

8 October 26, 2006(c) Desna Systems, 20068 Economics of Verification Flaws detected later in the design cycle are almost invariably very expensive in terms of increased costs, lost sales, and abandoned projects. –The least initial deviation from the truth is multiplied later a thousandfold Aristotle –Each delay in detection and correction of a design problem makes it an order of magnitude more to fix. Maxfield, Clive, and Goyal, EDA: Where Electronics Begins, TechBites Interactive, 2001. Example of a bug cost at different design stages: –HLM: $10 –RTL: $100 –Gates: $1K –HW prototype: $10K –Silicon: $100K (metal fix) up to $1M (re-spin)

9 October 26, 2006(c) Desna Systems, 20069 Philosophy of Verification Humans are not machines; we are prone to mistakes –All human actions have one or more of these seven causes: chance, nature, compulsions, habit, reason, passion, desire Aristotle Though a verification engineer works in a social environment with its own rules and code of behaviour, he/she must apply his/her reason in order to prove the truth –Verification motto: "Sapere aude" lat. (Dare to know) Immanuel Kant, What is Enlightenment?, 1784 Verification is an exploration process where the design specification is a primary source of knowledge, the DUV or its model is an object, and the verification engineer is a subject

10 October 26, 2006(c) Desna Systems, 200610 Verification using Simulation Specification is a description of the design in English Design model is an interpretation of the spec described in a computer executable language (C++/SystemC, Verilog, VHDL) Verification mill: testbench, verification infrastructure, checkers, predictors, coverage data, tests, etc. Specification Verification Mill Design Model Compare? Fail Pass

11 October 26, 2006(c) Desna Systems, 200611 Hardware Verification Closure Mosaic Code Assertions Code Coverage Formal Checks Specification Coverage Regression Testing Bug Rate Analysis and Statistics Functional Coverage

12 October 26, 2006(c) Desna Systems, 200612 Verification Languages and Tools Simulators –OSCI SystemC (license free) –Cadence Verilog/VHDL NcSim (very expensive licenses) –Synopsys Verilog VCS (very expensive licenses) –Mentor ModelSim (expensive licenses) –Aldec Verilog/VHDL Riviera (moderately expensive licenses) Verification languages –C++ in combination with SystemC (license free) –SystemVerilog (requires Verilog license) –SpecMan e (Cadence support, no clear roadmap) –Vera (practically in the end-of-life state, Vera engine is moved to Synopsys's VCS SystemVerilog simulator) Assertion languages –PSL (Property Specification Language) –SVA (SystemVerilog assertions) –Verilog OVL (Open Verification Library)

13 October 26, 2006(c) Desna Systems, 200613 Why Verification in Ukraine? During the Soviet Union era, Ukraine used to have a number of well-known fabrication testing and design for testability research groups and schools India and China are getting more and more expensive to outsource verification projects. Competition for highly qualified engineers is fierce. There are cultural issues. Ukraine has a better quality/labour_cost ratio Based on the experience of a number of US companies, Ukrainian engineers are very competitive, critical minded, always ask the question Why?, do not take things for granted, and go beyond the formal scope of work. Almost every engineer knows C++ and familiar with the principals of object oriented programming

14 October 26, 2006(c) Desna Systems, 200614 Obstacles to Outsourcing Verification Projects to Ukraine Political situation is confusing for any foreign observer Tax law and IP protection legislation are not clear Hardware verification does not have enough attention at the Universities There is not enough experienced verification engineers Ukrainian outsourcing companies face a so-called credit history dilemma HDL simulator licenses are expensive

15 October 26, 2006(c) Desna Systems, 200615 State of the Art of Verification in Ukraine Universities actively involved in HW design and verification: –Donetsk Technical University, Hard Club ( –Kharkov National University of Radio Electronics, Design Automation Department –Cherkasy State Technological University Ukrainian commercial verification companies: –East-West Design & Test Ltd. (, Kharkov –Verixiom (http://, Kiev –verious small design houses with some level of verification Conferences and Workshops –IEEE East-West Design and Test International Conference organized by Kharkov National University of Radioelectronics and Tallinn University of Technology. –Ukrainian Outsourcing Forum (

16 October 26, 2006(c) Desna Systems, 200616 Road Map for Verification Development Learn, learn, and learn –need verification courses at the Universities and commercial companies –need more publicity and information –University verification labs in collaboration with commercial companies –How about Ukrainian Hardware Design and Verification Forum? –It is feasible to involve Synopsys and Cadence in setting up their R&D centres in Ukraine. Good examples are Moscow, Russia, (Cadence, Synopsys) and Erevan, Armenia, (Synopsys) Use open source verification tools –SystemC simulator and libraries ( SystemC 2.0 simulator SystemC verification library SystemC transaction level modeling (TLM) library –Productivity tools ( Verilator: a translator from Verilog into a C++/SystemC cycle-accurate model SystemPerl: productivity tool for SystemC users Verilog productivity improvement macros –Icarus Verilog Simulator (

17 October 26, 2006(c) Desna Systems, 200617 Conclusions The continuing trend of outsourcing verification services opens new opportunities for Ukraine The area of hardware design and verification did not gain enough commercial ground in Ukraine Ukraine posses all necessary intellectual prerequisites to become a leading outsourcing country in hardware design and verification On one hand Ukrainian companies want to start verification, but on the other hand they cannot find qualified specialists. Financial support and investments can help a great deal. The main concern of foreign companies is trust. Trust means experience, experience means successful projects, projects mean trust. How can this vicious circle be broken?

18 October 26, 2006(c) Desna Systems, 200618 Contacts Author can be contacted:

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