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Non-synthesizability in Verilog Presented by Pradip Mukhopadhyay ISL-MOD3(E)PR3
©Interra Systems 2 Sub-module Description Schedule: –Presentation (PR1-PR4): 4 sessions –Lab: 5 sessions Objective: –Make the SpecToLayout trainees aware about the non- synthesizable aspects of Verilog Aim: –Enable SpecToLayout trainees to write proper and efficient Verilog codes, eliminating those elements that hinder synthesis
©Interra Systems 3 Contents Introduction Non-synthesizable Constructs Non-synthesizable Behavior Modeling Potential RTL-Gate Simulation Mismatch Summary Reference
©Interra Systems 4 Introduction Todays session covers: Non-synthesizable constructs and modeling styles in Verilog Styles causing simulation-synthesis mismatch
©Interra Systems 5 Non-synthesizable Constructs Initial block –Used only in test benches Events –Make more sense for syncing test bench components Datatypes –Real, Time, and RealTime are not supported for synthesis Force & Release –Force and release of data types are not supported Assign and deassign –Assign and deassign of reg data types are not supported –Assign on wire data type is supported
©Interra Systems 6 Fork join Preferable to use non-blocking assignments instead Primitives Only gate level primitives are supported Table Limited support for UDPs Delays Used for simulation purpose System task/function Limited usability in synthesis (e.g. $signed) Generally simulation specific Non-synthesizable Constructs (Contd.)
©Interra Systems 7 Non-synthesizable Behavioral Modeling Mixing of edge & level in the always sensitivity list Containing loops, where the number of iterations are not 'deterministic' during the processing of the loop Having multiple clocks in same always 'else' path of a synchronous assignment Consisting of storage specification within a subprogram – function/task Mixing of blocking and non-blocking assignments on the same variable Containing part select where both bounds are 'unknown'
©Interra Systems 8 Any improper asynchronous style of modeling other than always @ (edge s1 or edge s2 or..... edge sn) if (s1) else if (s2).............. else if (sn -1)...... else sync block Non-synthesizable Behavioral Modeling (Contd.)
©Interra Systems 9 Potential RTL-Gate Sim Mismatch Incomplete sensitivity list Delay specifications in assignments or anywhere applicable Run time out of range Array[0:15] Array[i]; where 'i' is integer (32 bit) Read before write of wire/reg Multiply driven nets (simulation output leads to 'unknown')
©Interra Systems 10 Summary Today we have covered: Non-synthesizable construct Non-synthesizable styles Places for potential simulation-synthesis mismatch
©Interra Systems 11 Reference Verilog LRM from Interra Library /software/Documents/verilog/verilog.pdf
©Interra Systems 12 Thank You
©Interra Systems 13 Copyright © 2006 Interra Systems India Pvt. Ltd. Presentation ID: ISL-MOD3(E)PR3 Author: Pradip Mukhopadhyay Reviewers: Pradip Mukhopadhyay, Reena Misra, and Partha Pratim Das Version: 1.0 Release date:
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