Presentation is loading. Please wait.

Presentation is loading. Please wait.

Roy Lee Advisor: Lei He October 26, 2011 1 SEU Mitigation for FPGA-based Systems.

Similar presentations


Presentation on theme: "Roy Lee Advisor: Lei He October 26, 2011 1 SEU Mitigation for FPGA-based Systems."— Presentation transcript:

1 Roy Lee Advisor: Lei He October 26, SEU Mitigation for FPGA-based Systems

2 Outline Introduction In-Place Decomposition (IPD) In-Place LUT Polarity Inversion (IPV) Experimental Results Conclusions & Future Works

3 Robustness in FPGAs FPGAs are extensively used not only for prototyping but also in a wide range of applications such as internet networking and communication equipment, and robustness is among the most important design objectives An effective approach for reducing the impact of Single Event Upset can lead to higher mean-time-to- failure(MTTF), increased quality of service, and reduced maintenance cost

4 Single Event Upset (SEU) Single Event Upsets (SEUs) : one of the main causes of reliability reduction caused by charge particle strikes due to cosmic radiation which create soft errors Major effect on circuits : change the logic state of a static memory element Trend : SEU vulnerability is increasing with technology shrinking

5 SEU in FPGAs Most of the commercial FPGAs employ SRAM as their configuration memory elements for higher logic density and programming flexibility Three of the major memory elements in FPGAs : user flip-flop, block RAM, and configuration RAM

6 Single Event Upset in FPGA The circuit effect of SEUs in a FPGA is permanent until the FPGA is re-programmed  Interconnect :  Logic : SEU on Configuration RAM is much more critical!

7 Demand for In-Place Reliability Optimizations Triple Modular Redundancy (TMR) is the most popular fault tolerant technique, but it requires more than 3X overhead on power, area, and cost For non-mission critical applications, such as communication systems, robustness improvement with little or no overhead is highly demanded In-place optimization techniques provide reliability improvement while preserving circuit placement and routing, and therefore the overhead is minimal

8 In-Place Resyntheses Flow Mitigation after placement and routing without change of placement and routing (and no change on design closure) Design Entry Logic Synthesis Map Bitstream Placement and Routing In-Place Decomposition (IPD) In-Place LUT Polarity Inversion (IPV) In-Place Resyntheses

9 Outline Introduction In-Place Decomposition (IPD) In-Place LUT Polarity Inversion (IPV) Experimental Results Conclusions & Future Works

10 Fault Metrics Soft Error Rate(SER) of a configuration SRAM bit: Mean-Time-To-Failure (MTTF) System level measurement of reliability For single fault model, MTTF  1/average(SER b )

11 In-Place LUT Decomposition Leveraging the dual-output feature of LUT architecture and the built-in carry chains Dual-output 6LUT Xilinx Virtex-5 6-input LUT architecture

12 Original LUT Decomposed LUT Decomposition LUT Decomposition Decomposition : F = C( F1, F2, ……, Fn ) (C is the converging logic function)

13 Example 1 : In-Place Duplication The average SER of the LUT is : ( S 0 +……+ S 31 )/32 5-input AND function InputOutputSER S0S S1S S2S S S 31 …… 5-input ……

14 InputOutputSER S0S S1S S2S S S 31 The average SER of the LUT is reduced to (2* S 31 )/32 Covered …… 0 -> 1 0 …… InputOutputSER S0S S1S S2S S S 31 …… Covered Example 1 : In-Place Duplication

15 InputOutputSER 0000AS AS AS AS 7 The number of SRAM bits used is reduced from 32 to 12, and the SERs of unused bits are 0 The average SER is also reduced due to logic masking of the converging logic …… InputOutputSER 000BS 0 010BS 1 100BS 2 111BS 3 Example 2 : In-Place Decomposition

16 Outline Introduction In-Place Decomposition (IPD) In-Place LUT Polarity Inversion (IPV) Experimental Results Conclusions & Future Works

17 Fault Masking for MUX Fault is masked when logic(i) = logic(j) SEU on a routing MUX

18 Example of Fault Masking SER(b k )=( v(i) v(j) ) · observ(m) observ(m) is the fault observability at MUX m : the probability of the fault that can be propagated to the primary outputs

19 LUT Polarity Inversion Polarity can be determined independently for each input and the output of an LUT LUT inversion Fanout adjustment

20 Inversion to Reduce SER SER: 1-0.9* *0.8=0.74 SER: 1-0.9* *0.2=0.26

21 Outline Introduction In-Place Decomposition (IPD) In-Place LUT Polarity Inversion (IPV) Experimental Results Conclusions & Future Works

22 Improvement by IPD LUT-LevelChip-level ABCIPDABCIPD alu40.34%0.11%0.45%3.23% apex20.29%0.04%0.33%2.67% apex41.16%0.25%1.41%10.63% des1.42%1.01%2.43%13.95% ex %0.29%1.53%11.60% exp5p0.73%0.24%0.97%7.06% misex30.55%0.10%0.65%5.08% pdc0.91%0.11%1.02%8.51% seq0.63%0.11%0.74%5.78% spla1.14%0.16%1.30%10.67% SER Ratio MTTF Imp IPV increase LUT-level MTTF by 4.52x, and chip-level MTTF by 1.07x (due to dominance of interconnects) SER reduction for MCNC benchmarks mapped to 6-input LUTs

23 Improvement by IPV IPV on average increases chip-level MTTF by 3.07X Less than 50% LUTs need to be inverted InterconnectChip-level ABCIPVABCIPV alu43.06%1.54%3.40%0.88% apex22.61%0.70%2.90%1.04% apex410.44%2.13%11.60%6.37% des12.78%11.71%14.20%13.03% ex %1.50%12.40%4.40% exp5p6.57%3.46%7.30%4.10% misex34.95%1.66%5.50%2.20% pdc8.19%0.65%9.10%1.24% seq5.67%1.67%6.30%1.28% spla10.26%0.73%11.40%1.47% SER Ratio MTTF Imp SER for MCNC benchmarks mapped to 6-input LUTs

24 Improvement by Combined Algorithms Combined Algorithms LUT LevelChip Level IPF + IPD66.53%19.63% IPF + IPV14.76%65.30% IPD + IPV76.06%67.48% IPF + IPD + IPV66.53%70.53% IPF+IPD+IPV reduces chip-level SER by 70.53%  3.39x chip-level MTTF increase Averaged SER reduction for MCNC benchmarks mapped to 6-input LUTs Zhe Feng, Naifeng Jing and Lei He, “IPF: In-Place X-Filling to Migrate Soft Errors in SRAM-Based FPGAS,” FPL 2011

25 Conclusions & Future Works Proposed two robust resynthesis techniques, In-Place Decomposition(IPD) for logic and In-Place LUT Polarity Inversion(IPV) for interconnect, to improve circuit robustness without global overhead We show on average 3.39X MTTF improvement on the MCNC benchmark circuits when combining IPD, IPV, and IPF In the future, we will develop more in-place resynthesis techniques and investigate the interaction among different techniques

26 Thank you!


Download ppt "Roy Lee Advisor: Lei He October 26, 2011 1 SEU Mitigation for FPGA-based Systems."

Similar presentations


Ads by Google