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Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power Hao Yu, Yiyu Shi and Lei He Electrical Engineering Dept. UCLA, USA Partially supported by NSF and UC-MICRO fund from Intel Tanay Karnik Circuit Research Lab Intel, USA

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2 New Solution for High-performance Integration n 2D SoC design has limited density and interconnect performance n Potential solution: 3D Integration [Banerjee-Saraswart:IEEE’01] l Fabrication Technologies: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth l Inter-layer via plays a crucial role in signaling, power delivery and heat- removal

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3 Thermal Challenges in 3D ICs n Temperature increases along third dimension l Inter-layer dielectric layers are poor thermal conductors 150c 135c 100c 70c 40c n High temperature affects interconnect and device reliability and leads to variations to timing n Thermal analysis and thermal-aware design for 3D ICs becomes a need

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4 Via Planning Problem n Motivation l Inter-layer vias are good thermal-conductor to remove heat l Inter-layer vias take additional chip area and routing resource n Previous work l Iterative via planning during placement [Goplen-Sapatnekar:ISPD’05] l Multilevel alternating direction via planning during routing [Zhang- Cong:ICCAD’05] l Both use steady-state analysis and assume a maximum-thermal power, and may lead to over-design n Primary contributions of our work l Minimize a thermal violation integral considering transient temperature l Develop an efficient sensitivity-driven sequential programming with use of macromodel

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5 Outline n Background and Problem Formulation n Structured and Parameterized Macromodel n Sequential Optimization n Experimental Results n Conclusions

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6 Thermal Model Overview Temperature Voltage state variables (x(t)) Thermal-Power Input Current sources (u(t)) Thermal conductance Electrical conductance (G) Thermal capacitanceElectrical capacitance (C) n Electric and thermal systems can be described in MNA (modified nodal analysis) equation n Via conductance gi and capacitance ci are both proportional to size Ai or density (Ai/a) (a is unit via area) l It can be parametrically added into MNA equation n Electric and thermal duality

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7 Steady State Model and Analysis n Steady-state temperature can be obtained by directly solving a time-invariant linear equation R n Active-device and inter-dielectric layers are discretized into tiles l Tiles connected by thermal resistance l Heat sources modeled as time-invariant current sources

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8 Transient Model and Analysis n Transient temperature can be obtained by solving a time- variant linear equation RC n Tiles connected by thermal resistance and thermal capacitance n Heat sources modeled as time-variant current sources

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9 Thermal Power Variation and Analysis n Different workloads and dynamic power management introduces temporally and spatially power variations l Thermal power is the runtime averaging of cycle-accurate power, and is not a constant spatially and temporally n Steady-state analysis needs to assume a maximum thermal power simultaneously for all regions l It seldom happens that each part of the chip achieves their maximum simultaneously, and can result in an over-design n Transient analysis is accurate but time-consuming l It calls for more accurate yet efficient transient thermal simulation during the design automation

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10 Thermal Violation Integral n Thermal violation is temperature overshoot for a long enough period, so maximum temperature is not a good Figure of Merit (FOM) Thermal-violation integral as FOM f k (A) is more accurate Time-domain transient temperature ( y ) integral over defined ceiling temperature ( T ceiling ) for a long enough period ( t 0 ~ t p ) at ith tile FOM f(A) for a group ( K ) of critical tiles A is a via density vector

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11 Problem Formulation Find a via density vector A to minimize the thermal violation integral under global/local routing congestion constraints n Two keys to efficiently solve this problem l Efficient models to transient response, and its first-order and second-order sensitivity with respect to via density l Efficient yet effective mathematic programming Global constraint Local constraint

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12 Outline n Background and Problem Formulation n Structured and Parameterized Macromodel n Sequential Optimization n Experimental Results n Conclusions

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13 Macromodel by Moment Matching large linear network … small linear network n Krylov-subspace based projection can reduce model size and preserve accuracy by matching moments of inputs [Odabasioglu-Celik-Pileggi:TCAD’98] l Flat projection does not preserve block matrix structure such as sparsity l Reduced macromodel does not contain sensitivity information for design automation

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14 Parameterization (I) The inserted location is described by adjacent matrix X The via density ( Ai ) is parameterized and added into MNA 1 2 34 5 6 78 1 2 3 4 5 6 7 8 1-1 0 0 0 1 0 0 0 X(2,6)= Need to separate sensitivity from nominal response

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15 Parameterization (II) Expand state variables x(A 1,…A K,s) by Taylor expansion w.r.t. A i (up to second order) l x^(0), x^(1), and x^(2) are nominal values, first-order and second-order sensitivities n Expanded system has lower-triangular structure n System size is enlarged and needs to be reduced by projection l Traditional flat projection can not separate the nominal state variables and their sensitivities [Li-Pileggi:ICCAD’04] l This can be solved by a structure-preserved projection [Yu-He-Tan:BMAS’05]

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16 Structured Projection (I) n Block-diagonally partition the projection matrix by the size of nominal state- variable, first-order sensitivity, and second- order sensitivity n Use structured projection can result in a reduced triangular system with nominal value and sensitivities to be solved independently

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17 Structured Projection (II) n Nominal response, and sensitivity can be solved separately and efficiently l The reduced model is sparse There is only one LU-factorization of the reduced diagonal block G 0 +(1/h)C 0 n Generated sensitivities can be used in any gradient based optimization n Time-domain transient response can be solved using Backward-Euler method

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18 Outline n Background and Problem Formulation n Structured and Parameterized Macromodel n Sequential Optimization n Experimental Results n Conclusions

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19 Sequential Approximation of Objective Function The objective function f(A) could be approximated Find ( ΔA ) to minimize f lp or f qp during each step n The objective function becomes semi-definite when integration is approximated by a discretized summation [Visweswariah:TCAD’00] l Sequential programming converges for convex-programming problems, and still has good convergence in semi-definite problems

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20 Sensitivity Calculation n Direct sensitivity calculation for objective function n Structured and parameterized reduction provides an efficient calculation of both nominal value and sensitivity The via density vector A can be efficiently updated during each iteration n The computation cost could be further reduced when an adjoint Lagrangian method is used to calculate sensitivity [Visweswariah:TCAD’00]

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21 Outline n Background and Problem Formulation n Structured and Parameterized Macromodel n Sequential Optimization n Experimental Results n Conclusions

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22 Experiment Settings n A modest 3D stacking with 1-heat-sink, 2-die- layer, 2-dielectric-layer is assumed, each extracted as RC mesh interconnected by RC- pair for via n Clock gating is assumed with a period of 250ms n Reduction algorithm assumes SIMO (single- input-multiple-output) reduction when the number of inputs is large n Compare our method (SP-Macro) with Steady- state solution

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23 Accuracy of Reduced Macromodel n Transient temperature responses of exact and SP-MACRO models at port 3, 18, and 58 of top layer with step-response input l The responses of macromodels are visually identical to those exact models

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24 Optimization Profile by SQP n Temperature reduction at selected location during the procedure of via-allocation by SQP l The allocated via results in a transient temperature meeting the targeted ceiling temperature 52C

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25 Temperature Map n Temperature maps before and after the via allocation at the top layer l The maximum temperature before allocation is about 150C l The temperature after allocation meets the targeted ceiling temperature 52C

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26 Allocated-via and Runtime Comparison n Compared to steady-state solution l SP-MACRO has smaller simulation and planning time when increasing circuit size u It reduces the runtime by 126X l SP-MACRO is more accurate to predict the via insertion u It reduces the inserted via number by 2.04X Total/ critical tile Total via Constraint Original/ ceiling T Steady-state by direct solution Transient by SP-MACRO Solve- dc(s) Solve- tran(s) Allo-viaRedu- ckt(s) Solve- sens(s) Qp/lp- plan (s) Allo-via 256/30704120/401.6410.274400.120.190.15360 1024/602818120/4012.62130.1222811.080.960.421609 4096/805980140/50341.133872.98562012.926.281.923217 8192/1008218140/507809.12NA802146.2716.928.984382 16384/12018000160/60NA 17600120.89101.2323.659280 32768/20024000160/60NA 23800262.12257.2142.7511660

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27 Conclusions n Via planning based on the transient thermal analysis reduces via umber by 2.04x compared to the steady-state thermal analysis n An efficient via planning algorithm is developed l Structured and parameterized model reduction provides both nominal values and sensitivities l Sequential linear/quadratic programming minimizes the thermal-violation integral n SP-MACRO is further extended for l Simultaneous power and thermal integrity driven via planning [Yu-Ho-He:ICCAD’06]

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